1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1994-1998 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_SIMBA_H 28*0Sstevel@tonic-gate #define _SYS_PCI_SIMBA_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * This files contains info specific to Simba (pci to pci bridge) 38*0Sstevel@tonic-gate * The rest of info common to simba and DecNet are in "pci.h" 39*0Sstevel@tonic-gate */ 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate /* 42*0Sstevel@tonic-gate * Simba configuration space registers. 43*0Sstevel@tonic-gate */ 44*0Sstevel@tonic-gate #define PCI_BCNF_SECSTATUS 0x1e /* secondary status */ 45*0Sstevel@tonic-gate 46*0Sstevel@tonic-gate /* 47*0Sstevel@tonic-gate * Simba device specific registers. 48*0Sstevel@tonic-gate */ 49*0Sstevel@tonic-gate #define PCI_BCNF_MATER_RETRY_LIMIT 0xc0 /* primary master retry limit */ 50*0Sstevel@tonic-gate #define PCI_BCNF_DMA_AFSR 0xc8 /* dma afsr */ 51*0Sstevel@tonic-gate #define PCI_BCNF_DMA_AFAR 0xd0 /* dma afar */ 52*0Sstevel@tonic-gate #define PCI_BCNF_PIOTGT_RTY_LIMIT 0xd8 /* pio target retry limit */ 53*0Sstevel@tonic-gate #define PCI_BCNF_PIOTGT_LATE_TIMER 0xd9 /* pio target retry limit */ 54*0Sstevel@tonic-gate #define PCI_BCNF_DMATGT_RTY_LIMIT 0xda /* dma target retry limit */ 55*0Sstevel@tonic-gate #define PCI_BCNF_DMATGT_LATE_TIMER 0xdb /* dma target retry limit */ 56*0Sstevel@tonic-gate #define PCI_BCNF_TGT_RETRY_LIMIT 0xdc /* primary master retry limit */ 57*0Sstevel@tonic-gate #define PCI_BCNF_SECBRIDGE_CTL 0xdd /* secondary bridge control */ 58*0Sstevel@tonic-gate #define PCI_BCNF_ADDR_MAP 0xdf /* address map */ 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate /* 61*0Sstevel@tonic-gate * Psycho compatible registers. 62*0Sstevel@tonic-gate */ 63*0Sstevel@tonic-gate #define PCI_BCNF_CTL_STAT 0xe0 /* control-status */ 64*0Sstevel@tonic-gate #define PCI_BCNF_PIO_AFSR 0xe8 /* pio afsr */ 65*0Sstevel@tonic-gate #define PCI_BCNF_PIO_AFAR 0xf0 /* pio afar */ 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate /* 68*0Sstevel@tonic-gate * Simba device specific registers. 69*0Sstevel@tonic-gate */ 70*0Sstevel@tonic-gate #define PCI_BCNF_DIAGNOSTICS 0xf8 /* diagnostics */ 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate 73*0Sstevel@tonic-gate /* 74*0Sstevel@tonic-gate * primary/secondary timer reg mask(addrs = 0x0d/0x1b). 75*0Sstevel@tonic-gate */ 76*0Sstevel@tonic-gate #define PCI_LATENCY_TMR_LO 0x7 /* read only part, 0x0 */ 77*0Sstevel@tonic-gate #define PCI_LATENCY_TMR_HI 0xf8 /* programable part */ 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate /* 80*0Sstevel@tonic-gate * PCI secondary status register bits. 81*0Sstevel@tonic-gate * All bit definitions are the same as primary status register, 82*0Sstevel@tonic-gate * but the meaning of bit 14 relates to secondary bus. 83*0Sstevel@tonic-gate */ 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate /* 87*0Sstevel@tonic-gate * Secondary control bit defines(addrs = 0xdd). 88*0Sstevel@tonic-gate */ 89*0Sstevel@tonic-gate #define PCI_SEC_CNTL_PIO_PREF 0x1 /* prefetch dma reads as pio */ 90*0Sstevel@tonic-gate #define PCI_SEC_CNTL_CONVT_MRM 0x2 /* convert mem multiple read */ 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate /* 93*0Sstevel@tonic-gate * Psycho ctrl/status reg bit defines(addrs = 0xe0). 94*0Sstevel@tonic-gate */ 95*0Sstevel@tonic-gate #define PCI_PSYCHO_SLOT_ENAM_MASK 0xf /* slot arbiter enable mask */ 96*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_ERRINIT_ENAB 0x100 /* 1=forward SERR to primary */ 97*0Sstevel@tonic-gate #define PCI_PSYCHO_WAKEUP_ENAB 0x200 /* not used, reads as 0 */ 98*0Sstevel@tonic-gate #define PCI_PSYCHO_SBH_INT_ENAB 0x400 /* not used, reads as 0 */ 99*0Sstevel@tonic-gate #define PCI_PSYCHO_SLOT_PRIORITY 0xf0000 /* slot arb priority mask */ 100*0Sstevel@tonic-gate #define PCI_PSYCHO_CPU_PRIORITY 0x100000 /* pio arb priority (simba) */ 101*0Sstevel@tonic-gate #define PCI_PSYCHO_PBUS_PARK_ENAB 0x200000 /* pci bus parking enable */ 102*0Sstevel@tonic-gate #define PCI_PSYCHO_INTER_ARB_ENAB 0x100000000 /* enable internal arb */ 103*0Sstevel@tonic-gate #define PCI_PSYCHO_PCI_SPEED 0x200000000 /* not used, reads as 0 */ 104*0Sstevel@tonic-gate #define PCI_PSYCHO_PCI_SYS_ERROR 0x800000000 /* set, if err on 2ndary */ 105*0Sstevel@tonic-gate #define PCI_PSYCHO_PCI_SBH_ERROR 0x1000000000 /* not used, reads as 0 */ 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate /* 108*0Sstevel@tonic-gate * Psycho AFSR reg bit defines(addrs = 0xe8). 109*0Sstevel@tonic-gate */ 110*0Sstevel@tonic-gate #define PCI_PSYCHO_ERR_NUM 0xff /* error index number */ 111*0Sstevel@tonic-gate #define PCI_PSYCHO_MID_MASK (0x1f<<25) /* mid mask, reads 0 */ 112*0Sstevel@tonic-gate #define PCI_PSYCHO_BLK (1<<31) /* block, reads 0 */ 113*0Sstevel@tonic-gate #define PCI_PSYCHO_BYTE_MASK (0xffff<<32) /* byte mask, reads 0 */ 114*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_APERR (1<<54) /* 2ndary adr par err */ 115*0Sstevel@tonic-gate #define PCI_PSYCHO_PRI_APERR (1<<55) /* pri addr par err */ 116*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_PERR (1<<56) /* 2nd data par err */ 117*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_RTRY_ERR (1<<57) /* 2nd retry err */ 118*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_TA_ERR (1<<58) /* 2nd tgt abort err */ 119*0Sstevel@tonic-gate #define PCI_PSYCHO_SEC_MA_ERR (1<<59) /* 2nd mstr abort err */ 120*0Sstevel@tonic-gate #define PCI_PSYCHO_PRI_PERR (1<<60) /* pri data par error */ 121*0Sstevel@tonic-gate #define PCI_PSYCHO_PRI_RTRY_ERR (1<<61) /* pri retry error */ 122*0Sstevel@tonic-gate #define PCI_PSYCHO_PRI_TA_ERR (1<<62) /* mstr tgt abort err */ 123*0Sstevel@tonic-gate #define PCI_PSYCHO_PRI_MA_ERR (1<<63) /* mstr mstr abrt err */ 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate /* 127*0Sstevel@tonic-gate * notice: In Simba, AFAR will log statring address of transaction with error 128*0Sstevel@tonic-gate * The byte offset will be logged in [7:0] of AFSR. 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate /* 132*0Sstevel@tonic-gate * Diagnostics reg bit defines(size=d word)(addrs = 0xf8). 133*0Sstevel@tonic-gate */ 134*0Sstevel@tonic-gate #define PCI_DIAG_IDMA_WDATA_PAR 0x1 /* invert dma wr data parity */ 135*0Sstevel@tonic-gate #define PCI_DIAG_IDMA_RDATA_PAR 0x2 /* invert dma rd data parity */ 136*0Sstevel@tonic-gate #define PCI_DIAG_IDMA_ADDR_PAR 0x4 /* invert dma addr parity */ 137*0Sstevel@tonic-gate #define PCI_DIAG_IPIO_WDATA_PAR 0x10 /* invert pio wr data parity */ 138*0Sstevel@tonic-gate #define PCI_DIAG_IPIO_RDATA_PAR 0x20 /* invert pio rd data parity */ 139*0Sstevel@tonic-gate #define PCI_DIAG_IPIO_ADDR_PAR 0x40 /* invert pio addr parity */ 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate /* 142*0Sstevel@tonic-gate * usefull defines. 143*0Sstevel@tonic-gate */ 144*0Sstevel@tonic-gate #define PCI_UNLIMITED_RETRY 0x0 /* unlimitted retry */ 145*0Sstevel@tonic-gate #define PCI_UNLIMITED_LATENCY 0x0 /* unlimitted latency */ 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate /* 148*0Sstevel@tonic-gate * vendor & device id for simba. 149*0Sstevel@tonic-gate */ 150*0Sstevel@tonic-gate #define PCI_SIMBA_VENID 0x108e /* vendor id for simba */ 151*0Sstevel@tonic-gate #define PCI_SIMBA_DEVID 0x5000 /* device id for simba */ 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate /* 154*0Sstevel@tonic-gate * programming interface for simba. 155*0Sstevel@tonic-gate */ 156*0Sstevel@tonic-gate #define PCI_SIMBA_PRI 0x0 /* prog interface for simba */ 157*0Sstevel@tonic-gate 158*0Sstevel@tonic-gate /* 159*0Sstevel@tonic-gate * master/secondary latency timer value. 160*0Sstevel@tonic-gate */ 161*0Sstevel@tonic-gate #define PCI_LATENCY_TIMER_VAL 0x28 /* timer value for simba */ 162*0Sstevel@tonic-gate 163*0Sstevel@tonic-gate /* 164*0Sstevel@tonic-gate * primary bus number for simba. 165*0Sstevel@tonic-gate */ 166*0Sstevel@tonic-gate #define PCI_BCNF_PRIBUS_NUM 0x0 /* primary bus # for simba */ 167*0Sstevel@tonic-gate 168*0Sstevel@tonic-gate /* 169*0Sstevel@tonic-gate * secondary bus number for simba. 170*0Sstevel@tonic-gate */ 171*0Sstevel@tonic-gate #define PCI_BCNF_SECBUS_NUM_ONE 0x1 /* secondary bus number one */ 172*0Sstevel@tonic-gate #define PCI_BCNF_SECBUS_NUM_TWO 0x2 /* secondary bus number two */ 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate #ifdef __cplusplus 176*0Sstevel@tonic-gate } 177*0Sstevel@tonic-gate #endif 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate #endif /* _SYS_PCI_SIMBA_H */ 180