1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_PBM_H 28*0Sstevel@tonic-gate #define _SYS_PCI_PBM_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #include <sys/types.h> 33*0Sstevel@tonic-gate #include <sys/dditypes.h> 34*0Sstevel@tonic-gate #include <sys/ontrap.h> 35*0Sstevel@tonic-gate #include <sys/callb.h> 36*0Sstevel@tonic-gate 37*0Sstevel@tonic-gate #ifdef __cplusplus 38*0Sstevel@tonic-gate extern "C" { 39*0Sstevel@tonic-gate #endif 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate /* 42*0Sstevel@tonic-gate * The following structure represents the pci configuration header 43*0Sstevel@tonic-gate * for a psycho or schizo PBM. 44*0Sstevel@tonic-gate */ 45*0Sstevel@tonic-gate typedef struct config_header config_header_t; 46*0Sstevel@tonic-gate struct config_header { 47*0Sstevel@tonic-gate volatile uint16_t ch_vendor_id; 48*0Sstevel@tonic-gate volatile uint16_t ch_device_id; 49*0Sstevel@tonic-gate volatile uint16_t ch_command_reg; 50*0Sstevel@tonic-gate volatile uint16_t ch_status_reg; 51*0Sstevel@tonic-gate volatile uint8_t ch_revision_id_reg; 52*0Sstevel@tonic-gate volatile uint8_t ch_programming_if_code_reg; 53*0Sstevel@tonic-gate volatile uint8_t ch_sub_class_reg; 54*0Sstevel@tonic-gate volatile uint8_t ch_base_class_reg; 55*0Sstevel@tonic-gate volatile uint8_t ch_cache_line_size_reg; 56*0Sstevel@tonic-gate volatile uint8_t ch_latency_timer_reg; 57*0Sstevel@tonic-gate volatile uint8_t ch_header_type_reg; 58*0Sstevel@tonic-gate }; 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate typedef enum { PBM_SPEED_33MHZ, PBM_SPEED_66MHZ } pbm_speed_t; 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate /* 63*0Sstevel@tonic-gate * Bit fields of ch_status_reg for cmn_err's %b 64*0Sstevel@tonic-gate */ 65*0Sstevel@tonic-gate #define PCI_STATUS_BITS "\020\ 66*0Sstevel@tonic-gate \11signaled-parity-error\ 67*0Sstevel@tonic-gate \14signaled-target-abort\ 68*0Sstevel@tonic-gate \15received-target-abort\ 69*0Sstevel@tonic-gate \16received-master-abort\ 70*0Sstevel@tonic-gate \17signaled-system-error\ 71*0Sstevel@tonic-gate \20detected-parity-error" 72*0Sstevel@tonic-gate 73*0Sstevel@tonic-gate /* 74*0Sstevel@tonic-gate * pbm block soft state structure: 75*0Sstevel@tonic-gate * 76*0Sstevel@tonic-gate * Each pci node has its own private pbm block structure. 77*0Sstevel@tonic-gate */ 78*0Sstevel@tonic-gate struct pbm { 79*0Sstevel@tonic-gate pci_t *pbm_pci_p; /* link back to pci soft state */ 80*0Sstevel@tonic-gate pbm_speed_t pbm_speed; /* PCI bus speed (33 or 66 Mhz) */ 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate /* 83*0Sstevel@tonic-gate * PBM control and error registers: 84*0Sstevel@tonic-gate */ 85*0Sstevel@tonic-gate volatile uint64_t *pbm_ctrl_reg; 86*0Sstevel@tonic-gate volatile uint64_t *pbm_async_flt_status_reg; 87*0Sstevel@tonic-gate volatile uint64_t *pbm_async_flt_addr_reg; 88*0Sstevel@tonic-gate volatile uint64_t *pbm_diag_reg; 89*0Sstevel@tonic-gate volatile uint64_t *pbm_estar_reg; 90*0Sstevel@tonic-gate volatile uint64_t *pbm_pcix_err_stat_reg; 91*0Sstevel@tonic-gate volatile uint64_t *pbm_pci_ped_ctrl; 92*0Sstevel@tonic-gate 93*0Sstevel@tonic-gate /* 94*0Sstevel@tonic-gate * PCI configuration header block for the PBM: 95*0Sstevel@tonic-gate */ 96*0Sstevel@tonic-gate config_header_t *pbm_config_header; 97*0Sstevel@tonic-gate 98*0Sstevel@tonic-gate /* 99*0Sstevel@tonic-gate * Memory address range on this PBM used to determine DMA on this pbm 100*0Sstevel@tonic-gate */ 101*0Sstevel@tonic-gate iopfn_t pbm_base_pfn; 102*0Sstevel@tonic-gate iopfn_t pbm_last_pfn; 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate /* 105*0Sstevel@tonic-gate * pbm Interrupt Mapping Register save area 106*0Sstevel@tonic-gate */ 107*0Sstevel@tonic-gate uint64_t pbm_imr_save; 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate /* To save CDMA interrupt state across CPR */ 110*0Sstevel@tonic-gate uint64_t pbm_cdma_imr_save; 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate /* 113*0Sstevel@tonic-gate * pbm error interrupt priority: 114*0Sstevel@tonic-gate */ 115*0Sstevel@tonic-gate ddi_iblock_cookie_t pbm_iblock_cookie; 116*0Sstevel@tonic-gate 117*0Sstevel@tonic-gate /* 118*0Sstevel@tonic-gate * Consistent Mode DMA Sync 119*0Sstevel@tonic-gate */ 120*0Sstevel@tonic-gate uint64_t pbm_sync_reg_pa; /* pending reg for xmits/tomatillo */ 121*0Sstevel@tonic-gate ib_ino_t pbm_sync_ino; 122*0Sstevel@tonic-gate 123*0Sstevel@tonic-gate volatile uint32_t pbm_cdma_flag; 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate /* 126*0Sstevel@tonic-gate * DMA sync lock to serialize access to sync hardware. 127*0Sstevel@tonic-gate * Used for schizo (>= 2.3) and xmits. Tomatillo does not require 128*0Sstevel@tonic-gate * serialization. 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate kmutex_t pbm_sync_mutex; 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate /* 133*0Sstevel@tonic-gate * support for ddi_poke: 134*0Sstevel@tonic-gate */ 135*0Sstevel@tonic-gate on_trap_data_t *pbm_ontrap_data; 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate kmutex_t pbm_pokefault_mutex; 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate /* 140*0Sstevel@tonic-gate * Support for cautious IO accesses 141*0Sstevel@tonic-gate */ 142*0Sstevel@tonic-gate ddi_acc_handle_t pbm_excl_handle; 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate /* 145*0Sstevel@tonic-gate * Support for PCI bus quiesce/unquiesce 146*0Sstevel@tonic-gate */ 147*0Sstevel@tonic-gate uint64_t pbm_saved_ctrl_reg; 148*0Sstevel@tonic-gate uint_t pbm_quiesce_count; 149*0Sstevel@tonic-gate callb_id_t pbm_panic_cb_id; 150*0Sstevel@tonic-gate callb_id_t pbm_debug_cb_id; 151*0Sstevel@tonic-gate uint64_t pbm_anychild_cfgpa; 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate /* 154*0Sstevel@tonic-gate * Sun Fire 15k PIO limiting semaphore 155*0Sstevel@tonic-gate */ 156*0Sstevel@tonic-gate uint32_t pbm_pio_limit; 157*0Sstevel@tonic-gate volatile uint32_t pbm_pio_counter; 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate #define PBM_NAMESTR_BUFLEN 64 160*0Sstevel@tonic-gate /* driver name & instance */ 161*0Sstevel@tonic-gate char pbm_nameinst_str[PBM_NAMESTR_BUFLEN]; 162*0Sstevel@tonic-gate 163*0Sstevel@tonic-gate /* nodename & node_addr */ 164*0Sstevel@tonic-gate char *pbm_nameaddr_str; 165*0Sstevel@tonic-gate }; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate /* 168*0Sstevel@tonic-gate * forward declarations (object creation and destruction): 169*0Sstevel@tonic-gate */ 170*0Sstevel@tonic-gate 171*0Sstevel@tonic-gate extern void pbm_create(pci_t *pci_p); 172*0Sstevel@tonic-gate extern void pbm_destroy(pci_t *pci_p); 173*0Sstevel@tonic-gate extern void pbm_configure(pbm_t *pbm_p); 174*0Sstevel@tonic-gate extern void pbm_clear_error(pbm_t *pbm_p); 175*0Sstevel@tonic-gate extern void pbm_enable_intr(pbm_t *pbm_p); 176*0Sstevel@tonic-gate extern void pbm_suspend(pbm_t *pbm_p); 177*0Sstevel@tonic-gate extern void pbm_resume(pbm_t *pbm_p); 178*0Sstevel@tonic-gate extern void pbm_intr_dist(void *arg); 179*0Sstevel@tonic-gate extern int pbm_register_intr(pbm_t *pbm_p); 180*0Sstevel@tonic-gate extern int pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena, 181*0Sstevel@tonic-gate pbm_errstate_t *pbm_err_p); 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate #ifdef __cplusplus 184*0Sstevel@tonic-gate } 185*0Sstevel@tonic-gate #endif 186*0Sstevel@tonic-gate 187*0Sstevel@tonic-gate #endif /* _SYS_PCI_PBM_H */ 188