1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_IOMMU_H 28*0Sstevel@tonic-gate #define _SYS_PCI_IOMMU_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #include <sys/vmem.h> 37*0Sstevel@tonic-gate 38*0Sstevel@tonic-gate typedef uint64_t dvma_addr_t; 39*0Sstevel@tonic-gate typedef uint64_t dma_bypass_addr_t; 40*0Sstevel@tonic-gate typedef uint64_t dma_peer_addr_t; 41*0Sstevel@tonic-gate typedef uint16_t dvma_context_t; 42*0Sstevel@tonic-gate typedef uint64_t window_t; 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate /* 45*0Sstevel@tonic-gate * The following typedef's represents the types for DMA transactions 46*0Sstevel@tonic-gate * and corresponding DMA addresses supported by psycho/schizo. 47*0Sstevel@tonic-gate */ 48*0Sstevel@tonic-gate typedef enum { IOMMU_XLATE, IOMMU_BYPASS, PCI_PEER_TO_PEER } iommu_dma_t; 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate /* 51*0Sstevel@tonic-gate * The following macros define the iommu page size and related operations. 52*0Sstevel@tonic-gate */ 53*0Sstevel@tonic-gate #define IOMMU_PAGE_SHIFT 13 54*0Sstevel@tonic-gate #define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT) 55*0Sstevel@tonic-gate #define IOMMU_PAGE_MASK ~(IOMMU_PAGE_SIZE - 1) 56*0Sstevel@tonic-gate #define IOMMU_PAGE_OFFSET (IOMMU_PAGE_SIZE - 1) 57*0Sstevel@tonic-gate #define IOMMU_PTOB(x) (((uint64_t)(x)) << IOMMU_PAGE_SHIFT) 58*0Sstevel@tonic-gate #define IOMMU_BTOP(x) ((x) >> IOMMU_PAGE_SHIFT) 59*0Sstevel@tonic-gate #define IOMMU_BTOPR(x) IOMMU_BTOP((x) + IOMMU_PAGE_OFFSET) 60*0Sstevel@tonic-gate 61*0Sstevel@tonic-gate /* 62*0Sstevel@tonic-gate * control register decoding 63*0Sstevel@tonic-gate */ 64*0Sstevel@tonic-gate /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 65*0Sstevel@tonic-gate #define IOMMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 66*0Sstevel@tonic-gate #define IOMMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 67*0Sstevel@tonic-gate #define IOMMU_DARWIN_BOGUS_TSBSIZE 7 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate /* 70*0Sstevel@tonic-gate * boiler plate for tte (everything except the pfn) 71*0Sstevel@tonic-gate */ 72*0Sstevel@tonic-gate #define MAKE_TTE_TEMPLATE(pfn, mp) (COMMON_IOMMU_TTE_V | \ 73*0Sstevel@tonic-gate (pf_is_memory(pfn) ? COMMON_IOMMU_TTE_C : 0) | \ 74*0Sstevel@tonic-gate ((mp->dmai_rflags & DDI_DMA_READ) ? COMMON_IOMMU_TTE_W : 0) | \ 75*0Sstevel@tonic-gate ((mp->dmai_rflags & DDI_DMA_CONSISTENT) ? 0 : COMMON_IOMMU_TTE_S)) 76*0Sstevel@tonic-gate #define TTE_IS_INVALID(tte) (((tte) & COMMON_IOMMU_TTE_V) == 0x0ull) 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate /* 79*0Sstevel@tonic-gate * The following macros define the address ranges supported for DVMA 80*0Sstevel@tonic-gate * and iommu bypass transfers. 81*0Sstevel@tonic-gate */ 82*0Sstevel@tonic-gate #define COMMON_IOMMU_BYPASS_BASE 0xFFFC000000000000ull 83*0Sstevel@tonic-gate #define COMMON_IOMMU_BYPASS_END 0xFFFC00FFFFFFFFFFull 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate /* 86*0Sstevel@tonic-gate * For iommu bypass addresses, bit 43 specifies cacheability. 87*0Sstevel@tonic-gate */ 88*0Sstevel@tonic-gate #define COMMON_IOMMU_BYPASS_NONCACHE 0x0000080000000000ull 89*0Sstevel@tonic-gate 90*0Sstevel@tonic-gate /* 91*0Sstevel@tonic-gate * Generic iommu definitions and types: 92*0Sstevel@tonic-gate */ 93*0Sstevel@tonic-gate #define IOMMU_TLB_ENTRIES 16 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate /* 96*0Sstevel@tonic-gate * The following macros are for loading and unloading iotte 97*0Sstevel@tonic-gate * entries. 98*0Sstevel@tonic-gate */ 99*0Sstevel@tonic-gate #define COMMON_IOMMU_TTE_SIZE 8 100*0Sstevel@tonic-gate #define COMMON_IOMMU_TTE_V 0x8000000000000000ull 101*0Sstevel@tonic-gate #define COMMON_IOMMU_TTE_S 0x1000000000000000ull 102*0Sstevel@tonic-gate #define COMMON_IOMMU_TTE_C 0x0000000000000010ull 103*0Sstevel@tonic-gate #define COMMON_IOMMU_TTE_W 0x0000000000000002ull 104*0Sstevel@tonic-gate #define COMMON_IOMMU_INVALID_TTE 0x0000000000000000ull 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate /* 107*0Sstevel@tonic-gate * Tomatillo's micro TLB bug. errata #82 108*0Sstevel@tonic-gate */ 109*0Sstevel@tonic-gate typedef struct dvma_unbind_req { 110*0Sstevel@tonic-gate uint32_t dur_base; 111*0Sstevel@tonic-gate uint_t dur_npg; 112*0Sstevel@tonic-gate uint_t dur_flags; /* = dmai_flags & DMAI_FLAGS_VMEMCACHE */ 113*0Sstevel@tonic-gate } dvma_unbind_req_t; 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate /* 116*0Sstevel@tonic-gate * iommu block soft state structure: 117*0Sstevel@tonic-gate * 118*0Sstevel@tonic-gate * Each pci node may share an iommu block structure with its peer 119*0Sstevel@tonic-gate * node of have its own private iommu block structure. 120*0Sstevel@tonic-gate */ 121*0Sstevel@tonic-gate typedef struct iommu iommu_t; 122*0Sstevel@tonic-gate struct iommu { 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate pci_t *iommu_pci_p; /* link back to pci soft state */ 125*0Sstevel@tonic-gate int iommu_inst; /* ddi_get_instance(iommu_pci_p->pci_dip) */ 126*0Sstevel@tonic-gate 127*0Sstevel@tonic-gate volatile uint64_t *iommu_ctrl_reg; 128*0Sstevel@tonic-gate volatile uint64_t *iommu_tsb_base_addr_reg; 129*0Sstevel@tonic-gate volatile uint64_t *iommu_flush_page_reg; 130*0Sstevel@tonic-gate volatile uint64_t *iommu_flush_ctx_reg; /* schizo only */ 131*0Sstevel@tonic-gate volatile uint64_t *iommu_tfar_reg; /* tomatillo only */ 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate /* 134*0Sstevel@tonic-gate * virtual and physical addresses and size of the iommu tsb: 135*0Sstevel@tonic-gate */ 136*0Sstevel@tonic-gate uint64_t *iommu_tsb_vaddr; 137*0Sstevel@tonic-gate uint64_t iommu_tsb_paddr; 138*0Sstevel@tonic-gate uint_t iommu_tsb_entries; 139*0Sstevel@tonic-gate uint_t iommu_tsb_size; 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate /* 142*0Sstevel@tonic-gate * address ranges of dvma space: 143*0Sstevel@tonic-gate */ 144*0Sstevel@tonic-gate dvma_addr_t iommu_dvma_base; 145*0Sstevel@tonic-gate dvma_addr_t iommu_dvma_end; 146*0Sstevel@tonic-gate dvma_addr_t iommu_dvma_fast_end; 147*0Sstevel@tonic-gate dvma_addr_t dvma_base_pg; /* = IOMMU_BTOP(iommu_dvma_base) */ 148*0Sstevel@tonic-gate dvma_addr_t dvma_end_pg; /* = IOMMU_BTOP(iommu_dvma_end) */ 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate /* 151*0Sstevel@tonic-gate * address ranges of dma bypass space: 152*0Sstevel@tonic-gate */ 153*0Sstevel@tonic-gate dma_bypass_addr_t iommu_dma_bypass_base; 154*0Sstevel@tonic-gate dma_bypass_addr_t iommu_dma_bypass_end; 155*0Sstevel@tonic-gate 156*0Sstevel@tonic-gate /* 157*0Sstevel@tonic-gate * virtual memory map and callback id for dvma space: 158*0Sstevel@tonic-gate */ 159*0Sstevel@tonic-gate vmem_t *iommu_dvma_map; 160*0Sstevel@tonic-gate uintptr_t iommu_dvma_clid; 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate /* 163*0Sstevel@tonic-gate * fields for fast dvma interfaces: 164*0Sstevel@tonic-gate */ 165*0Sstevel@tonic-gate ulong_t iommu_dvma_reserve; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate /* 168*0Sstevel@tonic-gate * dvma fast track page cache byte map 169*0Sstevel@tonic-gate */ 170*0Sstevel@tonic-gate uint8_t *iommu_dvma_cache_locks; 171*0Sstevel@tonic-gate uint_t iommu_dvma_addr_scan_start; 172*0Sstevel@tonic-gate 173*0Sstevel@tonic-gate /* 174*0Sstevel@tonic-gate * dvma context bitmap 175*0Sstevel@tonic-gate */ 176*0Sstevel@tonic-gate uint64_t *iommu_ctx_bitmap; 177*0Sstevel@tonic-gate 178*0Sstevel@tonic-gate /* 179*0Sstevel@tonic-gate * dvma debug 180*0Sstevel@tonic-gate */ 181*0Sstevel@tonic-gate kmutex_t dvma_debug_lock; 182*0Sstevel@tonic-gate uint32_t dvma_alloc_rec_index; 183*0Sstevel@tonic-gate uint32_t dvma_free_rec_index; 184*0Sstevel@tonic-gate uint32_t dvma_active_count; 185*0Sstevel@tonic-gate 186*0Sstevel@tonic-gate struct dvma_rec *dvma_alloc_rec; 187*0Sstevel@tonic-gate struct dvma_rec *dvma_free_rec; 188*0Sstevel@tonic-gate struct dvma_rec *dvma_active_list; 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate /* 191*0Sstevel@tonic-gate * tomatillo's micro TLB bug. errata #82 192*0Sstevel@tonic-gate */ 193*0Sstevel@tonic-gate dvma_unbind_req_t *iommu_mtlb_req_p; /* unbind requests */ 194*0Sstevel@tonic-gate uint32_t iommu_mtlb_maxpgs; /* GC threshold */ 195*0Sstevel@tonic-gate uint32_t iommu_mtlb_npgs; /* total page count */ 196*0Sstevel@tonic-gate uint32_t iommu_mtlb_nreq; /* total request count */ 197*0Sstevel@tonic-gate kmutex_t iommu_mtlb_lock; 198*0Sstevel@tonic-gate }; 199*0Sstevel@tonic-gate 200*0Sstevel@tonic-gate typedef struct pci_dvma_range_prop { 201*0Sstevel@tonic-gate uint32_t dvma_base; 202*0Sstevel@tonic-gate uint32_t dvma_len; 203*0Sstevel@tonic-gate } pci_dvma_range_prop_t; 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate #define IOMMU_PAGE_INDEX(iommu_p, dvma_pg) ((dvma_pg) - (iommu_p)->dvma_base_pg) 206*0Sstevel@tonic-gate #define IOMMU_PAGE_FLUSH(iommu_p, dvma_pg) \ 207*0Sstevel@tonic-gate *(iommu_p)->iommu_flush_page_reg = IOMMU_PTOB(dvma_pg) 208*0Sstevel@tonic-gate #define IOMMU_UNLOAD_TTE(iommu_p, pg_index) \ 209*0Sstevel@tonic-gate (iommu_p)->iommu_tsb_vaddr[pg_index] = COMMON_IOMMU_INVALID_TTE 210*0Sstevel@tonic-gate #define IOMMU_PAGE_TTEPA(iommu_p, dvma_pg) \ 211*0Sstevel@tonic-gate ((iommu_p)->iommu_tsb_paddr + (IOMMU_PAGE_INDEX(iommu_p, dvma_pg) << 3)) 212*0Sstevel@tonic-gate 213*0Sstevel@tonic-gate #define IOMMU_CONTEXT_BITS 12 214*0Sstevel@tonic-gate #define IOMMU_CTX_MASK ((1 << IOMMU_CONTEXT_BITS) - 1) 215*0Sstevel@tonic-gate #define IOMMU_TTE_CTX_SHIFT 47 216*0Sstevel@tonic-gate #define IOMMU_CTX2TTE(ctx) (((uint64_t)(ctx)) << IOMMU_TTE_CTX_SHIFT) 217*0Sstevel@tonic-gate #define IOMMU_TTE2CTX(tte) \ 218*0Sstevel@tonic-gate (((tte) >> (IOMMU_TTE_CTX_SHIFT - 32)) & IOMMU_CTX_MASK) 219*0Sstevel@tonic-gate #define MP2CTX(mp) IOMMU_TTE2CTX((uint32_t)(mp)->dmai_tte) 220*0Sstevel@tonic-gate 221*0Sstevel@tonic-gate /* dvma debug */ 222*0Sstevel@tonic-gate #define DVMA_DBG_ON(iommu_p) \ 223*0Sstevel@tonic-gate ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_on) 224*0Sstevel@tonic-gate #define DVMA_DBG_OFF(iommu_p) \ 225*0Sstevel@tonic-gate ((1ull << (iommu_p)->iommu_inst) & pci_dvma_debug_off) 226*0Sstevel@tonic-gate 227*0Sstevel@tonic-gate extern void pci_dvma_debug_fini(iommu_t *iommu_p); 228*0Sstevel@tonic-gate extern void pci_dvma_alloc_debug(iommu_t *iommu_p, char *address, uint_t len, 229*0Sstevel@tonic-gate ddi_dma_impl_t *mp); 230*0Sstevel@tonic-gate extern void pci_dvma_free_debug(iommu_t *iommu_p, char *address, uint_t len, 231*0Sstevel@tonic-gate ddi_dma_impl_t *mp); 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate /* dvma routines */ 234*0Sstevel@tonic-gate extern void iommu_map_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 235*0Sstevel@tonic-gate dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 236*0Sstevel@tonic-gate extern void iommu_unmap_pages(iommu_t *iommu_p, dvma_addr_t dvma_pg, 237*0Sstevel@tonic-gate uint_t npages); 238*0Sstevel@tonic-gate extern void iommu_remap_pages(iommu_t *iommu_p, ddi_dma_impl_t *mp, 239*0Sstevel@tonic-gate dvma_addr_t dvma_pg, size_t npages, size_t pfn_index); 240*0Sstevel@tonic-gate extern void iommu_map_window(iommu_t *iommu_p, 241*0Sstevel@tonic-gate ddi_dma_impl_t *mp, window_t window); 242*0Sstevel@tonic-gate extern void iommu_unmap_window(iommu_t *iommu_p, ddi_dma_impl_t *mp); 243*0Sstevel@tonic-gate 244*0Sstevel@tonic-gate /* iommu initialization routines */ 245*0Sstevel@tonic-gate extern void iommu_configure(iommu_t *iommu_p); 246*0Sstevel@tonic-gate extern void iommu_create(pci_t *pci_p); 247*0Sstevel@tonic-gate extern void iommu_destroy(pci_t *pci_p); 248*0Sstevel@tonic-gate extern uint_t iommu_tsb_size_encode(uint_t tsb_bytes); 249*0Sstevel@tonic-gate 250*0Sstevel@tonic-gate /* TSB allocate/free */ 251*0Sstevel@tonic-gate extern int pci_alloc_tsb(pci_t *pci_p); 252*0Sstevel@tonic-gate extern void pci_free_tsb(pci_t *pci_p); 253*0Sstevel@tonic-gate 254*0Sstevel@tonic-gate #ifdef __cplusplus 255*0Sstevel@tonic-gate } 256*0Sstevel@tonic-gate #endif 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate #endif /* _SYS_PCI_IOMMU_H */ 259