xref: /onnv-gate/usr/src/uts/sun4u/sys/pci/pci_ib.h (revision 10053:79ff8cfc9153)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
52973Sgovinda  * Common Development and Distribution License (the "License").
62973Sgovinda  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
22*10053SEvan.Yan@Sun.COM  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
230Sstevel@tonic-gate  * Use is subject to license terms.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #ifndef	_SYS_PCI_IB_H
270Sstevel@tonic-gate #define	_SYS_PCI_IB_H
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #ifdef	__cplusplus
300Sstevel@tonic-gate extern "C" {
310Sstevel@tonic-gate #endif
320Sstevel@tonic-gate 
330Sstevel@tonic-gate #include <sys/ddi_subrdefs.h>
34117Sschwartz #include <sys/pci_tools.h>
350Sstevel@tonic-gate 
360Sstevel@tonic-gate typedef uint8_t ib_ino_t;
370Sstevel@tonic-gate typedef uint16_t ib_mondo_t;
380Sstevel@tonic-gate typedef struct ib_ino_info ib_ino_info_t;
392973Sgovinda typedef struct ib_ino_pil ib_ino_pil_t;
400Sstevel@tonic-gate typedef uint8_t device_num_t;
410Sstevel@tonic-gate typedef uint8_t interrupt_t;
420Sstevel@tonic-gate 
430Sstevel@tonic-gate /*
440Sstevel@tonic-gate  * interrupt block soft state structure:
450Sstevel@tonic-gate  *
460Sstevel@tonic-gate  * Each pci node may share an interrupt block structure with its peer
470Sstevel@tonic-gate  * node or have its own private interrupt block structure.
480Sstevel@tonic-gate  */
490Sstevel@tonic-gate typedef struct ib ib_t;
500Sstevel@tonic-gate struct ib {
510Sstevel@tonic-gate 
520Sstevel@tonic-gate 	pci_t *ib_pci_p;	/* link back to pci soft state */
530Sstevel@tonic-gate 	pci_ign_t ib_ign;	/* interrupt group # */
540Sstevel@tonic-gate 
550Sstevel@tonic-gate 	/*
560Sstevel@tonic-gate 	 * PCI slot and onboard I/O interrupt mapping register blocks addresses:
570Sstevel@tonic-gate 	 */
580Sstevel@tonic-gate 	uintptr_t ib_slot_intr_map_regs;
590Sstevel@tonic-gate #define	ib_intr_map_regs	ib_slot_intr_map_regs
600Sstevel@tonic-gate 	uintptr_t ib_obio_intr_map_regs;
610Sstevel@tonic-gate 
620Sstevel@tonic-gate 	/*
630Sstevel@tonic-gate 	 * PCI slot and onboard I/O clear interrupt register block addresses:
640Sstevel@tonic-gate 	 */
650Sstevel@tonic-gate 	uintptr_t ib_slot_clear_intr_regs;
660Sstevel@tonic-gate 	uintptr_t ib_obio_clear_intr_regs;
670Sstevel@tonic-gate 
680Sstevel@tonic-gate 	/*
690Sstevel@tonic-gate 	 * UPA expansion slot interrupt mapping register addresses:
700Sstevel@tonic-gate 	 */
710Sstevel@tonic-gate 	volatile uint64_t *ib_upa_imr[2];
720Sstevel@tonic-gate 	uint64_t ib_upa_imr_state[2];
730Sstevel@tonic-gate 
740Sstevel@tonic-gate 	/*
750Sstevel@tonic-gate 	 * Interrupt retry register address:
760Sstevel@tonic-gate 	 */
770Sstevel@tonic-gate 	volatile uint64_t *ib_intr_retry_timer_reg;
780Sstevel@tonic-gate 
790Sstevel@tonic-gate 	/*
800Sstevel@tonic-gate 	 * PCI slot and onboard I/O interrupt state diag register addresses:
810Sstevel@tonic-gate 	 */
820Sstevel@tonic-gate 	volatile uint64_t *ib_slot_intr_state_diag_reg;
830Sstevel@tonic-gate 	volatile uint64_t *ib_obio_intr_state_diag_reg;
840Sstevel@tonic-gate 
850Sstevel@tonic-gate 	uint_t ib_max_ino;			/* largest supported INO */
860Sstevel@tonic-gate 	ib_ino_info_t *ib_ino_lst;		/* ino link list */
870Sstevel@tonic-gate 	kmutex_t ib_ino_lst_mutex;		/* mutex for ino link list */
880Sstevel@tonic-gate 	kmutex_t ib_intr_lock;			/* lock for internal intr  */
890Sstevel@tonic-gate 	uint16_t ib_map_reg_counters[8];	/* counters for shared map */
900Sstevel@tonic-gate 						/* registers */
910Sstevel@tonic-gate };
920Sstevel@tonic-gate 
930Sstevel@tonic-gate #define	PCI_PULSE_INO	0x80000000
940Sstevel@tonic-gate #define	PSYCHO_MAX_INO	0x3f
950Sstevel@tonic-gate #define	SCHIZO_MAX_INO	0x37
960Sstevel@tonic-gate #define	PCI_INO_BITS	6			/* INO#s are 6 bits long */
970Sstevel@tonic-gate #define	PCI_IGN_BITS	5			/* IGN#s are 5 bits long */
980Sstevel@tonic-gate 
990Sstevel@tonic-gate /*
1002973Sgovinda  * ih structure: one per every consumer of each ino and pil pair with interrupt
1012973Sgovinda  * registered.
1020Sstevel@tonic-gate  */
1030Sstevel@tonic-gate typedef struct ih {
1040Sstevel@tonic-gate 	dev_info_t *ih_dip;		/* devinfo structure */
1050Sstevel@tonic-gate 	uint32_t ih_inum;		/* interrupt number for this device */
1060Sstevel@tonic-gate 	uint_t	ih_intr_state;		/* Only used for fixed interrupts */
1070Sstevel@tonic-gate 	uint_t (*ih_handler)();		/* interrupt handler */
1080Sstevel@tonic-gate 	caddr_t ih_handler_arg1;	/* interrupt handler argument #1 */
1090Sstevel@tonic-gate 	caddr_t ih_handler_arg2;	/* interrupt handler argument #2 */
1100Sstevel@tonic-gate 	ddi_acc_handle_t ih_config_handle; /* config space reg map handle */
1110Sstevel@tonic-gate 	struct ih *ih_next;		/* next entry in list */
1120Sstevel@tonic-gate 	uint64_t ih_ticks;		/* ticks spent in this handler */
1130Sstevel@tonic-gate 	uint64_t ih_nsec;		/* nsec spent in this handler */
1142973Sgovinda 	kstat_t *ih_ksp;		/* pointer to kstat information */
1152973Sgovinda 	ib_ino_pil_t *ih_ipil_p;	/* only for use by kstat */
1160Sstevel@tonic-gate } ih_t;
1170Sstevel@tonic-gate 
1180Sstevel@tonic-gate /* Only used for fixed or legacy interrupts */
1190Sstevel@tonic-gate #define	PCI_INTR_STATE_DISABLE	0	/* disabled */
1200Sstevel@tonic-gate #define	PCI_INTR_STATE_ENABLE	1	/* enabled */
1210Sstevel@tonic-gate 
1220Sstevel@tonic-gate /*
1232973Sgovinda  * ino_pil structure: one per each ino and pil pair with interrupt registered
1242973Sgovinda  */
1252973Sgovinda struct ib_ino_pil {
1262973Sgovinda 	ushort_t ipil_pil;		/* PIL for this ino */
1272973Sgovinda 	ushort_t ipil_ih_size;		/* size of ih_t list */
1282973Sgovinda 	ih_t *ipil_ih_head;		/* ih_t list head */
1292973Sgovinda 	ih_t *ipil_ih_tail;		/* ih_t list tail */
1302973Sgovinda 	ih_t *ipil_ih_start;		/* starting point in ih_t list  */
1312973Sgovinda 	ib_ino_info_t *ipil_ino_p;	/* pointer to ib_ino_info_t */
1322973Sgovinda 	ib_ino_pil_t *ipil_next_p;	/* pointer to next ib_ino_pil_t */
1332973Sgovinda };
1342973Sgovinda 
1352973Sgovinda /*
1362973Sgovinda  * ino structure: one per each ino with interrupt registered
1370Sstevel@tonic-gate  */
1380Sstevel@tonic-gate struct ib_ino_info {
1390Sstevel@tonic-gate 	ib_ino_t ino_ino;		/* INO number - 8 bit */
1402973Sgovinda 	uint64_t ino_mondo;		/* store mondo number */
1410Sstevel@tonic-gate 	uint8_t ino_slot_no;		/* PCI slot number 0-8 */
1420Sstevel@tonic-gate 	ib_t *ino_ib_p;			/* link back to interrupt block state */
1430Sstevel@tonic-gate 	volatile uint64_t *ino_clr_reg;	/* ino interrupt clear register */
1440Sstevel@tonic-gate 	volatile uint64_t *ino_map_reg;	/* ino interrupt mapping register */
1450Sstevel@tonic-gate 	uint64_t ino_map_reg_save;	/* = *ino_map_reg if saved */
1462973Sgovinda 	volatile uint_t ino_unclaimed_intrs; /* number of unclaimed intrs */
1470Sstevel@tonic-gate 	clock_t ino_spurintr_begin;	/* begin time of spurious intr series */
1480Sstevel@tonic-gate 	int ino_established;		/* ino has been associated with a cpu */
1490Sstevel@tonic-gate 	uint32_t ino_cpuid;		/* cpu that ino is targeting */
1500Sstevel@tonic-gate 	int32_t ino_intr_weight;	/* intr weight of devices sharing ino */
1512973Sgovinda 	ushort_t ino_ipil_size;		/* number of ib_ino_pil_t sharing ino */
1522973Sgovinda 	ushort_t ino_lopil;		/* lowest PIL sharing ino */
1532973Sgovinda 	ushort_t ino_claimed;		/* pil bit masks, who claimed intr */
1542973Sgovinda 	ib_ino_pil_t *ino_ipil_p;	/* pointer to first ib_ino_pil_t */
1552973Sgovinda 	ib_ino_info_t *ino_next_p;	/* pointer to next ib_ino_info_t */
1560Sstevel@tonic-gate };
1570Sstevel@tonic-gate 
1580Sstevel@tonic-gate #define	IB_INTR_WAIT	1		/* wait for interrupt completion */
1590Sstevel@tonic-gate #define	IB_INTR_NOWAIT	0		/* already handling intr, no wait */
1600Sstevel@tonic-gate 
1610Sstevel@tonic-gate #define	IB2CB(ib_p)	((ib_p)->ib_pci_p->pci_cb_p)
1620Sstevel@tonic-gate 
1630Sstevel@tonic-gate #define	IB_MONDO_TO_INO(mondo)		((ib_ino_t)((mondo) & 0x3f))
1640Sstevel@tonic-gate #define	IB_INO_INTR_ON(reg_p)		*(reg_p) |= COMMON_INTR_MAP_REG_VALID
1650Sstevel@tonic-gate #define	IB_INO_INTR_OFF(reg_p)		*(reg_p) &= ~COMMON_INTR_MAP_REG_VALID
1660Sstevel@tonic-gate #define	IB_INO_INTR_RESET(reg_p)	*(reg_p) = 0ull
1670Sstevel@tonic-gate #define	IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \
1680Sstevel@tonic-gate 	ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg)
1690Sstevel@tonic-gate #define	IB_INO_INTR_PENDING(reg_p, ino) \
1700Sstevel@tonic-gate 	(((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \
1710Sstevel@tonic-gate 	COMMON_CLEAR_INTR_REG_PENDING)
1720Sstevel@tonic-gate #define	IB_INO_INTR_CLEAR(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_IDLE
1730Sstevel@tonic-gate #define	IB_INO_INTR_TRIG(reg_p)	*(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED
1740Sstevel@tonic-gate #define	IB_INO_INTR_PEND(reg_p)		*(reg_p) = COMMON_CLEAR_INTR_REG_PENDING
1750Sstevel@tonic-gate #define	IB_INO_INTR_ISON(imr)		((imr) >> 31)
1760Sstevel@tonic-gate #define	IB_IMR2MONDO(imr) \
1770Sstevel@tonic-gate 	((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO))
1780Sstevel@tonic-gate 
1790Sstevel@tonic-gate #define	IB_IS_OBIO_INO(ino) (ino & 0x20)
1800Sstevel@tonic-gate 
1810Sstevel@tonic-gate #ifdef _STARFIRE
1820Sstevel@tonic-gate /*
1830Sstevel@tonic-gate  * returns a uniq ino per interrupt mapping register
1840Sstevel@tonic-gate  * For on board devices, inos are not shared. But for plugin devices,
1850Sstevel@tonic-gate  * return the 1st ino of the 4 that are sharing the same mapping register.
1860Sstevel@tonic-gate  */
1870Sstevel@tonic-gate #define	IB_GET_MAPREG_INO(ino)	\
188946Smathue 	((volatile uint64_t *)(uintptr_t)((ino & 0x20) ? \
189946Smathue 	    ino : ((ino >> 2) << 2)))
1900Sstevel@tonic-gate #endif /* _STARFIRE */
1910Sstevel@tonic-gate 
1920Sstevel@tonic-gate #define	IB_IGN_TO_MONDO(ign, ino)	(((ign) << PCI_INO_BITS) | (ino))
1930Sstevel@tonic-gate #define	IB_INO_TO_MONDO(ib_p, ino)	IB_IGN_TO_MONDO((ib_p)->ib_ign, ino)
1940Sstevel@tonic-gate 
1950Sstevel@tonic-gate extern void ib_create(pci_t *pci_p);
1960Sstevel@tonic-gate extern void ib_destroy(pci_t *pci_p);
1970Sstevel@tonic-gate extern void ib_configure(ib_t *ib_p);
1980Sstevel@tonic-gate extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id);
1990Sstevel@tonic-gate extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino);
2000Sstevel@tonic-gate extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait);
2010Sstevel@tonic-gate extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino);
2020Sstevel@tonic-gate extern void ib_suspend(ib_t *ib_p);
2030Sstevel@tonic-gate extern void ib_resume(ib_t *ib_p);
2040Sstevel@tonic-gate 
2050Sstevel@tonic-gate extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num);
2062973Sgovinda extern ib_ino_pil_t *ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil,
2072973Sgovinda     ih_t *ih_p);
2082973Sgovinda extern void ib_delete_ino_pil(ib_t *ib_p, ib_ino_pil_t *ipil_p);
2090Sstevel@tonic-gate extern void ib_free_ino_all(ib_t *ib_p);
2102973Sgovinda extern ib_ino_pil_t *ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil);
2112973Sgovinda extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
2122973Sgovinda extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_pil_t *ipil_p, ih_t *ih_p);
2132973Sgovinda extern ih_t *ib_intr_locate_ih(ib_ino_pil_t *ipil_p, dev_info_t *dip,
2140Sstevel@tonic-gate     uint32_t inum);
2150Sstevel@tonic-gate extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum,
2160Sstevel@tonic-gate     uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2),
2170Sstevel@tonic-gate     caddr_t int_handler_arg1, caddr_t int_handler_arg2);
2180Sstevel@tonic-gate extern void ib_free_ih(ih_t *ih_p);
2190Sstevel@tonic-gate extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino,
2202973Sgovinda     ib_ino_info_t *ino_p);
2210Sstevel@tonic-gate extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino,
2222973Sgovinda     ib_ino_info_t *ino_p);
2230Sstevel@tonic-gate extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
2242973Sgovinda     uint_t (*handler)(caddr_t arg), caddr_t arg);
2250Sstevel@tonic-gate extern void ib_unregister_intr(ib_mondo_t mondo);
2260Sstevel@tonic-gate extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino,
2272973Sgovinda     volatile uint64_t *imr_p);
2280Sstevel@tonic-gate extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight);
229117Sschwartz extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id);
230*10053SEvan.Yan@Sun.COM extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip,
231*10053SEvan.Yan@Sun.COM     ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state);
232*10053SEvan.Yan@Sun.COM extern int ib_get_intr_target(pci_t *pci_p, ib_ino_t ino, int *cpu_id_p);
233*10053SEvan.Yan@Sun.COM extern int ib_set_intr_target(pci_t *pci_p, ib_ino_t ino, int cpu_id);
234117Sschwartz extern uint8_t ib_get_ino_devs(ib_t *ib_p, uint32_t ino, uint8_t *devs_ret,
2352973Sgovinda     pcitool_intr_dev_t *devs);
236117Sschwartz extern void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id,
2372973Sgovinda     uint32_t ino);
2380Sstevel@tonic-gate 
2390Sstevel@tonic-gate extern int pci_pil[];
2400Sstevel@tonic-gate 
2410Sstevel@tonic-gate #ifdef	__cplusplus
2420Sstevel@tonic-gate }
2430Sstevel@tonic-gate #endif
2440Sstevel@tonic-gate 
2450Sstevel@tonic-gate #endif	/* _SYS_PCI_IB_H */
246