1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_CB_H 28*0Sstevel@tonic-gate #define _SYS_PCI_CB_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate typedef uint16_t cb_nid_t; 37*0Sstevel@tonic-gate enum cb_nintr_index { 38*0Sstevel@tonic-gate CBNINTR_PBM = 0, /* all not shared */ 39*0Sstevel@tonic-gate CBNINTR_PBM66 = 0, /* all not shared */ 40*0Sstevel@tonic-gate CBNINTR_PBM33 = 0, /* all not shared */ 41*0Sstevel@tonic-gate CBNINTR_UE = 1, /* all shared */ 42*0Sstevel@tonic-gate CBNINTR_CE = 2, /* all shared */ 43*0Sstevel@tonic-gate CBNINTR_POWER_FAIL = 3, /* psycho shared */ 44*0Sstevel@tonic-gate CBNINTR_POWER_BUTTON = 3, /* sabre N/A */ 45*0Sstevel@tonic-gate CBNINTR_PME_HB = 3, /* hummingbird N/A */ 46*0Sstevel@tonic-gate CBNINTR_BUS_ERROR = 3, /* schizo shared */ 47*0Sstevel@tonic-gate CBNINTR_THERMAL = 4, /* psycho shared */ 48*0Sstevel@tonic-gate CBNINTR_PME = 4, /* schizo not shared */ 49*0Sstevel@tonic-gate CBNINTR_CDMA = 4, /* schizo not shared */ 50*0Sstevel@tonic-gate CBNINTR_PWR_MANAGE = 5, /* psycho shared */ 51*0Sstevel@tonic-gate CBNINTR_MAX /* count coding */ 52*0Sstevel@tonic-gate }; 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate /* 55*0Sstevel@tonic-gate * control block soft state structure: 56*0Sstevel@tonic-gate * 57*0Sstevel@tonic-gate * Each pci node contains shares a control block structure with its peer 58*0Sstevel@tonic-gate * node. The control block node contains csr and id registers for chip 59*0Sstevel@tonic-gate * and acts as a "catch all" for other functionality that does not cleanly 60*0Sstevel@tonic-gate * fall into other functional blocks. This block is also used to handle 61*0Sstevel@tonic-gate * software workarounds for known hardware bugs in different chip revs. 62*0Sstevel@tonic-gate */ 63*0Sstevel@tonic-gate typedef struct cb cb_t; 64*0Sstevel@tonic-gate struct cb { 65*0Sstevel@tonic-gate pci_common_t *cb_pci_cmn_p; 66*0Sstevel@tonic-gate cb_nid_t cb_node_id; 67*0Sstevel@tonic-gate pci_ign_t cb_ign; /* 1st-attached-side interrupt grp# */ 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate kmutex_t cb_intr_lock; /* guards add/rem intr and intr dist */ 70*0Sstevel@tonic-gate uint32_t cb_no_of_inos; /* # of actual inos, including PBM */ 71*0Sstevel@tonic-gate uint32_t cb_inos[CBNINTR_MAX]; /* subset of pci_p->pci_inos array */ 72*0Sstevel@tonic-gate 73*0Sstevel@tonic-gate uint64_t cb_base_pa; /* PA of schizo CSR bank, 2nd "reg" */ 74*0Sstevel@tonic-gate uint64_t cb_icbase_pa; /* PA of tomatillo IChip register */ 75*0Sstevel@tonic-gate /* bank, 4th "reg" entry */ 76*0Sstevel@tonic-gate uint64_t cb_map_pa; /* 1st-attached-side map reg base PA */ 77*0Sstevel@tonic-gate uint64_t cb_clr_pa; /* 1st-attached-side clr reg base PA */ 78*0Sstevel@tonic-gate uint64_t cb_obsta_pa; /* 1st-attached-side sta reg base PA */ 79*0Sstevel@tonic-gate 80*0Sstevel@tonic-gate uint64_t *cb_imr_save; 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate #ifdef _STARFIRE 83*0Sstevel@tonic-gate caddr_t cb_ittrans_cookie; /* intr tgt translation */ 84*0Sstevel@tonic-gate #endif 85*0Sstevel@tonic-gate }; 86*0Sstevel@tonic-gate 87*0Sstevel@tonic-gate #define CB_INO_TO_MONDO(cb_p, ino) ((cb_p)->cb_ign << PCI_INO_BITS | (ino)) 88*0Sstevel@tonic-gate #define CB_MONDO_TO_XMONDO(cb_p, mondo) /* local mondo to global mondo */ \ 89*0Sstevel@tonic-gate ((cb_p)->cb_node_id << (PCI_IGN_BITS + PCI_INO_BITS) | (mondo)) 90*0Sstevel@tonic-gate 91*0Sstevel@tonic-gate extern void cb_create(pci_t *pci_p); 92*0Sstevel@tonic-gate extern void cb_destroy(pci_t *pci_p); 93*0Sstevel@tonic-gate extern void cb_suspend(cb_t *cb_p); 94*0Sstevel@tonic-gate extern void cb_resume(cb_t *cb_p); 95*0Sstevel@tonic-gate extern void cb_enable_nintr(pci_t *pci_p, enum cb_nintr_index idx); 96*0Sstevel@tonic-gate extern void cb_disable_nintr(cb_t *cb_p, enum cb_nintr_index idx, int wait); 97*0Sstevel@tonic-gate extern void cb_clear_nintr(cb_t *cb_p, enum cb_nintr_index idx); 98*0Sstevel@tonic-gate extern void cb_intr_dist(void *arg); 99*0Sstevel@tonic-gate 100*0Sstevel@tonic-gate #ifdef __cplusplus 101*0Sstevel@tonic-gate } 102*0Sstevel@tonic-gate #endif 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate #endif /* _SYS_PCI_CB_H */ 105