1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_DB21554_CSR_H 28*0Sstevel@tonic-gate #define _SYS_DB21554_CSR_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* CSR Register Offset definitions */ 37*0Sstevel@tonic-gate #define DB_CSR_DS_CONF_ADDR 0x000 /* DownStream config addres */ 38*0Sstevel@tonic-gate #define DB_CSR_DS_CONF_DATA 0x004 /* downstream config data */ 39*0Sstevel@tonic-gate #define DB_CSR_US_CONF_ADDR 0x008 /* UpStream config address */ 40*0Sstevel@tonic-gate #define DB_CSR_US_CONF_DATA 0x00C /* UpStream config data */ 41*0Sstevel@tonic-gate #define DB_CSR_CONF_OWN 0x010 /* config own bits - word reg */ 42*0Sstevel@tonic-gate #define DB_CSR8_DS_CONF_OWN 0x010 /* config own bits - byte reg */ 43*0Sstevel@tonic-gate #define DB_CSR8_US_CONF_OWN 0x011 /* config own bits - byte reg */ 44*0Sstevel@tonic-gate #define DB_CSR_CONF_CSR 0x012 /* config ctrl/status - word */ 45*0Sstevel@tonic-gate #define DB_CSR8_DS_CONF_CSR 0x012 /* DS config csr - byte */ 46*0Sstevel@tonic-gate #define DB_CSR8_US_CONF_CSR 0x013 /* US config csr - byte */ 47*0Sstevel@tonic-gate #define DB_CSR_DS_IO_ADDR 0x014 /* DS io address */ 48*0Sstevel@tonic-gate #define DB_CSR_DS_IO_DATA 0x018 /* DS io data */ 49*0Sstevel@tonic-gate #define DB_CSR_US_IO_ADDR 0x01C /* US io address */ 50*0Sstevel@tonic-gate #define DB_CSR_US_IO_DATA 0x020 /* US io data */ 51*0Sstevel@tonic-gate #define DB_CSR_IO_OWN 0x024 /* IO Own bits - word reg */ 52*0Sstevel@tonic-gate #define DB_CSR8_DS_IO_OWN 0x024 /* DS IO Own bits - byte reg */ 53*0Sstevel@tonic-gate #define DB_CSR8_US_IO_OWN 0x025 /* DS IO Own bits - byte reg */ 54*0Sstevel@tonic-gate #define DB_CSR_IO_CSR 0x026 /* IO csr - word reg */ 55*0Sstevel@tonic-gate #define DB_CSR8_DS_IO_CSR 0x026 /* DS IO csr - byte reg */ 56*0Sstevel@tonic-gate #define DB_CSR8_US_IO_CSR 0x027 /* US IO csr - byte reg */ 57*0Sstevel@tonic-gate #define DB_CSR_LUT_OFFSET 0x028 /* Lookup Table offset */ 58*0Sstevel@tonic-gate #define DB_CSR_LUT_DATA 0x02C /* LookUp Table Data */ 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate #define DB_CSR_I2O_OB_PL_STATUS 0x030 /* I2O outbound postlist stat */ 61*0Sstevel@tonic-gate #define DB_CSR_I2O_OB_PL_INTR_MASK 0x034 /* I2O outbound postlistImask */ 62*0Sstevel@tonic-gate #define DB_CSR_I2O_IB_PL_STATUS 0x038 /* I2O inbound postlist stat */ 63*0Sstevel@tonic-gate #define DB_CSR_I2O_IB_PL_INTR_MASK 0x03C /* I2O inbound postlist Imask */ 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate #define DB_CSR_CHIP_STATUS_CSR 0x082 /* chip status CSR */ 66*0Sstevel@tonic-gate #define DB_CSR_CHIP_SET_IRQ_MASK 0x084 /* chip set IRQ mask */ 67*0Sstevel@tonic-gate #define DB_CSR_CHIP_CLR_IRQ_MASK 0x086 /* chip clear IRQ mask */ 68*0Sstevel@tonic-gate #define DB_CSR_US_PAGEBOUND_IRQ0 0x088 /* US page boundary IRQ 0 */ 69*0Sstevel@tonic-gate #define DB_CSR_US_PAGEBOUND_IRQ1 0x08C /* US page boundary IRQ 1 */ 70*0Sstevel@tonic-gate #define DB_CSR_US_PAGEBOUND_IRQ_MASK0 0x090 /* US page boundary IRQ mask0 */ 71*0Sstevel@tonic-gate #define DB_CSR_US_PAGEBOUND_IRQ_MASK1 0x094 /* US page boundary IRQ mask1 */ 72*0Sstevel@tonic-gate #define DB_CSR_PRIM_CLR_IRQ 0x098 /* Primary Clear IRQ */ 73*0Sstevel@tonic-gate #define DB_CSR_SEC_CLR_IRQ 0x09A /* Secondary Clear IRQ */ 74*0Sstevel@tonic-gate #define DB_CSR_PRIM_SET_IRQ 0x09C /* Primary Set IRQ */ 75*0Sstevel@tonic-gate #define DB_CSR_SEC_SET_IRQ 0x09E /* Secondary Set IRQ */ 76*0Sstevel@tonic-gate #define DB_CSR_PRIM_CLR_IRQ_MASK 0x0A0 /* Primary Clear IRQ Mask */ 77*0Sstevel@tonic-gate #define DB_CSR_SEC_CLR_IRQ_MASK 0x0A2 /* Secondary Clear IRQ Mask */ 78*0Sstevel@tonic-gate #define DB_CSR_PRIM_SET_IRQ_MASK 0x0A4 /* Primary Set IRQ Mask */ 79*0Sstevel@tonic-gate #define DB_CSR_SEC_SET_IRQ_MASK 0x0A6 /* Secondary Set IRQ Mask */ 80*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_0 0x0A8 /* Scratchpad 0 */ 81*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_1 0x0AC /* Scratchpad 1 */ 82*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_2 0x0B0 /* Scratchpad 2 */ 83*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_3 0x0B4 /* Scratchpad 3 */ 84*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_4 0x0B8 /* Scratchpad 4 */ 85*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_5 0x0BC /* Scratchpad 5 */ 86*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_6 0x0C0 /* Scratchpad 6 */ 87*0Sstevel@tonic-gate #define DB_CSR_SCRATCHPAD_7 0x0C4 /* Scratchpad 7 */ 88*0Sstevel@tonic-gate #define DB_CSR_ROM_SETUP 0x0C8 /* ROM setup register */ 89*0Sstevel@tonic-gate #define DB_CSR_ROM_DATA 0x0CA /* ROM Data register */ 90*0Sstevel@tonic-gate #define DB_CSR_ROM_ADDR 0x0CC /* ROM Address register */ 91*0Sstevel@tonic-gate #define DB_CSR_ROM_CTRL 0x0CF /* ROM control */ 92*0Sstevel@tonic-gate #define DB_CSR_US_MEM2_LUT 0x100 /* US Memory 2 Lookup Table */ 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* Configuration Own Bits register definition */ 95*0Sstevel@tonic-gate #define DS_IO_OWN 0x0001 96*0Sstevel@tonic-gate #define US_IO_OWN 0x0100 97*0Sstevel@tonic-gate /* the following is a 8bit register bit definitions for IO own */ 98*0Sstevel@tonic-gate #define DS8_IO_OWN 0x01 99*0Sstevel@tonic-gate #define US8_IO_OWN 0x01 100*0Sstevel@tonic-gate 101*0Sstevel@tonic-gate /* IO control status register bits: Register offset 0x26-27 */ 102*0Sstevel@tonic-gate #define IO_DS_OWN_STAT 0x0001 /* downstream config own status */ 103*0Sstevel@tonic-gate #define IO_DS_ENABLE 0x0002 /* enable downstream config cycles */ 104*0Sstevel@tonic-gate #define IO_US_OWN_STAT 0x0100 /* upstream config own status */ 105*0Sstevel@tonic-gate #define IO_US_ENABLE 0x0200 /* enable upstream config cycles */ 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate typedef volatile struct us_mem2_tbl { 108*0Sstevel@tonic-gate uchar_t unimpl[256]; /* currently unimplemented */ 109*0Sstevel@tonic-gate } us_mem2_tbl_t; 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate #ifdef __cplusplus 112*0Sstevel@tonic-gate } 113*0Sstevel@tonic-gate #endif 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate #endif /* _SYS_DB21554_CSR_H */ 116