1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate /*
30*0Sstevel@tonic-gate * Following is STARFIRE specific code
31*0Sstevel@tonic-gate */
32*0Sstevel@tonic-gate
33*0Sstevel@tonic-gate #include <sys/types.h>
34*0Sstevel@tonic-gate #include <sys/systm.h>
35*0Sstevel@tonic-gate #include <sys/archsystm.h>
36*0Sstevel@tonic-gate #include <sys/machsystm.h>
37*0Sstevel@tonic-gate #include <sys/vmem.h>
38*0Sstevel@tonic-gate #include <sys/mman.h>
39*0Sstevel@tonic-gate #include <sys/vm.h>
40*0Sstevel@tonic-gate
41*0Sstevel@tonic-gate #include <sys/cmn_err.h>
42*0Sstevel@tonic-gate #include <sys/cpu_sgnblk_defs.h>
43*0Sstevel@tonic-gate #include <sys/starfire.h>
44*0Sstevel@tonic-gate
45*0Sstevel@tonic-gate #include <vm/seg.h>
46*0Sstevel@tonic-gate #include <vm/seg_kmem.h>
47*0Sstevel@tonic-gate #include <vm/seg_kp.h>
48*0Sstevel@tonic-gate #include <sys/vtrace.h>
49*0Sstevel@tonic-gate #include <sys/cpu_sgn.h>
50*0Sstevel@tonic-gate
51*0Sstevel@tonic-gate /*
52*0Sstevel@tonic-gate * SIGBCPU represents the cpu maintaining the primary
53*0Sstevel@tonic-gate * sigblock (bbsram). This bbsram is used for CVC
54*0Sstevel@tonic-gate * and maintains the post2obp structure. It starts
55*0Sstevel@tonic-gate * out as the bootproc (cpu0).
56*0Sstevel@tonic-gate */
57*0Sstevel@tonic-gate struct cpu *SIGBCPU = &cpu0;
58*0Sstevel@tonic-gate
59*0Sstevel@tonic-gate cpu_sgnblk_t *cpu_sgnblkp[NCPU];
60*0Sstevel@tonic-gate
61*0Sstevel@tonic-gate /*
62*0Sstevel@tonic-gate * Mapin the the cpu's signature block.
63*0Sstevel@tonic-gate */
64*0Sstevel@tonic-gate void
cpu_sgn_mapin(int cpuid)65*0Sstevel@tonic-gate cpu_sgn_mapin(int cpuid)
66*0Sstevel@tonic-gate {
67*0Sstevel@tonic-gate uint64_t bbsram_physaddr;
68*0Sstevel@tonic-gate uint64_t cpu_sgnblk_physaddr;
69*0Sstevel@tonic-gate uint32_t cpu_sgnblk_offset;
70*0Sstevel@tonic-gate caddr_t cvaddr;
71*0Sstevel@tonic-gate pgcnt_t num_pages;
72*0Sstevel@tonic-gate pfn_t pfn;
73*0Sstevel@tonic-gate
74*0Sstevel@tonic-gate ASSERT(cpu_sgnblkp[cpuid] == NULL);
75*0Sstevel@tonic-gate
76*0Sstevel@tonic-gate /*
77*0Sstevel@tonic-gate * Construct the physical base address of the bbsram
78*0Sstevel@tonic-gate * in PSI space associated with this cpu in question.
79*0Sstevel@tonic-gate */
80*0Sstevel@tonic-gate cpu_sgnblk_physaddr = bbsram_physaddr =
81*0Sstevel@tonic-gate STARFIRE_UPAID2UPS(cpuid) | STARFIRE_PSI_BASE;
82*0Sstevel@tonic-gate
83*0Sstevel@tonic-gate /*
84*0Sstevel@tonic-gate * The cpu_sgnblk pointer offsets are stored in the
85*0Sstevel@tonic-gate * undefined hardware trap slot 0x7f which is located
86*0Sstevel@tonic-gate * at offset 0xfe0. There are 2 of them since the
87*0Sstevel@tonic-gate * bbsram is shared among the 2 cpus residing on the
88*0Sstevel@tonic-gate * a PC. We need to determine the CPU in question whether
89*0Sstevel@tonic-gate * it is in port 0 or 1. CPU on port 0 has its
90*0Sstevel@tonic-gate * signature blkptr stored in 0xfe0 while the cpu_sgnblk
91*0Sstevel@tonic-gate * ptr of local port 1's CPU is in offset 0xfe8.
92*0Sstevel@tonic-gate */
93*0Sstevel@tonic-gate if (cpuid & 0x1) {
94*0Sstevel@tonic-gate /* CPU is in local port 1 */
95*0Sstevel@tonic-gate bbsram_physaddr |= 0xfe8ULL;
96*0Sstevel@tonic-gate } else {
97*0Sstevel@tonic-gate /* CPU is in local port 0 */
98*0Sstevel@tonic-gate bbsram_physaddr |= 0xfe0ULL;
99*0Sstevel@tonic-gate }
100*0Sstevel@tonic-gate
101*0Sstevel@tonic-gate /*
102*0Sstevel@tonic-gate * Read in the cpu_sgnblk pointer offset. Add it to the bbsram
103*0Sstevel@tonic-gate * base address to get the base address of the cpu_sgnblk.
104*0Sstevel@tonic-gate */
105*0Sstevel@tonic-gate cpu_sgnblk_offset = ldphysio(bbsram_physaddr);
106*0Sstevel@tonic-gate cpu_sgnblk_physaddr += cpu_sgnblk_offset;
107*0Sstevel@tonic-gate
108*0Sstevel@tonic-gate pfn = (pfn_t)(cpu_sgnblk_physaddr >> MMU_PAGESHIFT);
109*0Sstevel@tonic-gate
110*0Sstevel@tonic-gate num_pages = mmu_btopr(((cpu_sgnblk_physaddr &
111*0Sstevel@tonic-gate MMU_PAGEOFFSET) + sizeof (cpu_sgnblk_t)));
112*0Sstevel@tonic-gate
113*0Sstevel@tonic-gate /*
114*0Sstevel@tonic-gate * Map in the cpu_sgnblk
115*0Sstevel@tonic-gate */
116*0Sstevel@tonic-gate cvaddr = vmem_alloc(heap_arena, ptob(num_pages), VM_SLEEP);
117*0Sstevel@tonic-gate
118*0Sstevel@tonic-gate hat_devload(kas.a_hat, cvaddr, ptob(num_pages),
119*0Sstevel@tonic-gate pfn, PROT_READ | PROT_WRITE, HAT_LOAD_LOCK);
120*0Sstevel@tonic-gate
121*0Sstevel@tonic-gate cpu_sgnblkp[cpuid] = ((cpu_sgnblk_t *)(cvaddr +
122*0Sstevel@tonic-gate (uint32_t)(cpu_sgnblk_offset & MMU_PAGEOFFSET)));
123*0Sstevel@tonic-gate }
124*0Sstevel@tonic-gate
125*0Sstevel@tonic-gate void
cpu_sgn_mapout(int cpuid)126*0Sstevel@tonic-gate cpu_sgn_mapout(int cpuid)
127*0Sstevel@tonic-gate {
128*0Sstevel@tonic-gate ulong_t cvaddr, num_pages;
129*0Sstevel@tonic-gate uint32_t cpu_sgnblk_offset;
130*0Sstevel@tonic-gate uint64_t cpu_sgnblk_physaddr;
131*0Sstevel@tonic-gate uint64_t bbsram_physaddr;
132*0Sstevel@tonic-gate
133*0Sstevel@tonic-gate if ((cvaddr = (ulong_t)cpu_sgnblkp[cpuid]) == NULL) {
134*0Sstevel@tonic-gate cmn_err(CE_WARN, "cpu_sgn_mapout: ERROR: "
135*0Sstevel@tonic-gate "cpu_sgnblkp[%d] = NULL\n", cpuid);
136*0Sstevel@tonic-gate } else {
137*0Sstevel@tonic-gate cvaddr &= ~MMU_PAGEOFFSET;
138*0Sstevel@tonic-gate
139*0Sstevel@tonic-gate /*
140*0Sstevel@tonic-gate * Construct the physical base address of the bbsram
141*0Sstevel@tonic-gate * in PSI space associated with this cpu in question.
142*0Sstevel@tonic-gate */
143*0Sstevel@tonic-gate bbsram_physaddr = STARFIRE_UPAID2UPS(cpuid) |
144*0Sstevel@tonic-gate STARFIRE_PSI_BASE;
145*0Sstevel@tonic-gate cpu_sgnblk_physaddr = bbsram_physaddr;
146*0Sstevel@tonic-gate
147*0Sstevel@tonic-gate /*
148*0Sstevel@tonic-gate * The cpu_sgnblk pointer offsets are stored in the
149*0Sstevel@tonic-gate * undefined hardware trap slot 0x7f which is located
150*0Sstevel@tonic-gate * at offset 0xfe0. There are 2 of them since the
151*0Sstevel@tonic-gate * bbsram is shared among the 2 cpus residing on the
152*0Sstevel@tonic-gate * a PC. We need to determine the CPU in question whether
153*0Sstevel@tonic-gate * it is in port 0 or 1. CPU on port 0 has its
154*0Sstevel@tonic-gate * signature blkptr stored in 0xfe0 while the cpu_sgnblk
155*0Sstevel@tonic-gate * ptr of local port 1's CPU is in offset 0xfe8.
156*0Sstevel@tonic-gate */
157*0Sstevel@tonic-gate if (cpuid & 0x1) {
158*0Sstevel@tonic-gate /* CPU is in local port 1 */
159*0Sstevel@tonic-gate bbsram_physaddr |= 0xfe8ULL;
160*0Sstevel@tonic-gate } else {
161*0Sstevel@tonic-gate /* CPU is in local port 0 */
162*0Sstevel@tonic-gate bbsram_physaddr |= 0xfe0ULL;
163*0Sstevel@tonic-gate }
164*0Sstevel@tonic-gate
165*0Sstevel@tonic-gate /*
166*0Sstevel@tonic-gate * Read in the cpu_sgnblk pointer offset. Add it to the bbsram
167*0Sstevel@tonic-gate * base address to get the base address of the cpu_sgnblk.
168*0Sstevel@tonic-gate */
169*0Sstevel@tonic-gate cpu_sgnblk_offset = ldphysio(bbsram_physaddr);
170*0Sstevel@tonic-gate cpu_sgnblk_physaddr += cpu_sgnblk_offset;
171*0Sstevel@tonic-gate
172*0Sstevel@tonic-gate num_pages = mmu_btopr(((uint_t)(cpu_sgnblk_physaddr &
173*0Sstevel@tonic-gate MMU_PAGEOFFSET) + sizeof (cpu_sgnblk_t)));
174*0Sstevel@tonic-gate
175*0Sstevel@tonic-gate hat_unload(kas.a_hat, (caddr_t)cvaddr, ptob(num_pages),
176*0Sstevel@tonic-gate HAT_UNLOAD_UNLOCK);
177*0Sstevel@tonic-gate vmem_free(heap_arena, (caddr_t)cvaddr, ptob(num_pages));
178*0Sstevel@tonic-gate
179*0Sstevel@tonic-gate cpu_sgnblkp[cpuid] = NULL;
180*0Sstevel@tonic-gate }
181*0Sstevel@tonic-gate }
182