1*1708Sstevel /* 2*1708Sstevel * CDDL HEADER START 3*1708Sstevel * 4*1708Sstevel * The contents of this file are subject to the terms of the 5*1708Sstevel * Common Development and Distribution License (the "License"). 6*1708Sstevel * You may not use this file except in compliance with the License. 7*1708Sstevel * 8*1708Sstevel * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*1708Sstevel * or http://www.opensolaris.org/os/licensing. 10*1708Sstevel * See the License for the specific language governing permissions 11*1708Sstevel * and limitations under the License. 12*1708Sstevel * 13*1708Sstevel * When distributing Covered Code, include this CDDL HEADER in each 14*1708Sstevel * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*1708Sstevel * If applicable, add the following below this CDDL HEADER, with the 16*1708Sstevel * fields enclosed by brackets "[]" replaced with your own identifying 17*1708Sstevel * information: Portions Copyright [yyyy] [name of copyright owner] 18*1708Sstevel * 19*1708Sstevel * CDDL HEADER END 20*1708Sstevel */ 21*1708Sstevel 22*1708Sstevel /* 23*1708Sstevel * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*1708Sstevel * Use is subject to license terms. 25*1708Sstevel */ 26*1708Sstevel 27*1708Sstevel #ifndef _SYS_SCHPC_MSG_H 28*1708Sstevel #define _SYS_SCHPC_MSG_H 29*1708Sstevel 30*1708Sstevel #pragma ident "%Z%%M% %I% %E% SMI" 31*1708Sstevel 32*1708Sstevel /* 33*1708Sstevel * This header file describes the messages that are sent between the 34*1708Sstevel * schpc Hot Plug Controller Driver running on the domain and the System 35*1708Sstevel * Controller. 36*1708Sstevel */ 37*1708Sstevel 38*1708Sstevel #ifdef __cplusplus 39*1708Sstevel extern "C" { 40*1708Sstevel #endif 41*1708Sstevel 42*1708Sstevel /* 43*1708Sstevel * Format of the Get Slot Status specific part of 44*1708Sstevel * PCI Hot Plug message. 45*1708Sstevel */ 46*1708Sstevel typedef struct { 47*1708Sstevel uint16_t slot_power_on :1, /* Slot Power is on */ 48*1708Sstevel slot_powergood :1, /* Slot Power is good */ 49*1708Sstevel slot_powerfault :1, /* Slot Power has faulted */ 50*1708Sstevel slot_empty :1, /* No occupant in slot */ 51*1708Sstevel slot_freq_cap :2, /* Slot's Freq Capability */ 52*1708Sstevel slot_freq_setting :2, /* Slot Freq setting */ 53*1708Sstevel slot_condition :2, /* Condition of slot */ 54*1708Sstevel slot_HEALTHY :1, /* Value of HEALTHY# sig */ 55*1708Sstevel slot_ENUM :1, /* Value of ENUM# sig */ 56*1708Sstevel slot_mode_cap :1, /* Conven or PCI-X */ 57*1708Sstevel slot_mode_setting :1, /* Conven or PCI-X */ 58*1708Sstevel reserved :2; 59*1708Sstevel uint8_t slot_replystatus; 60*1708Sstevel } pci_getslot_t; 61*1708Sstevel 62*1708Sstevel /* 63*1708Sstevel * Format of the Set Slot Status specific part of 64*1708Sstevel * PCI Hot Plug message. 65*1708Sstevel */ 66*1708Sstevel typedef struct { 67*1708Sstevel uint16_t slot_power_on :1, /* Connect Slot to bus */ 68*1708Sstevel slot_power_off :1, /* Disconnect from bus */ 69*1708Sstevel slot_led_power :2, /* Slot Power LED */ 70*1708Sstevel slot_led_service :2, /* OK To Remove LED */ 71*1708Sstevel slot_led_fault :2, /* Fault LED */ 72*1708Sstevel slot_disable_ENUM :1, /* Disable ENUM Event */ 73*1708Sstevel slot_enable_ENUM :1, /* Enable ENUM Event */ 74*1708Sstevel slot_disable_HEALTHY :1, /* Disable HEALTHY EVENT */ 75*1708Sstevel slot_enable_HEALTHY :1, /* Enable HEALTHY EVENT */ 76*1708Sstevel reserved :4; 77*1708Sstevel uint8_t slot_replystatus; 78*1708Sstevel } pci_setslot_t; 79*1708Sstevel 80*1708Sstevel /* 81*1708Sstevel * Format of the Slot Event specific part of 82*1708Sstevel * the PCI Hot Plug message. 83*1708Sstevel */ 84*1708Sstevel typedef struct { 85*1708Sstevel uint16_t slot_power :1, /* Slot Power has changed */ 86*1708Sstevel slot_presence :1, /* occupant has been */ 87*1708Sstevel /* inserted or removed */ 88*1708Sstevel slot_ENUM :1, /* ENUM# has changed */ 89*1708Sstevel slot_HEALTHY :1, /* HEALTHY# has changed */ 90*1708Sstevel slot_powergood :1, /* Power is good */ 91*1708Sstevel slot_powerfault :1, /* Power has faulted */ 92*1708Sstevel reserved :10; 93*1708Sstevel } pci_slotevent_t; 94*1708Sstevel 95*1708Sstevel /* 96*1708Sstevel * PCI Hot Plug message 97*1708Sstevel */ 98*1708Sstevel typedef struct { 99*1708Sstevel uint8_t pcimsg_node; 100*1708Sstevel uint8_t pcimsg_board; 101*1708Sstevel uint8_t pcimsg_slot; 102*1708Sstevel uint8_t pcimsg_revision; 103*1708Sstevel uint8_t pcimsg_command; 104*1708Sstevel union { 105*1708Sstevel pci_setslot_t pcimsg_setslot; 106*1708Sstevel pci_getslot_t pcimsg_getslot; 107*1708Sstevel pci_slotevent_t pcimsg_slotevent; 108*1708Sstevel } pcimsg_type; 109*1708Sstevel } pcimsg_t; 110*1708Sstevel 111*1708Sstevel /* 112*1708Sstevel * Keys for the outgoing and incoming mailboxes 113*1708Sstevel */ 114*1708Sstevel #define KEY_PCSC 0x50435343 /* Outgoing Mailbox 'PCSC' */ 115*1708Sstevel #define KEY_SCPC 0x53435043 /* Incoming Mailbox 'SCPC' */ 116*1708Sstevel 117*1708Sstevel /* 118*1708Sstevel * default timeout in seconds for mboxsc_getmsg calls 119*1708Sstevel */ 120*1708Sstevel #define PCSC_TIMEOUT 30 121*1708Sstevel 122*1708Sstevel /* Commands */ 123*1708Sstevel #define PCIMSG_GETSLOTSTATUS 0x1 124*1708Sstevel #define PCIMSG_SETSLOTSTATUS 0x2 125*1708Sstevel #define PCIMSG_SLOTEVENT 0x3 126*1708Sstevel 127*1708Sstevel /* Message Revisions */ 128*1708Sstevel #define PCIMSG_REVISION 0x10 129*1708Sstevel #define PCIMSG_REVISION_1_0 0x10 130*1708Sstevel 131*1708Sstevel /* 132*1708Sstevel * Values for the slot_condition field of the get slot status command. 133*1708Sstevel */ 134*1708Sstevel #define PCIMSG_SLOTCOND_UNKNOWN 0x0 135*1708Sstevel #define PCIMSG_SLOTCOND_GOOD 0x1 136*1708Sstevel #define PCIMSG_SLOTCOND_REC_FAIL 0x2 137*1708Sstevel #define PCIMSG_SLOTCOND_OCC_FAIL 0x3 138*1708Sstevel #define PCIMSG_SLOTCOND_NOHOTPLUG 0x4 139*1708Sstevel 140*1708Sstevel /* 141*1708Sstevel * Values for the slot_freq_cap and slot_freq_setting fields of the get 142*1708Sstevel * slot status command. 143*1708Sstevel */ 144*1708Sstevel #define PCIMSG_FREQ_33MHZ 0x0 145*1708Sstevel #define PCIMSG_FREQ_66MHZ 0x1 146*1708Sstevel #define PCIMSG_FREQ_90MHZ 0x2 147*1708Sstevel #define PCIMSG_FREQ_133MHZ 0x3 148*1708Sstevel 149*1708Sstevel /* 150*1708Sstevel * Values for the slot_mode_cap and slot_mode_setting of the get 151*1708Sstevel * slot status command. 152*1708Sstevel */ 153*1708Sstevel #define PCIMSG_MODE_CONVEN 0x0 154*1708Sstevel #define PCIMSG_MODE_PCIX 0x1 155*1708Sstevel 156*1708Sstevel /* 157*1708Sstevel * Values for the PRSNT signals. 158*1708Sstevel */ 159*1708Sstevel #define PCIMSG_PRSNT_NOADAPTER 0x0 160*1708Sstevel #define PCIMSG_PRSNT_25W 0x1 161*1708Sstevel #define PCIMSG_PRSNT_15W 0x2 162*1708Sstevel #define PCIMSG_PRSNT_7_5W 0x3 163*1708Sstevel 164*1708Sstevel /* 165*1708Sstevel * Values to turn on and off slot characteristics. 166*1708Sstevel */ 167*1708Sstevel #define PCIMSG_ON 0x1 168*1708Sstevel #define PCIMSG_OFF 0x0 169*1708Sstevel 170*1708Sstevel /* 171*1708Sstevel * Values to set the power, service and fault LEDs 172*1708Sstevel */ 173*1708Sstevel #define PCIMSG_LED_OFF 0x00 174*1708Sstevel #define PCIMSG_LED_ON 0x01 175*1708Sstevel #define PCIMSG_LED_FLASH 0x02 176*1708Sstevel 177*1708Sstevel /* 178*1708Sstevel * Return values for the slot_replystatus field for the get/set slot status 179*1708Sstevel * commands. 180*1708Sstevel */ 181*1708Sstevel #define PCIMSG_REPLY_GOOD 0x0 182*1708Sstevel #define PCIMSG_REPLY_FAIL 0x1 183*1708Sstevel 184*1708Sstevel #ifdef __cplusplus 185*1708Sstevel } 186*1708Sstevel #endif 187*1708Sstevel 188*1708Sstevel #endif /* _SYS_SCHPC_MSG_H */ 189