1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2003 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate #include <sys/param.h>
30*0Sstevel@tonic-gate #include <sys/systm.h>
31*0Sstevel@tonic-gate #include <sys/sysmacros.h>
32*0Sstevel@tonic-gate #include <sys/sunddi.h>
33*0Sstevel@tonic-gate #include <sys/esunddi.h>
34*0Sstevel@tonic-gate #include <sys/sunndi.h>
35*0Sstevel@tonic-gate
36*0Sstevel@tonic-gate #include <sys/platform_module.h>
37*0Sstevel@tonic-gate #include <sys/errno.h>
38*0Sstevel@tonic-gate
39*0Sstevel@tonic-gate #define SHARED_SMBUS_PATH "/pci@1f,0/pci@1,1/pmu@3/i2c@0,0/i2c-nvram@0,8e"
40*0Sstevel@tonic-gate static dev_info_t *shared_smbus_dip;
41*0Sstevel@tonic-gate static kmutex_t snowbird_smbus_mutex;
42*0Sstevel@tonic-gate
43*0Sstevel@tonic-gate void
startup_platform(void)44*0Sstevel@tonic-gate startup_platform(void)
45*0Sstevel@tonic-gate {
46*0Sstevel@tonic-gate mutex_init(&snowbird_smbus_mutex, NULL, NULL, NULL);
47*0Sstevel@tonic-gate }
48*0Sstevel@tonic-gate
49*0Sstevel@tonic-gate int
set_platform_tsb_spares()50*0Sstevel@tonic-gate set_platform_tsb_spares()
51*0Sstevel@tonic-gate {
52*0Sstevel@tonic-gate return (0);
53*0Sstevel@tonic-gate }
54*0Sstevel@tonic-gate
55*0Sstevel@tonic-gate void
set_platform_defaults(void)56*0Sstevel@tonic-gate set_platform_defaults(void)
57*0Sstevel@tonic-gate {
58*0Sstevel@tonic-gate extern char *tod_module_name;
59*0Sstevel@tonic-gate tod_module_name = "todds1307";
60*0Sstevel@tonic-gate }
61*0Sstevel@tonic-gate
62*0Sstevel@tonic-gate /*
63*0Sstevel@tonic-gate * Definitions for accessing the pci config space of the isa node
64*0Sstevel@tonic-gate * of Southbridge.
65*0Sstevel@tonic-gate */
66*0Sstevel@tonic-gate #define PLATFORM_ISA_PATHNAME "/pci@1f,0/isa@7"
67*0Sstevel@tonic-gate #define PLATFORM_ISA_PATHNAME_WITH_SIMBA "/pci@1f,0/pci@1,1/isa@7"
68*0Sstevel@tonic-gate ddi_acc_handle_t platform_isa_handle; /* handle for isa pci space */
69*0Sstevel@tonic-gate
70*0Sstevel@tonic-gate void
load_platform_drivers(void)71*0Sstevel@tonic-gate load_platform_drivers(void)
72*0Sstevel@tonic-gate {
73*0Sstevel@tonic-gate dev_info_t *dip; /* dip of the isa driver */
74*0Sstevel@tonic-gate
75*0Sstevel@tonic-gate if (ddi_install_driver("power") != DDI_SUCCESS)
76*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"power\" driver.");
77*0Sstevel@tonic-gate
78*0Sstevel@tonic-gate /*
79*0Sstevel@tonic-gate * It is OK to return error because 'us' driver is not available
80*0Sstevel@tonic-gate * in all clusters (e.g. missing in Core cluster).
81*0Sstevel@tonic-gate */
82*0Sstevel@tonic-gate (void) ddi_install_driver("us");
83*0Sstevel@tonic-gate
84*0Sstevel@tonic-gate /*
85*0Sstevel@tonic-gate * Install Isa driver. This is required for the southbridge IDE
86*0Sstevel@tonic-gate * workaround - to reset the IDE channel during IDE bus reset.
87*0Sstevel@tonic-gate * Panic the system in case ISA driver could not be loaded or
88*0Sstevel@tonic-gate * any problem in accessing its pci config space. Since the register
89*0Sstevel@tonic-gate * to reset the channel for IDE is in ISA config space!.
90*0Sstevel@tonic-gate */
91*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME_WITH_SIMBA, 0);
92*0Sstevel@tonic-gate
93*0Sstevel@tonic-gate if (dip == NULL)
94*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME, 0);
95*0Sstevel@tonic-gate
96*0Sstevel@tonic-gate if (dip == NULL) {
97*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not install the isa driver\n");
98*0Sstevel@tonic-gate return;
99*0Sstevel@tonic-gate }
100*0Sstevel@tonic-gate
101*0Sstevel@tonic-gate if (pci_config_setup(dip, &platform_isa_handle) != DDI_SUCCESS) {
102*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not get the config space of isa\n");
103*0Sstevel@tonic-gate return;
104*0Sstevel@tonic-gate }
105*0Sstevel@tonic-gate
106*0Sstevel@tonic-gate /*
107*0Sstevel@tonic-gate * Figure out which smbus_dip is shared with OBP for the nvram
108*0Sstevel@tonic-gate * device, so the lock can be acquired.
109*0Sstevel@tonic-gate *
110*0Sstevel@tonic-gate * This should really be done elsewhere, like startup_platform, but
111*0Sstevel@tonic-gate * that runs before the devinfo tree is setup with configure().
112*0Sstevel@tonic-gate * So it is here until there is a better place.
113*0Sstevel@tonic-gate */
114*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(SHARED_SMBUS_PATH, 0);
115*0Sstevel@tonic-gate
116*0Sstevel@tonic-gate if (dip != NULL) {
117*0Sstevel@tonic-gate ASSERT(dip != NULL);
118*0Sstevel@tonic-gate shared_smbus_dip = ddi_get_parent(dip);
119*0Sstevel@tonic-gate
120*0Sstevel@tonic-gate ndi_hold_devi(shared_smbus_dip);
121*0Sstevel@tonic-gate ndi_rele_devi(dip);
122*0Sstevel@tonic-gate } else {
123*0Sstevel@tonic-gate shared_smbus_dip = NULL;
124*0Sstevel@tonic-gate }
125*0Sstevel@tonic-gate
126*0Sstevel@tonic-gate /*
127*0Sstevel@tonic-gate * Install the TOD driver
128*0Sstevel@tonic-gate */
129*0Sstevel@tonic-gate if (ddi_install_driver("todds1307") != DDI_SUCCESS)
130*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"todds1307\" driver.");
131*0Sstevel@tonic-gate }
132*0Sstevel@tonic-gate
133*0Sstevel@tonic-gate /*
134*0Sstevel@tonic-gate * This routine provides a workaround for a bug in the SB chip which
135*0Sstevel@tonic-gate * can cause data corruption. Will be invoked from the IDE HBA driver for
136*0Sstevel@tonic-gate * Acer SouthBridge at the time of IDE bus reset.
137*0Sstevel@tonic-gate */
138*0Sstevel@tonic-gate /*ARGSUSED*/
139*0Sstevel@tonic-gate int
plat_ide_chipreset(dev_info_t * dip,int chno)140*0Sstevel@tonic-gate plat_ide_chipreset(dev_info_t *dip, int chno)
141*0Sstevel@tonic-gate {
142*0Sstevel@tonic-gate uint8_t val;
143*0Sstevel@tonic-gate int ret = DDI_SUCCESS;
144*0Sstevel@tonic-gate
145*0Sstevel@tonic-gate val = pci_config_get8(platform_isa_handle, 0x58);
146*0Sstevel@tonic-gate /*
147*0Sstevel@tonic-gate * The dip passed as the argument is not used for snowbird.
148*0Sstevel@tonic-gate * This will be needed for platforms which have multiple on-board SB,
149*0Sstevel@tonic-gate * The dip passed will be used to match the corresponding ISA node.
150*0Sstevel@tonic-gate */
151*0Sstevel@tonic-gate switch (chno) {
152*0Sstevel@tonic-gate case 0:
153*0Sstevel@tonic-gate /*
154*0Sstevel@tonic-gate * First disable the primary channel then re-enable it.
155*0Sstevel@tonic-gate * As per ALI no wait should be required in between have
156*0Sstevel@tonic-gate * given 1ms delay in between to be on safer side.
157*0Sstevel@tonic-gate * bit 2 of register 0x58 when 0 disable the channel 0.
158*0Sstevel@tonic-gate * bit 2 of register 0x58 when 1 enables the channel 0.
159*0Sstevel@tonic-gate */
160*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val & 0xFB);
161*0Sstevel@tonic-gate drv_usecwait(1000);
162*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val);
163*0Sstevel@tonic-gate break;
164*0Sstevel@tonic-gate case 1:
165*0Sstevel@tonic-gate /*
166*0Sstevel@tonic-gate * bit 3 of register 0x58 when 0 disable the channel 1.
167*0Sstevel@tonic-gate * bit 3 of register 0x58 when 1 enables the channel 1.
168*0Sstevel@tonic-gate */
169*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val & 0xF7);
170*0Sstevel@tonic-gate drv_usecwait(1000);
171*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val);
172*0Sstevel@tonic-gate break;
173*0Sstevel@tonic-gate default:
174*0Sstevel@tonic-gate /*
175*0Sstevel@tonic-gate * Unknown channel number passed. Return failure.
176*0Sstevel@tonic-gate */
177*0Sstevel@tonic-gate ret = DDI_FAILURE;
178*0Sstevel@tonic-gate }
179*0Sstevel@tonic-gate
180*0Sstevel@tonic-gate return (ret);
181*0Sstevel@tonic-gate }
182*0Sstevel@tonic-gate
183*0Sstevel@tonic-gate
184*0Sstevel@tonic-gate
185*0Sstevel@tonic-gate /*ARGSUSED*/
186*0Sstevel@tonic-gate int
plat_cpu_poweron(struct cpu * cp)187*0Sstevel@tonic-gate plat_cpu_poweron(struct cpu *cp)
188*0Sstevel@tonic-gate {
189*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
190*0Sstevel@tonic-gate }
191*0Sstevel@tonic-gate
192*0Sstevel@tonic-gate /*ARGSUSED*/
193*0Sstevel@tonic-gate int
plat_cpu_poweroff(struct cpu * cp)194*0Sstevel@tonic-gate plat_cpu_poweroff(struct cpu *cp)
195*0Sstevel@tonic-gate {
196*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
197*0Sstevel@tonic-gate }
198*0Sstevel@tonic-gate
199*0Sstevel@tonic-gate /*ARGSUSED*/
200*0Sstevel@tonic-gate void
plat_freelist_process(int mnode)201*0Sstevel@tonic-gate plat_freelist_process(int mnode)
202*0Sstevel@tonic-gate {
203*0Sstevel@tonic-gate }
204*0Sstevel@tonic-gate
205*0Sstevel@tonic-gate char *platform_module_list[] = {
206*0Sstevel@tonic-gate (char *)0
207*0Sstevel@tonic-gate };
208*0Sstevel@tonic-gate
209*0Sstevel@tonic-gate /*ARGSUSED*/
210*0Sstevel@tonic-gate void
plat_tod_fault(enum tod_fault_type tod_bad)211*0Sstevel@tonic-gate plat_tod_fault(enum tod_fault_type tod_bad)
212*0Sstevel@tonic-gate {
213*0Sstevel@tonic-gate }
214*0Sstevel@tonic-gate
215*0Sstevel@tonic-gate /*
216*0Sstevel@tonic-gate * Unfortunately, snowbird's smbus controller is used by both OBP
217*0Sstevel@tonic-gate * and the OS's i2c drivers. The 'eeprom' command executes
218*0Sstevel@tonic-gate * OBP code to handle property requests. If eeprom didn't do this, or if the
219*0Sstevel@tonic-gate * controllers were partitioned so that all devices on a given controller were
220*0Sstevel@tonic-gate * driven by either OBP or the OS, this wouldn't be necessary.
221*0Sstevel@tonic-gate *
222*0Sstevel@tonic-gate * Note that getprop doesn't have the same issue as it reads from cached
223*0Sstevel@tonic-gate * memory in OBP.
224*0Sstevel@tonic-gate */
225*0Sstevel@tonic-gate
226*0Sstevel@tonic-gate /*
227*0Sstevel@tonic-gate * Common locking enter code
228*0Sstevel@tonic-gate */
229*0Sstevel@tonic-gate void
plat_setprop_enter(void)230*0Sstevel@tonic-gate plat_setprop_enter(void)
231*0Sstevel@tonic-gate {
232*0Sstevel@tonic-gate mutex_enter(&snowbird_smbus_mutex);
233*0Sstevel@tonic-gate }
234*0Sstevel@tonic-gate
235*0Sstevel@tonic-gate /*
236*0Sstevel@tonic-gate * Common locking exit code
237*0Sstevel@tonic-gate */
238*0Sstevel@tonic-gate void
plat_setprop_exit(void)239*0Sstevel@tonic-gate plat_setprop_exit(void)
240*0Sstevel@tonic-gate {
241*0Sstevel@tonic-gate mutex_exit(&snowbird_smbus_mutex);
242*0Sstevel@tonic-gate }
243*0Sstevel@tonic-gate
244*0Sstevel@tonic-gate /*
245*0Sstevel@tonic-gate * Called by smbus driver
246*0Sstevel@tonic-gate */
247*0Sstevel@tonic-gate void
plat_shared_i2c_enter(dev_info_t * dip)248*0Sstevel@tonic-gate plat_shared_i2c_enter(dev_info_t *dip)
249*0Sstevel@tonic-gate {
250*0Sstevel@tonic-gate if (dip == shared_smbus_dip) {
251*0Sstevel@tonic-gate plat_setprop_enter();
252*0Sstevel@tonic-gate }
253*0Sstevel@tonic-gate }
254*0Sstevel@tonic-gate
255*0Sstevel@tonic-gate /*
256*0Sstevel@tonic-gate * Called by smbus driver
257*0Sstevel@tonic-gate */
258*0Sstevel@tonic-gate void
plat_shared_i2c_exit(dev_info_t * dip)259*0Sstevel@tonic-gate plat_shared_i2c_exit(dev_info_t *dip)
260*0Sstevel@tonic-gate {
261*0Sstevel@tonic-gate if (dip == shared_smbus_dip) {
262*0Sstevel@tonic-gate plat_setprop_exit();
263*0Sstevel@tonic-gate }
264*0Sstevel@tonic-gate }
265