xref: /onnv-gate/usr/src/uts/sun4u/os/cpc_subr.c (revision 12525:6680f9eca16d)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
52973Sgovinda  * Common Development and Distribution License (the "License").
62973Sgovinda  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
210Sstevel@tonic-gate /*
22*12525SChris.Baumbauer@Oracle.COM  * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved.
230Sstevel@tonic-gate  */
240Sstevel@tonic-gate 
250Sstevel@tonic-gate /*
260Sstevel@tonic-gate  * sun4u common CPC subroutines.
270Sstevel@tonic-gate  */
280Sstevel@tonic-gate 
290Sstevel@tonic-gate #include <sys/types.h>
300Sstevel@tonic-gate #include <sys/time.h>
310Sstevel@tonic-gate #include <sys/atomic.h>
320Sstevel@tonic-gate #include <sys/thread.h>
330Sstevel@tonic-gate #include <sys/regset.h>
340Sstevel@tonic-gate #include <sys/archsystm.h>
350Sstevel@tonic-gate #include <sys/machsystm.h>
360Sstevel@tonic-gate #include <sys/cpc_impl.h>
370Sstevel@tonic-gate #include <sys/cpc_ultra.h>
380Sstevel@tonic-gate #include <sys/sunddi.h>
390Sstevel@tonic-gate #include <sys/intr.h>
400Sstevel@tonic-gate #include <sys/ivintr.h>
410Sstevel@tonic-gate #include <sys/x_call.h>
420Sstevel@tonic-gate #include <sys/cpuvar.h>
430Sstevel@tonic-gate #include <sys/machcpuvar.h>
440Sstevel@tonic-gate #include <sys/cpc_pcbe.h>
450Sstevel@tonic-gate #include <sys/modctl.h>
460Sstevel@tonic-gate #include <sys/sdt.h>
4711389SAlexander.Kolbasov@Sun.COM #include <sys/kcpc.h>
480Sstevel@tonic-gate 
49*12525SChris.Baumbauer@Oracle.COM uint64_t	cpc_level15_inum = 0;	/* used in interrupt.s */
508803SJonathan.Haslam@Sun.COM int		cpc_has_overflow_intr;	/* set in cheetah.c */
510Sstevel@tonic-gate 
520Sstevel@tonic-gate extern kcpc_ctx_t *kcpc_overflow_intr(caddr_t arg, uint64_t bitmap);
530Sstevel@tonic-gate extern int kcpc_counts_include_idle;
540Sstevel@tonic-gate 
550Sstevel@tonic-gate /*
560Sstevel@tonic-gate  * Called on the boot CPU during startup.
570Sstevel@tonic-gate  */
580Sstevel@tonic-gate void
kcpc_hw_init(void)590Sstevel@tonic-gate kcpc_hw_init(void)
600Sstevel@tonic-gate {
61*12525SChris.Baumbauer@Oracle.COM 	if ((cpc_has_overflow_intr) && (cpc_level15_inum == 0)) {
620Sstevel@tonic-gate 		cpc_level15_inum = add_softintr(PIL_15,
632973Sgovinda 		    kcpc_hw_overflow_intr, NULL, SOFTINT_MT);
640Sstevel@tonic-gate 	}
650Sstevel@tonic-gate 
660Sstevel@tonic-gate 	/*
670Sstevel@tonic-gate 	 * Make sure the boot CPU gets set up.
680Sstevel@tonic-gate 	 */
690Sstevel@tonic-gate 	kcpc_hw_startup_cpu(CPU->cpu_flags);
700Sstevel@tonic-gate }
710Sstevel@tonic-gate 
720Sstevel@tonic-gate /*
730Sstevel@tonic-gate  * Prepare for CPC interrupts and install an idle thread CPC context.
740Sstevel@tonic-gate  */
750Sstevel@tonic-gate void
kcpc_hw_startup_cpu(ushort_t cpflags)760Sstevel@tonic-gate kcpc_hw_startup_cpu(ushort_t cpflags)
770Sstevel@tonic-gate {
780Sstevel@tonic-gate 	cpu_t		*cp = CPU;
790Sstevel@tonic-gate 	kthread_t	*t = cp->cpu_idle_thread;
800Sstevel@tonic-gate 
810Sstevel@tonic-gate 	ASSERT(t->t_bound_cpu == cp);
820Sstevel@tonic-gate 
830Sstevel@tonic-gate 	if (cpc_has_overflow_intr && (cpflags & CPU_FROZEN) == 0) {
840Sstevel@tonic-gate 		int pstate_save = disable_vec_intr();
850Sstevel@tonic-gate 
860Sstevel@tonic-gate 		ASSERT(cpc_level15_inum != 0);
870Sstevel@tonic-gate 
880Sstevel@tonic-gate 		intr_enqueue_req(PIL_15, cpc_level15_inum);
890Sstevel@tonic-gate 		enable_vec_intr(pstate_save);
900Sstevel@tonic-gate 	}
910Sstevel@tonic-gate 
920Sstevel@tonic-gate 	mutex_init(&cp->cpu_cpc_ctxlock, "cpu_cpc_ctxlock", MUTEX_DEFAULT, 0);
930Sstevel@tonic-gate 
940Sstevel@tonic-gate 	if (kcpc_counts_include_idle)
950Sstevel@tonic-gate 		return;
960Sstevel@tonic-gate 
970Sstevel@tonic-gate 	installctx(t, cp, kcpc_idle_save, kcpc_idle_restore, NULL, NULL,
980Sstevel@tonic-gate 	    NULL, NULL);
990Sstevel@tonic-gate }
1000Sstevel@tonic-gate 
1010Sstevel@tonic-gate /*
1020Sstevel@tonic-gate  * Examine the processor and load an appropriate PCBE.
1030Sstevel@tonic-gate  */
1040Sstevel@tonic-gate int
kcpc_hw_load_pcbe(void)1050Sstevel@tonic-gate kcpc_hw_load_pcbe(void)
1060Sstevel@tonic-gate {
1070Sstevel@tonic-gate 	uint64_t	ver = ultra_getver();
1080Sstevel@tonic-gate 
1090Sstevel@tonic-gate 	return (kcpc_pcbe_tryload(NULL, ULTRA_VER_MANUF(ver),
1100Sstevel@tonic-gate 	    ULTRA_VER_IMPL(ver), ULTRA_VER_MASK(ver)));
1110Sstevel@tonic-gate }
1120Sstevel@tonic-gate 
1130Sstevel@tonic-gate /*ARGSUSED*/
1140Sstevel@tonic-gate int
kcpc_hw_cpu_hook(processorid_t cpuid,ulong_t * kcpc_cpumap)1150Sstevel@tonic-gate kcpc_hw_cpu_hook(processorid_t cpuid, ulong_t *kcpc_cpumap)
1160Sstevel@tonic-gate {
1170Sstevel@tonic-gate 	return (0);
1180Sstevel@tonic-gate }
1190Sstevel@tonic-gate 
1200Sstevel@tonic-gate int
kcpc_hw_lwp_hook(void)1210Sstevel@tonic-gate kcpc_hw_lwp_hook(void)
1220Sstevel@tonic-gate {
1230Sstevel@tonic-gate 	return (0);
1240Sstevel@tonic-gate }
125