1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/machsystm.h> 31*0Sstevel@tonic-gate #include <sys/x_call.h> 32*0Sstevel@tonic-gate #include <sys/cmp.h> 33*0Sstevel@tonic-gate #include <sys/debug.h> 34*0Sstevel@tonic-gate #include <sys/chip.h> 35*0Sstevel@tonic-gate #include <sys/cheetahregs.h> 36*0Sstevel@tonic-gate 37*0Sstevel@tonic-gate /* 38*0Sstevel@tonic-gate * Note: We assume that chipid == portid. This is not necessarily true. 39*0Sstevel@tonic-gate * We buried it down here in the implementation, and not in the 40*0Sstevel@tonic-gate * interfaces, so that we can change it later. 41*0Sstevel@tonic-gate */ 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate /* 44*0Sstevel@tonic-gate * pre-alloc'ed because this is used early in boot (before the memory 45*0Sstevel@tonic-gate * allocator is available). 46*0Sstevel@tonic-gate */ 47*0Sstevel@tonic-gate static cpuset_t chips[MAX_CPU_CHIPID]; 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate /* 50*0Sstevel@tonic-gate * Returns 1 if cpuid is CMP-capable, 0 otherwise. 51*0Sstevel@tonic-gate */ 52*0Sstevel@tonic-gate int 53*0Sstevel@tonic-gate cmp_cpu_is_cmp(processorid_t cpuid) 54*0Sstevel@tonic-gate { 55*0Sstevel@tonic-gate chipid_t chipid; 56*0Sstevel@tonic-gate 57*0Sstevel@tonic-gate /* N.B. We're assuming that the cpunode[].portid is still intact */ 58*0Sstevel@tonic-gate chipid = cpunodes[cpuid].portid; 59*0Sstevel@tonic-gate return (!CPUSET_ISNULL(chips[chipid])); 60*0Sstevel@tonic-gate } 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate /* 63*0Sstevel@tonic-gate * Indicate that this core (cpuid) resides on the chip indicated by chipid. 64*0Sstevel@tonic-gate * Called during boot and DR add. 65*0Sstevel@tonic-gate */ 66*0Sstevel@tonic-gate void 67*0Sstevel@tonic-gate cmp_add_cpu(chipid_t chipid, processorid_t cpuid) 68*0Sstevel@tonic-gate { 69*0Sstevel@tonic-gate CPUSET_ADD(chips[chipid], cpuid); 70*0Sstevel@tonic-gate } 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate /* 73*0Sstevel@tonic-gate * Indicate that this core (cpuid) is being DR removed. 74*0Sstevel@tonic-gate */ 75*0Sstevel@tonic-gate void 76*0Sstevel@tonic-gate cmp_delete_cpu(processorid_t cpuid) 77*0Sstevel@tonic-gate { 78*0Sstevel@tonic-gate chipid_t chipid; 79*0Sstevel@tonic-gate 80*0Sstevel@tonic-gate /* N.B. We're assuming that the cpunode[].portid is still intact */ 81*0Sstevel@tonic-gate chipid = cpunodes[cpuid].portid; 82*0Sstevel@tonic-gate CPUSET_DEL(chips[chipid], cpuid); 83*0Sstevel@tonic-gate } 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate /* 86*0Sstevel@tonic-gate * Called when cpuid is being onlined or offlined. If the offlined 87*0Sstevel@tonic-gate * processor is CMP-capable then current target of the CMP Error Steering 88*0Sstevel@tonic-gate * Register is set to either the lowest numbered on-line sibling core, if 89*0Sstevel@tonic-gate * one exists, or else to this core. 90*0Sstevel@tonic-gate */ 91*0Sstevel@tonic-gate void 92*0Sstevel@tonic-gate cmp_error_resteer(processorid_t cpuid) 93*0Sstevel@tonic-gate { 94*0Sstevel@tonic-gate cpuset_t mycores; 95*0Sstevel@tonic-gate cpu_t *cpu; 96*0Sstevel@tonic-gate chipid_t chipid; 97*0Sstevel@tonic-gate int i; 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate if (!cmp_cpu_is_cmp(cpuid)) 100*0Sstevel@tonic-gate return; 101*0Sstevel@tonic-gate 102*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 103*0Sstevel@tonic-gate chipid = cpunodes[cpuid].portid; 104*0Sstevel@tonic-gate mycores = chips[chipid]; 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate /* Look for an online sibling core */ 107*0Sstevel@tonic-gate for (i = 0; i < NCPU; i++) { 108*0Sstevel@tonic-gate if (i == cpuid) 109*0Sstevel@tonic-gate continue; 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate if (CPU_IN_SET(mycores, i) && 112*0Sstevel@tonic-gate (cpu = cpu_get(i)) != NULL && cpu_is_active(cpu)) { 113*0Sstevel@tonic-gate /* Found one, reset error steering */ 114*0Sstevel@tonic-gate xc_one(i, (xcfunc_t *)set_cmp_error_steering, 0, 0); 115*0Sstevel@tonic-gate break; 116*0Sstevel@tonic-gate } 117*0Sstevel@tonic-gate } 118*0Sstevel@tonic-gate 119*0Sstevel@tonic-gate /* No online sibling cores, point to this core. */ 120*0Sstevel@tonic-gate if (i == NCPU) { 121*0Sstevel@tonic-gate xc_one(cpuid, (xcfunc_t *)set_cmp_error_steering, 0, 0); 122*0Sstevel@tonic-gate } 123*0Sstevel@tonic-gate } 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate chipid_t 126*0Sstevel@tonic-gate cmp_cpu_to_chip(processorid_t cpuid) 127*0Sstevel@tonic-gate { 128*0Sstevel@tonic-gate if (!cmp_cpu_is_cmp(cpuid)) { 129*0Sstevel@tonic-gate /* This CPU is not a CMP, so by definition chipid==cpuid */ 130*0Sstevel@tonic-gate ASSERT(cpuid < MAX_CPU_CHIPID && CPUSET_ISNULL(chips[cpuid])); 131*0Sstevel@tonic-gate return (cpuid); 132*0Sstevel@tonic-gate } 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate /* N.B. We're assuming that the cpunode[].portid is still intact */ 135*0Sstevel@tonic-gate return (cpunodes[cpuid].portid); 136*0Sstevel@tonic-gate } 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate /* 139*0Sstevel@tonic-gate * Return a chip "id" for the given cpu_t 140*0Sstevel@tonic-gate * cpu_t's residing on the same physical processor 141*0Sstevel@tonic-gate * should map to the same "id" 142*0Sstevel@tonic-gate */ 143*0Sstevel@tonic-gate chipid_t 144*0Sstevel@tonic-gate chip_plat_get_chipid(cpu_t *cp) 145*0Sstevel@tonic-gate { 146*0Sstevel@tonic-gate return (cmp_cpu_to_chip(cp->cpu_id)); 147*0Sstevel@tonic-gate } 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate void 150*0Sstevel@tonic-gate chip_plat_define_chip(cpu_t *cp, chip_def_t *cd) 151*0Sstevel@tonic-gate { 152*0Sstevel@tonic-gate int impl; 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate /* 155*0Sstevel@tonic-gate * Define the chip's type 156*0Sstevel@tonic-gate */ 157*0Sstevel@tonic-gate impl = cpunodes[cp->cpu_id].implementation; 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate if (IS_JAGUAR(impl)) { 160*0Sstevel@tonic-gate cd->chipd_type = CHIP_CMP_SPLIT_CACHE; 161*0Sstevel@tonic-gate } else if (IS_PANTHER(impl)) { 162*0Sstevel@tonic-gate cd->chipd_type = CHIP_CMP_SHARED_CACHE; 163*0Sstevel@tonic-gate } else { 164*0Sstevel@tonic-gate cd->chipd_type = CHIP_DEFAULT; 165*0Sstevel@tonic-gate } 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate /* 168*0Sstevel@tonic-gate * Define any needed adjustment of rechoose_interval 169*0Sstevel@tonic-gate * For now, all chips use the default. This 170*0Sstevel@tonic-gate * will change with future processors. 171*0Sstevel@tonic-gate */ 172*0Sstevel@tonic-gate cd->chipd_rechoose_adj = 0; 173*0Sstevel@tonic-gate } 174