xref: /onnv-gate/usr/src/uts/sun4u/opl/ml/drmach.il.cpp (revision 3517:79d66aa80b8b)
11772Sjl139090 /*
21772Sjl139090  * CDDL HEADER START
31772Sjl139090  *
41772Sjl139090  * The contents of this file are subject to the terms of the
51772Sjl139090  * Common Development and Distribution License (the "License").
61772Sjl139090  * You may not use this file except in compliance with the License.
71772Sjl139090  *
81772Sjl139090  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
91772Sjl139090  * or http://www.opensolaris.org/os/licensing.
101772Sjl139090  * See the License for the specific language governing permissions
111772Sjl139090  * and limitations under the License.
121772Sjl139090  *
131772Sjl139090  * When distributing Covered Code, include this CDDL HEADER in each
141772Sjl139090  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
151772Sjl139090  * If applicable, add the following below this CDDL HEADER, with the
161772Sjl139090  * fields enclosed by brackets "[]" replaced with your own identifying
171772Sjl139090  * information: Portions Copyright [yyyy] [name of copyright owner]
181772Sjl139090  *
191772Sjl139090  * CDDL HEADER END
201772Sjl139090  */
211772Sjl139090 /*
223354Sjl139090  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
231772Sjl139090  * Use is subject to license terms.
241772Sjl139090  */
251772Sjl139090 
261772Sjl139090 #pragma ident	"%Z%%M%	%I%	%E% SMI"
271772Sjl139090 
281772Sjl139090 
291772Sjl139090 /*
301772Sjl139090  * This file is through cpp before being used as
311772Sjl139090  * an inline.  It contains support routines used
321772Sjl139090  * only by DR for the copy-rename sequence.
331772Sjl139090  */
341772Sjl139090 
351772Sjl139090 #if defined(lint)
361772Sjl139090 #include <sys/types.h>
371772Sjl139090 #endif /* lint */
381772Sjl139090 
391772Sjl139090 #ifndef	INLINE
401772Sjl139090 
411772Sjl139090 #include <sys/asm_linkage.h>
421772Sjl139090 
431772Sjl139090 #else /* INLINE */
441772Sjl139090 
451772Sjl139090 #define	ENTRY_NP(x)	.inline	x,0
461772Sjl139090 #define	retl		/* nop */
471772Sjl139090 #define	SET_SIZE(x)	.end
481772Sjl139090 
491772Sjl139090 #endif /* INLINE */
501772Sjl139090 
511772Sjl139090 #include <sys/privregs.h>
521772Sjl139090 #include <sys/sun4asi.h>
531772Sjl139090 #include <sys/machparam.h>
541772Sjl139090 
551772Sjl139090 #include <sys/intreg.h>
561772Sjl139090 #include <sys/opl_olympus_regs.h>
571772Sjl139090 
581772Sjl139090 /*
591772Sjl139090  * Bcopy routine used by DR to copy
601772Sjl139090  * between physical addresses.
611772Sjl139090  * Borrowed from Starfire DR 2.6.
621772Sjl139090  */
631772Sjl139090 #if defined(lint)
641772Sjl139090 
651772Sjl139090 /*ARGSUSED*/
661772Sjl139090 void
bcopy32_il(uint64_t paddr1,uint64_t paddr2)671772Sjl139090 bcopy32_il(uint64_t paddr1, uint64_t paddr2)
681772Sjl139090 {}
691772Sjl139090 
701772Sjl139090 #else /* lint */
711772Sjl139090 
721772Sjl139090 	ENTRY_NP(bcopy32_il)
731772Sjl139090 	.register %g2, #scratch
741772Sjl139090 	.register %g3, #scratch
751772Sjl139090 	rdpr	%pstate, %g0
761772Sjl139090 	ldxa	[%o0]ASI_MEM, %o2
771772Sjl139090 	add	%o0, 8, %o0
781772Sjl139090 	ldxa	[%o0]ASI_MEM, %o3
791772Sjl139090 	add	%o0, 8, %o0
801772Sjl139090 	ldxa	[%o0]ASI_MEM, %g1
811772Sjl139090 	add	%o0, 8, %o0
821772Sjl139090 	ldxa	[%o0]ASI_MEM, %g2
831772Sjl139090 
841772Sjl139090 	stxa	%o2, [%o1]ASI_MEM
851772Sjl139090 	add	%o1, 8, %o1
861772Sjl139090 	stxa	%o3, [%o1]ASI_MEM
871772Sjl139090 	add	%o1, 8, %o1
881772Sjl139090 	stxa	%g1, [%o1]ASI_MEM
891772Sjl139090 	add	%o1, 8, %o1
901772Sjl139090 	stxa	%g2, [%o1]ASI_MEM
911772Sjl139090 
921772Sjl139090 	retl
931772Sjl139090 	nop
941772Sjl139090 	SET_SIZE(bcopy32_il)
951772Sjl139090 
961772Sjl139090 #endif /* lint */
971772Sjl139090 
981772Sjl139090 #if defined(lint)
991772Sjl139090 
1001772Sjl139090 /*ARGSUSED*/
1011772Sjl139090 void
1021772Sjl139090 flush_cache_il(void)
1031772Sjl139090 {}
1041772Sjl139090 
1051772Sjl139090 #else /* lint */
1061772Sjl139090 
1071772Sjl139090 	ENTRY_NP(flush_cache_il)
1081772Sjl139090 	rdpr	%pstate, %o3
1091772Sjl139090 	andn	%o3, PSTATE_IE, %o4
1101772Sjl139090 	wrpr	%g0, %o4, %pstate
1111772Sjl139090 	mov	ASI_L2_CTRL_U2_FLUSH, %o4
1121772Sjl139090 	mov	ASI_L2_CTRL_RW_ADDR, %o5
1131772Sjl139090 	stxa	%o4, [%o5]ASI_L2_CTRL
1141772Sjl139090 	! retl
1151772Sjl139090 	wrpr	%g0, %o3, %pstate	! restore earlier pstate
1161772Sjl139090 	SET_SIZE(flush_cache_il)
1171772Sjl139090 
1181772Sjl139090 #endif /* lint */
1191772Sjl139090 
1201772Sjl139090 #if defined(lint)
1211772Sjl139090 /* ARGUSED */
1221772Sjl139090 uint64_t
drmach_get_stick_il(void)1231772Sjl139090 drmach_get_stick_il(void)
1241772Sjl139090 {}
1251772Sjl139090 
1261772Sjl139090 #else /* lint */
ENTRY_NP(drmach_get_stick_il)1271772Sjl139090 	ENTRY_NP(drmach_get_stick_il)
1281772Sjl139090 	retl
1291772Sjl139090 	rd	STICK, %o0
1301772Sjl139090 	SET_SIZE(drmach_get_stick_il)
1311772Sjl139090 #endif /* lint */
1321772Sjl139090 
1331772Sjl139090 #if defined(lint)
1341772Sjl139090 /* ARGUSED */
1351772Sjl139090 void
1361772Sjl139090 membar_sync_il(void)
1371772Sjl139090 {}
1381772Sjl139090 
1391772Sjl139090 #else /* lint */
1401772Sjl139090 	ENTRY_NP(membar_sync_il)
1411772Sjl139090 	retl
1421772Sjl139090 	membar #Sync
1431772Sjl139090 	SET_SIZE(membar_sync_il)
1441772Sjl139090 #endif /* lint */
1451772Sjl139090 
1461772Sjl139090 
1471772Sjl139090 #if defined(lint)
1481772Sjl139090 
1491772Sjl139090 /* ARGSUSED */
1501772Sjl139090 void
flush_instr_mem_il(caddr_t vaddr)1511772Sjl139090 flush_instr_mem_il(caddr_t vaddr)
1521772Sjl139090 {}
1531772Sjl139090 
1541772Sjl139090 #else	/* lint */
1551772Sjl139090 
1561772Sjl139090 /*
1571772Sjl139090  * flush_instr_mem:
1581772Sjl139090  *	Flush 1 page of the I-$ starting at vaddr
1591772Sjl139090  * 	%o0 vaddr
1601772Sjl139090  *
1611772Sjl139090  * SPARC64-VI maintains consistency of the on-chip Instruction Cache with
1621772Sjl139090  * the stores from all processors so that a FLUSH instruction is only needed
1631772Sjl139090  * to ensure pipeline is consistent. This means a single flush is sufficient at
1641772Sjl139090  * the end of a sequence of stores that updates the instruction stream to
1651772Sjl139090  * ensure correct operation.
1661772Sjl139090  */
1671772Sjl139090 
1681772Sjl139090 	ENTRY_NP(flush_instr_mem_il)
169*3517Smp204432 	flush	%o0			! address irrelevant
1701772Sjl139090 	retl
1713354Sjl139090 	 nop
1721772Sjl139090 	SET_SIZE(flush_instr_mem_il)
1731772Sjl139090 
1741772Sjl139090 #endif	/* lint */
1751772Sjl139090 
1761772Sjl139090 #if defined(lint)
1771772Sjl139090 
1781772Sjl139090 /* ARGSUSED */
1791772Sjl139090 void
1801772Sjl139090 drmach_sleep_il(void)
1811772Sjl139090 {}
1821772Sjl139090 
1831772Sjl139090 #else	/* lint */
1841772Sjl139090 
1851772Sjl139090 /*
1861772Sjl139090  * drmach-sleep_il:
1871772Sjl139090  *
1881772Sjl139090  * busy loop wait can affect performance of the sibling strand
1891772Sjl139090  * the sleep instruction can be used to avoid that.
1901772Sjl139090  */
1911772Sjl139090 
1921772Sjl139090 	ENTRY_NP(drmach_sleep_il)
1931772Sjl139090 .word	0x81b01060
1943354Sjl139090 	retl
1953354Sjl139090 	 nop
1963354Sjl139090 	SET_SIZE(drmach_sleep_il)
1971772Sjl139090 
1981772Sjl139090 #endif	/* lint */
1993354Sjl139090 
2003354Sjl139090 #if defined(lint)
2013354Sjl139090 
2023354Sjl139090 /* ARGSUSED */
2033354Sjl139090 void
flush_windows_il(void)2043354Sjl139090 flush_windows_il(void)
2053354Sjl139090 {}
2063354Sjl139090 
2073354Sjl139090 #else	/* lint */
2083354Sjl139090 
2093354Sjl139090 /*
2103354Sjl139090  * flush_windows_il:
2113354Sjl139090  *
2123354Sjl139090  */
2133354Sjl139090 
2143354Sjl139090 	ENTRY_NP(flush_windows_il)
2153354Sjl139090 	retl
2163354Sjl139090 	 flushw
2173354Sjl139090 	SET_SIZE(flush_windows_il)
2183354Sjl139090 
2193354Sjl139090 #endif	/* lint */
220