1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/kmem.h> 31*0Sstevel@tonic-gate #include <sys/conf.h> 32*0Sstevel@tonic-gate #include <sys/ddi.h> 33*0Sstevel@tonic-gate #include <sys/sunddi.h> 34*0Sstevel@tonic-gate #include <sys/modctl.h> 35*0Sstevel@tonic-gate #include <sys/disp.h> 36*0Sstevel@tonic-gate #include <sys/stat.h> 37*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 38*0Sstevel@tonic-gate #include <sys/vmem.h> 39*0Sstevel@tonic-gate #include <sys/iommutsb.h> 40*0Sstevel@tonic-gate #include <sys/cpuvar.h> 41*0Sstevel@tonic-gate #include <px_obj.h> 42*0Sstevel@tonic-gate #include <pcie_pwr.h> 43*0Sstevel@tonic-gate #include "px_tools_var.h" 44*0Sstevel@tonic-gate #include <px_regs.h> 45*0Sstevel@tonic-gate #include <px_csr.h> 46*0Sstevel@tonic-gate #include "px_lib4u.h" 47*0Sstevel@tonic-gate 48*0Sstevel@tonic-gate #pragma weak jbus_stst_order 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate extern void jbus_stst_order(); 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate ulong_t px_mmu_dvma_end = 0xfffffffful; 53*0Sstevel@tonic-gate uint_t px_ranges_phi_mask = 0xfffffffful; 54*0Sstevel@tonic-gate 55*0Sstevel@tonic-gate static int px_goto_l23ready(px_t *px_p); 56*0Sstevel@tonic-gate static uint32_t px_identity_chip(px_t *px_p); 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate int 59*0Sstevel@tonic-gate px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 60*0Sstevel@tonic-gate { 61*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 62*0Sstevel@tonic-gate caddr_t xbc_csr_base = (caddr_t)px_p->px_address[PX_REG_XBC]; 63*0Sstevel@tonic-gate caddr_t csr_base = (caddr_t)px_p->px_address[PX_REG_CSR]; 64*0Sstevel@tonic-gate px_dvma_range_prop_t px_dvma_range; 65*0Sstevel@tonic-gate uint32_t chip_id; 66*0Sstevel@tonic-gate pxu_t *pxu_p; 67*0Sstevel@tonic-gate 68*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p\n", dip); 69*0Sstevel@tonic-gate 70*0Sstevel@tonic-gate if ((chip_id = px_identity_chip(px_p)) == PX_CHIP_UNIDENTIFIED) 71*0Sstevel@tonic-gate return (DDI_FAILURE); 72*0Sstevel@tonic-gate 73*0Sstevel@tonic-gate switch (chip_id) { 74*0Sstevel@tonic-gate case FIRE_VER_10: 75*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "FIRE Hardware Version 1.0\n"); 76*0Sstevel@tonic-gate break; 77*0Sstevel@tonic-gate case FIRE_VER_20: 78*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "FIRE Hardware Version 2.0\n"); 79*0Sstevel@tonic-gate break; 80*0Sstevel@tonic-gate default: 81*0Sstevel@tonic-gate cmn_err(CE_WARN, "%s(%d): FIRE Hardware Version Unknown\n", 82*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 83*0Sstevel@tonic-gate return (DDI_FAILURE); 84*0Sstevel@tonic-gate } 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate /* 87*0Sstevel@tonic-gate * Allocate platform specific structure and link it to 88*0Sstevel@tonic-gate * the px state structure. 89*0Sstevel@tonic-gate */ 90*0Sstevel@tonic-gate pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP); 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate pxu_p->chip_id = chip_id; 93*0Sstevel@tonic-gate pxu_p->portid = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 94*0Sstevel@tonic-gate "portid", -1); 95*0Sstevel@tonic-gate 96*0Sstevel@tonic-gate /* 97*0Sstevel@tonic-gate * XXX - Move all ddi_regs_map_setup() from px_util.c 98*0Sstevel@tonic-gate * to to this file before complete virtualization. 99*0Sstevel@tonic-gate */ 100*0Sstevel@tonic-gate pxu_p->tsb_cookie = iommu_tsb_alloc(pxu_p->portid); 101*0Sstevel@tonic-gate pxu_p->tsb_size = iommu_tsb_cookie_to_size(pxu_p->tsb_cookie); 102*0Sstevel@tonic-gate pxu_p->tsb_vaddr = iommu_tsb_cookie_to_va(pxu_p->tsb_cookie); 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate /* 105*0Sstevel@tonic-gate * Create "virtual-dma" property to support child devices 106*0Sstevel@tonic-gate * needing to know DVMA range. 107*0Sstevel@tonic-gate */ 108*0Sstevel@tonic-gate px_dvma_range.dvma_base = (uint32_t)px_mmu_dvma_end + 1 109*0Sstevel@tonic-gate - ((pxu_p->tsb_size >> 3) << MMU_PAGE_SHIFT); 110*0Sstevel@tonic-gate px_dvma_range.dvma_len = (uint32_t) 111*0Sstevel@tonic-gate px_mmu_dvma_end - px_dvma_range.dvma_base + 1; 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 114*0Sstevel@tonic-gate "virtual-dma", (caddr_t)&px_dvma_range, 115*0Sstevel@tonic-gate sizeof (px_dvma_range_prop_t)); 116*0Sstevel@tonic-gate /* 117*0Sstevel@tonic-gate * Initilize all fire hardware specific blocks. 118*0Sstevel@tonic-gate */ 119*0Sstevel@tonic-gate hvio_cb_init(xbc_csr_base, pxu_p); 120*0Sstevel@tonic-gate hvio_ib_init(csr_base, pxu_p); 121*0Sstevel@tonic-gate hvio_pec_init(csr_base, pxu_p); 122*0Sstevel@tonic-gate hvio_mmu_init(csr_base, pxu_p); 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate px_p->px_plat_p = (void *)pxu_p; 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate /* Initilize device handle */ 127*0Sstevel@tonic-gate *dev_hdl = (devhandle_t)csr_base; 128*0Sstevel@tonic-gate 129*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate return (DDI_SUCCESS); 132*0Sstevel@tonic-gate } 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate int 135*0Sstevel@tonic-gate px_lib_dev_fini(dev_info_t *dip) 136*0Sstevel@tonic-gate { 137*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 138*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 139*0Sstevel@tonic-gate 140*0Sstevel@tonic-gate DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate iommu_tsb_free(pxu_p->tsb_cookie); 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate px_p->px_plat_p = NULL; 145*0Sstevel@tonic-gate kmem_free(pxu_p, sizeof (pxu_t)); 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate return (DDI_SUCCESS); 148*0Sstevel@tonic-gate } 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate /*ARGSUSED*/ 151*0Sstevel@tonic-gate int 152*0Sstevel@tonic-gate px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 153*0Sstevel@tonic-gate sysino_t *sysino) 154*0Sstevel@tonic-gate { 155*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 156*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 157*0Sstevel@tonic-gate uint64_t ret; 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 160*0Sstevel@tonic-gate "devino 0x%x\n", dip, devino); 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 163*0Sstevel@tonic-gate pxu_p, devino, sysino)) != H_EOK) { 164*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, 165*0Sstevel@tonic-gate "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 166*0Sstevel@tonic-gate return (DDI_FAILURE); 167*0Sstevel@tonic-gate } 168*0Sstevel@tonic-gate 169*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 170*0Sstevel@tonic-gate *sysino); 171*0Sstevel@tonic-gate 172*0Sstevel@tonic-gate return (DDI_SUCCESS); 173*0Sstevel@tonic-gate } 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate /*ARGSUSED*/ 176*0Sstevel@tonic-gate int 177*0Sstevel@tonic-gate px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 178*0Sstevel@tonic-gate intr_valid_state_t *intr_valid_state) 179*0Sstevel@tonic-gate { 180*0Sstevel@tonic-gate uint64_t ret; 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 183*0Sstevel@tonic-gate dip, sysino); 184*0Sstevel@tonic-gate 185*0Sstevel@tonic-gate if ((ret = hvio_intr_getvalid(DIP_TO_HANDLE(dip), 186*0Sstevel@tonic-gate sysino, intr_valid_state)) != H_EOK) { 187*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 188*0Sstevel@tonic-gate ret); 189*0Sstevel@tonic-gate return (DDI_FAILURE); 190*0Sstevel@tonic-gate } 191*0Sstevel@tonic-gate 192*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 193*0Sstevel@tonic-gate *intr_valid_state); 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate return (DDI_SUCCESS); 196*0Sstevel@tonic-gate } 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate /*ARGSUSED*/ 199*0Sstevel@tonic-gate int 200*0Sstevel@tonic-gate px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 201*0Sstevel@tonic-gate intr_valid_state_t intr_valid_state) 202*0Sstevel@tonic-gate { 203*0Sstevel@tonic-gate uint64_t ret; 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 206*0Sstevel@tonic-gate "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 207*0Sstevel@tonic-gate 208*0Sstevel@tonic-gate if ((ret = hvio_intr_setvalid(DIP_TO_HANDLE(dip), 209*0Sstevel@tonic-gate sysino, intr_valid_state)) != H_EOK) { 210*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 211*0Sstevel@tonic-gate ret); 212*0Sstevel@tonic-gate return (DDI_FAILURE); 213*0Sstevel@tonic-gate } 214*0Sstevel@tonic-gate 215*0Sstevel@tonic-gate return (DDI_SUCCESS); 216*0Sstevel@tonic-gate } 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate /*ARGSUSED*/ 219*0Sstevel@tonic-gate int 220*0Sstevel@tonic-gate px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 221*0Sstevel@tonic-gate intr_state_t *intr_state) 222*0Sstevel@tonic-gate { 223*0Sstevel@tonic-gate uint64_t ret; 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 226*0Sstevel@tonic-gate dip, sysino); 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate if ((ret = hvio_intr_getstate(DIP_TO_HANDLE(dip), 229*0Sstevel@tonic-gate sysino, intr_state)) != H_EOK) { 230*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 231*0Sstevel@tonic-gate ret); 232*0Sstevel@tonic-gate return (DDI_FAILURE); 233*0Sstevel@tonic-gate } 234*0Sstevel@tonic-gate 235*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 236*0Sstevel@tonic-gate *intr_state); 237*0Sstevel@tonic-gate 238*0Sstevel@tonic-gate return (DDI_SUCCESS); 239*0Sstevel@tonic-gate } 240*0Sstevel@tonic-gate 241*0Sstevel@tonic-gate /*ARGSUSED*/ 242*0Sstevel@tonic-gate int 243*0Sstevel@tonic-gate px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 244*0Sstevel@tonic-gate intr_state_t intr_state) 245*0Sstevel@tonic-gate { 246*0Sstevel@tonic-gate uint64_t ret; 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 249*0Sstevel@tonic-gate "intr_state 0x%x\n", dip, sysino, intr_state); 250*0Sstevel@tonic-gate 251*0Sstevel@tonic-gate if ((ret = hvio_intr_setstate(DIP_TO_HANDLE(dip), 252*0Sstevel@tonic-gate sysino, intr_state)) != H_EOK) { 253*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 254*0Sstevel@tonic-gate ret); 255*0Sstevel@tonic-gate return (DDI_FAILURE); 256*0Sstevel@tonic-gate } 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate return (DDI_SUCCESS); 259*0Sstevel@tonic-gate } 260*0Sstevel@tonic-gate 261*0Sstevel@tonic-gate /*ARGSUSED*/ 262*0Sstevel@tonic-gate int 263*0Sstevel@tonic-gate px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 264*0Sstevel@tonic-gate { 265*0Sstevel@tonic-gate uint64_t ret; 266*0Sstevel@tonic-gate 267*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 268*0Sstevel@tonic-gate dip, sysino); 269*0Sstevel@tonic-gate 270*0Sstevel@tonic-gate if ((ret = hvio_intr_gettarget(DIP_TO_HANDLE(dip), 271*0Sstevel@tonic-gate sysino, cpuid)) != H_EOK) { 272*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_gettarget failed, ret 0x%lx\n", 273*0Sstevel@tonic-gate ret); 274*0Sstevel@tonic-gate return (DDI_FAILURE); 275*0Sstevel@tonic-gate } 276*0Sstevel@tonic-gate 277*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 278*0Sstevel@tonic-gate 279*0Sstevel@tonic-gate return (DDI_SUCCESS); 280*0Sstevel@tonic-gate } 281*0Sstevel@tonic-gate 282*0Sstevel@tonic-gate /*ARGSUSED*/ 283*0Sstevel@tonic-gate int 284*0Sstevel@tonic-gate px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 285*0Sstevel@tonic-gate { 286*0Sstevel@tonic-gate uint64_t ret; 287*0Sstevel@tonic-gate 288*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 289*0Sstevel@tonic-gate "cpuid 0x%x\n", dip, sysino, cpuid); 290*0Sstevel@tonic-gate 291*0Sstevel@tonic-gate if ((ret = hvio_intr_settarget(DIP_TO_HANDLE(dip), 292*0Sstevel@tonic-gate sysino, cpuid)) != H_EOK) { 293*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "hvio_intr_settarget failed, ret 0x%lx\n", 294*0Sstevel@tonic-gate ret); 295*0Sstevel@tonic-gate return (DDI_FAILURE); 296*0Sstevel@tonic-gate } 297*0Sstevel@tonic-gate 298*0Sstevel@tonic-gate return (DDI_SUCCESS); 299*0Sstevel@tonic-gate } 300*0Sstevel@tonic-gate 301*0Sstevel@tonic-gate /*ARGSUSED*/ 302*0Sstevel@tonic-gate int 303*0Sstevel@tonic-gate px_lib_intr_reset(dev_info_t *dip) 304*0Sstevel@tonic-gate { 305*0Sstevel@tonic-gate devino_t ino; 306*0Sstevel@tonic-gate sysino_t sysino; 307*0Sstevel@tonic-gate 308*0Sstevel@tonic-gate DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 309*0Sstevel@tonic-gate 310*0Sstevel@tonic-gate /* Reset all Interrupts */ 311*0Sstevel@tonic-gate for (ino = 0; ino < INTERRUPT_MAPPING_ENTRIES; ino++) { 312*0Sstevel@tonic-gate if (px_lib_intr_devino_to_sysino(dip, ino, 313*0Sstevel@tonic-gate &sysino) != DDI_SUCCESS) 314*0Sstevel@tonic-gate return (BF_FATAL); 315*0Sstevel@tonic-gate 316*0Sstevel@tonic-gate if (px_lib_intr_setstate(dip, sysino, 317*0Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 318*0Sstevel@tonic-gate return (BF_FATAL); 319*0Sstevel@tonic-gate } 320*0Sstevel@tonic-gate 321*0Sstevel@tonic-gate return (BF_NONE); 322*0Sstevel@tonic-gate } 323*0Sstevel@tonic-gate 324*0Sstevel@tonic-gate /*ARGSUSED*/ 325*0Sstevel@tonic-gate int 326*0Sstevel@tonic-gate px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 327*0Sstevel@tonic-gate io_attributes_t io_attributes, void *addr, size_t pfn_index, 328*0Sstevel@tonic-gate int flag) 329*0Sstevel@tonic-gate { 330*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 331*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 332*0Sstevel@tonic-gate uint64_t ret; 333*0Sstevel@tonic-gate 334*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 335*0Sstevel@tonic-gate "pages 0x%x atrr 0x%x addr 0x%p pfn_index 0x%llx, flag 0x%x\n", 336*0Sstevel@tonic-gate dip, tsbid, pages, io_attributes, addr, pfn_index, flag); 337*0Sstevel@tonic-gate 338*0Sstevel@tonic-gate if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, 339*0Sstevel@tonic-gate io_attributes, addr, pfn_index, flag)) != H_EOK) { 340*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, 341*0Sstevel@tonic-gate "px_lib_iommu_map failed, ret 0x%lx\n", ret); 342*0Sstevel@tonic-gate return (DDI_FAILURE); 343*0Sstevel@tonic-gate } 344*0Sstevel@tonic-gate 345*0Sstevel@tonic-gate return (DDI_SUCCESS); 346*0Sstevel@tonic-gate } 347*0Sstevel@tonic-gate 348*0Sstevel@tonic-gate /*ARGSUSED*/ 349*0Sstevel@tonic-gate int 350*0Sstevel@tonic-gate px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 351*0Sstevel@tonic-gate { 352*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 353*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 354*0Sstevel@tonic-gate uint64_t ret; 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 357*0Sstevel@tonic-gate "pages 0x%x\n", dip, tsbid, pages); 358*0Sstevel@tonic-gate 359*0Sstevel@tonic-gate if ((ret = hvio_iommu_demap(px_p->px_dev_hdl, pxu_p, tsbid, pages)) 360*0Sstevel@tonic-gate != H_EOK) { 361*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, 362*0Sstevel@tonic-gate "px_lib_iommu_demap failed, ret 0x%lx\n", ret); 363*0Sstevel@tonic-gate 364*0Sstevel@tonic-gate return (DDI_FAILURE); 365*0Sstevel@tonic-gate } 366*0Sstevel@tonic-gate 367*0Sstevel@tonic-gate return (DDI_SUCCESS); 368*0Sstevel@tonic-gate } 369*0Sstevel@tonic-gate 370*0Sstevel@tonic-gate /*ARGSUSED*/ 371*0Sstevel@tonic-gate int 372*0Sstevel@tonic-gate px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, 373*0Sstevel@tonic-gate io_attributes_t *attributes_p, r_addr_t *r_addr_p) 374*0Sstevel@tonic-gate { 375*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 376*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 377*0Sstevel@tonic-gate uint64_t ret; 378*0Sstevel@tonic-gate 379*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 380*0Sstevel@tonic-gate dip, tsbid); 381*0Sstevel@tonic-gate 382*0Sstevel@tonic-gate if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, 383*0Sstevel@tonic-gate attributes_p, r_addr_p)) != H_EOK) { 384*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, 385*0Sstevel@tonic-gate "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 386*0Sstevel@tonic-gate 387*0Sstevel@tonic-gate return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 388*0Sstevel@tonic-gate } 389*0Sstevel@tonic-gate 390*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 391*0Sstevel@tonic-gate *attributes_p, *r_addr_p); 392*0Sstevel@tonic-gate 393*0Sstevel@tonic-gate return (DDI_SUCCESS); 394*0Sstevel@tonic-gate } 395*0Sstevel@tonic-gate 396*0Sstevel@tonic-gate 397*0Sstevel@tonic-gate /* 398*0Sstevel@tonic-gate * Checks dma attributes against system bypass ranges 399*0Sstevel@tonic-gate * The bypass range is determined by the hardware. Return them so the 400*0Sstevel@tonic-gate * common code can do generic checking against them. 401*0Sstevel@tonic-gate */ 402*0Sstevel@tonic-gate /*ARGSUSED*/ 403*0Sstevel@tonic-gate int 404*0Sstevel@tonic-gate px_lib_dma_bypass_rngchk(ddi_dma_attr_t *attrp, uint64_t *lo_p, uint64_t *hi_p) 405*0Sstevel@tonic-gate { 406*0Sstevel@tonic-gate *lo_p = MMU_BYPASS_BASE; 407*0Sstevel@tonic-gate *hi_p = MMU_BYPASS_END; 408*0Sstevel@tonic-gate 409*0Sstevel@tonic-gate return (DDI_SUCCESS); 410*0Sstevel@tonic-gate } 411*0Sstevel@tonic-gate 412*0Sstevel@tonic-gate 413*0Sstevel@tonic-gate /*ARGSUSED*/ 414*0Sstevel@tonic-gate int 415*0Sstevel@tonic-gate px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, 416*0Sstevel@tonic-gate io_attributes_t io_attributes, io_addr_t *io_addr_p) 417*0Sstevel@tonic-gate { 418*0Sstevel@tonic-gate uint64_t ret; 419*0Sstevel@tonic-gate 420*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 421*0Sstevel@tonic-gate "attr 0x%x\n", dip, ra, io_attributes); 422*0Sstevel@tonic-gate 423*0Sstevel@tonic-gate if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), ra, 424*0Sstevel@tonic-gate io_attributes, io_addr_p)) != H_EOK) { 425*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, 426*0Sstevel@tonic-gate "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 427*0Sstevel@tonic-gate return (DDI_FAILURE); 428*0Sstevel@tonic-gate } 429*0Sstevel@tonic-gate 430*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 431*0Sstevel@tonic-gate *io_addr_p); 432*0Sstevel@tonic-gate 433*0Sstevel@tonic-gate return (DDI_SUCCESS); 434*0Sstevel@tonic-gate } 435*0Sstevel@tonic-gate 436*0Sstevel@tonic-gate /* 437*0Sstevel@tonic-gate * bus dma sync entry point. 438*0Sstevel@tonic-gate */ 439*0Sstevel@tonic-gate /*ARGSUSED*/ 440*0Sstevel@tonic-gate int 441*0Sstevel@tonic-gate px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 442*0Sstevel@tonic-gate off_t off, size_t len, uint_t cache_flags) 443*0Sstevel@tonic-gate { 444*0Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 445*0Sstevel@tonic-gate 446*0Sstevel@tonic-gate DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 447*0Sstevel@tonic-gate "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 448*0Sstevel@tonic-gate dip, rdip, handle, off, len, cache_flags); 449*0Sstevel@tonic-gate 450*0Sstevel@tonic-gate /* 451*0Sstevel@tonic-gate * jbus_stst_order is found only in certain cpu modules. 452*0Sstevel@tonic-gate * Just return success if not present. 453*0Sstevel@tonic-gate */ 454*0Sstevel@tonic-gate if (&jbus_stst_order == NULL) 455*0Sstevel@tonic-gate return (DDI_SUCCESS); 456*0Sstevel@tonic-gate 457*0Sstevel@tonic-gate if (!(mp->dmai_flags & DMAI_FLAGS_INUSE)) { 458*0Sstevel@tonic-gate cmn_err(CE_WARN, "Unbound dma handle %p from %s%d", (void *)mp, 459*0Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip)); 460*0Sstevel@tonic-gate return (DDI_FAILURE); 461*0Sstevel@tonic-gate } 462*0Sstevel@tonic-gate 463*0Sstevel@tonic-gate if (mp->dmai_flags & DMAI_FLAGS_NOSYNC) 464*0Sstevel@tonic-gate return (DDI_SUCCESS); 465*0Sstevel@tonic-gate 466*0Sstevel@tonic-gate /* 467*0Sstevel@tonic-gate * No flush needed when sending data from memory to device. 468*0Sstevel@tonic-gate * Nothing to do to "sync" memory to what device would already see. 469*0Sstevel@tonic-gate */ 470*0Sstevel@tonic-gate if (!(mp->dmai_rflags & DDI_DMA_READ) || 471*0Sstevel@tonic-gate ((cache_flags & PX_DMA_SYNC_DDI_FLAGS) == DDI_DMA_SYNC_FORDEV)) 472*0Sstevel@tonic-gate return (DDI_SUCCESS); 473*0Sstevel@tonic-gate 474*0Sstevel@tonic-gate /* 475*0Sstevel@tonic-gate * Perform necessary cpu workaround to ensure jbus ordering. 476*0Sstevel@tonic-gate * CPU's internal "invalidate FIFOs" are flushed. 477*0Sstevel@tonic-gate */ 478*0Sstevel@tonic-gate 479*0Sstevel@tonic-gate #if !defined(lint) 480*0Sstevel@tonic-gate kpreempt_disable(); 481*0Sstevel@tonic-gate #endif 482*0Sstevel@tonic-gate jbus_stst_order(); 483*0Sstevel@tonic-gate #if !defined(lint) 484*0Sstevel@tonic-gate kpreempt_enable(); 485*0Sstevel@tonic-gate #endif 486*0Sstevel@tonic-gate return (DDI_SUCCESS); 487*0Sstevel@tonic-gate } 488*0Sstevel@tonic-gate 489*0Sstevel@tonic-gate /* 490*0Sstevel@tonic-gate * MSIQ Functions: 491*0Sstevel@tonic-gate */ 492*0Sstevel@tonic-gate /*ARGSUSED*/ 493*0Sstevel@tonic-gate int 494*0Sstevel@tonic-gate px_lib_msiq_init(dev_info_t *dip) 495*0Sstevel@tonic-gate { 496*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 497*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 498*0Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 499*0Sstevel@tonic-gate caddr_t msiq_addr; 500*0Sstevel@tonic-gate px_dvma_addr_t pg_index; 501*0Sstevel@tonic-gate size_t size; 502*0Sstevel@tonic-gate int ret; 503*0Sstevel@tonic-gate 504*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 505*0Sstevel@tonic-gate 506*0Sstevel@tonic-gate /* 507*0Sstevel@tonic-gate * Map the EQ memory into the Fire MMU (has to be 512KB aligned) 508*0Sstevel@tonic-gate * and then initialize the base address register. 509*0Sstevel@tonic-gate * 510*0Sstevel@tonic-gate * Allocate entries from Fire IOMMU so that the resulting address 511*0Sstevel@tonic-gate * is properly aligned. Calculate the index of the first allocated 512*0Sstevel@tonic-gate * entry. Note: The size of the mapping is assumed to be a multiple 513*0Sstevel@tonic-gate * of the page size. 514*0Sstevel@tonic-gate */ 515*0Sstevel@tonic-gate msiq_addr = (caddr_t)(((uint64_t)msiq_state_p->msiq_buf_p + 516*0Sstevel@tonic-gate (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 517*0Sstevel@tonic-gate 518*0Sstevel@tonic-gate size = msiq_state_p->msiq_cnt * 519*0Sstevel@tonic-gate msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 520*0Sstevel@tonic-gate 521*0Sstevel@tonic-gate pxu_p->msiq_mapped_p = vmem_xalloc(px_p->px_mmu_p->mmu_dvma_map, 522*0Sstevel@tonic-gate size, (512 * 1024), 0, 0, NULL, NULL, VM_NOSLEEP | VM_BESTFIT); 523*0Sstevel@tonic-gate 524*0Sstevel@tonic-gate if (pxu_p->msiq_mapped_p == NULL) 525*0Sstevel@tonic-gate return (DDI_FAILURE); 526*0Sstevel@tonic-gate 527*0Sstevel@tonic-gate pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 528*0Sstevel@tonic-gate MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 529*0Sstevel@tonic-gate 530*0Sstevel@tonic-gate if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), 531*0Sstevel@tonic-gate MMU_BTOP(size), PCI_MAP_ATTR_WRITE, (void *)msiq_addr, 0, 532*0Sstevel@tonic-gate MMU_MAP_BUF)) != DDI_SUCCESS) { 533*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 534*0Sstevel@tonic-gate "hvio_msiq_init failed, ret 0x%lx\n", ret); 535*0Sstevel@tonic-gate 536*0Sstevel@tonic-gate (void) px_lib_msiq_fini(dip); 537*0Sstevel@tonic-gate return (DDI_FAILURE); 538*0Sstevel@tonic-gate } 539*0Sstevel@tonic-gate 540*0Sstevel@tonic-gate (void) hvio_msiq_init(DIP_TO_HANDLE(dip), pxu_p); 541*0Sstevel@tonic-gate 542*0Sstevel@tonic-gate return (DDI_SUCCESS); 543*0Sstevel@tonic-gate } 544*0Sstevel@tonic-gate 545*0Sstevel@tonic-gate /*ARGSUSED*/ 546*0Sstevel@tonic-gate int 547*0Sstevel@tonic-gate px_lib_msiq_fini(dev_info_t *dip) 548*0Sstevel@tonic-gate { 549*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 550*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 551*0Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 552*0Sstevel@tonic-gate px_dvma_addr_t pg_index; 553*0Sstevel@tonic-gate size_t size; 554*0Sstevel@tonic-gate 555*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 556*0Sstevel@tonic-gate 557*0Sstevel@tonic-gate /* 558*0Sstevel@tonic-gate * Unmap and free the EQ memory that had been mapped 559*0Sstevel@tonic-gate * into the Fire IOMMU. 560*0Sstevel@tonic-gate */ 561*0Sstevel@tonic-gate size = msiq_state_p->msiq_cnt * 562*0Sstevel@tonic-gate msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 563*0Sstevel@tonic-gate 564*0Sstevel@tonic-gate pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 565*0Sstevel@tonic-gate MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 566*0Sstevel@tonic-gate 567*0Sstevel@tonic-gate (void) px_lib_iommu_demap(px_p->px_dip, 568*0Sstevel@tonic-gate PCI_TSBID(0, pg_index), MMU_BTOP(size)); 569*0Sstevel@tonic-gate 570*0Sstevel@tonic-gate /* Free the entries from the Fire MMU */ 571*0Sstevel@tonic-gate vmem_xfree(px_p->px_mmu_p->mmu_dvma_map, 572*0Sstevel@tonic-gate (void *)pxu_p->msiq_mapped_p, size); 573*0Sstevel@tonic-gate 574*0Sstevel@tonic-gate return (DDI_SUCCESS); 575*0Sstevel@tonic-gate } 576*0Sstevel@tonic-gate 577*0Sstevel@tonic-gate /*ARGSUSED*/ 578*0Sstevel@tonic-gate int 579*0Sstevel@tonic-gate px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 580*0Sstevel@tonic-gate uint_t *msiq_rec_cnt_p) 581*0Sstevel@tonic-gate { 582*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 583*0Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 584*0Sstevel@tonic-gate uint64_t *msiq_addr; 585*0Sstevel@tonic-gate size_t msiq_size; 586*0Sstevel@tonic-gate 587*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 588*0Sstevel@tonic-gate dip, msiq_id); 589*0Sstevel@tonic-gate 590*0Sstevel@tonic-gate msiq_addr = (uint64_t *)(((uint64_t)msiq_state_p->msiq_buf_p + 591*0Sstevel@tonic-gate (MMU_PAGE_SIZE - 1)) >> MMU_PAGE_SHIFT << MMU_PAGE_SHIFT); 592*0Sstevel@tonic-gate msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 593*0Sstevel@tonic-gate ra_p = (r_addr_t *)((caddr_t)msiq_addr + (msiq_id * msiq_size)); 594*0Sstevel@tonic-gate 595*0Sstevel@tonic-gate *msiq_rec_cnt_p = msiq_state_p->msiq_rec_cnt; 596*0Sstevel@tonic-gate 597*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 598*0Sstevel@tonic-gate ra_p, *msiq_rec_cnt_p); 599*0Sstevel@tonic-gate 600*0Sstevel@tonic-gate return (DDI_SUCCESS); 601*0Sstevel@tonic-gate } 602*0Sstevel@tonic-gate 603*0Sstevel@tonic-gate /*ARGSUSED*/ 604*0Sstevel@tonic-gate int 605*0Sstevel@tonic-gate px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 606*0Sstevel@tonic-gate pci_msiq_valid_state_t *msiq_valid_state) 607*0Sstevel@tonic-gate { 608*0Sstevel@tonic-gate uint64_t ret; 609*0Sstevel@tonic-gate 610*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 611*0Sstevel@tonic-gate dip, msiq_id); 612*0Sstevel@tonic-gate 613*0Sstevel@tonic-gate if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 614*0Sstevel@tonic-gate msiq_id, msiq_valid_state)) != H_EOK) { 615*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 616*0Sstevel@tonic-gate "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 617*0Sstevel@tonic-gate return (DDI_FAILURE); 618*0Sstevel@tonic-gate } 619*0Sstevel@tonic-gate 620*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 621*0Sstevel@tonic-gate *msiq_valid_state); 622*0Sstevel@tonic-gate 623*0Sstevel@tonic-gate return (DDI_SUCCESS); 624*0Sstevel@tonic-gate } 625*0Sstevel@tonic-gate 626*0Sstevel@tonic-gate /*ARGSUSED*/ 627*0Sstevel@tonic-gate int 628*0Sstevel@tonic-gate px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 629*0Sstevel@tonic-gate pci_msiq_valid_state_t msiq_valid_state) 630*0Sstevel@tonic-gate { 631*0Sstevel@tonic-gate uint64_t ret; 632*0Sstevel@tonic-gate 633*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 634*0Sstevel@tonic-gate "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 635*0Sstevel@tonic-gate 636*0Sstevel@tonic-gate if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 637*0Sstevel@tonic-gate msiq_id, msiq_valid_state)) != H_EOK) { 638*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 639*0Sstevel@tonic-gate "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 640*0Sstevel@tonic-gate return (DDI_FAILURE); 641*0Sstevel@tonic-gate } 642*0Sstevel@tonic-gate 643*0Sstevel@tonic-gate return (DDI_SUCCESS); 644*0Sstevel@tonic-gate } 645*0Sstevel@tonic-gate 646*0Sstevel@tonic-gate /*ARGSUSED*/ 647*0Sstevel@tonic-gate int 648*0Sstevel@tonic-gate px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 649*0Sstevel@tonic-gate pci_msiq_state_t *msiq_state) 650*0Sstevel@tonic-gate { 651*0Sstevel@tonic-gate uint64_t ret; 652*0Sstevel@tonic-gate 653*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 654*0Sstevel@tonic-gate dip, msiq_id); 655*0Sstevel@tonic-gate 656*0Sstevel@tonic-gate if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 657*0Sstevel@tonic-gate msiq_id, msiq_state)) != H_EOK) { 658*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 659*0Sstevel@tonic-gate "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 660*0Sstevel@tonic-gate return (DDI_FAILURE); 661*0Sstevel@tonic-gate } 662*0Sstevel@tonic-gate 663*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 664*0Sstevel@tonic-gate *msiq_state); 665*0Sstevel@tonic-gate 666*0Sstevel@tonic-gate return (DDI_SUCCESS); 667*0Sstevel@tonic-gate } 668*0Sstevel@tonic-gate 669*0Sstevel@tonic-gate /*ARGSUSED*/ 670*0Sstevel@tonic-gate int 671*0Sstevel@tonic-gate px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 672*0Sstevel@tonic-gate pci_msiq_state_t msiq_state) 673*0Sstevel@tonic-gate { 674*0Sstevel@tonic-gate uint64_t ret; 675*0Sstevel@tonic-gate 676*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 677*0Sstevel@tonic-gate "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 678*0Sstevel@tonic-gate 679*0Sstevel@tonic-gate if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 680*0Sstevel@tonic-gate msiq_id, msiq_state)) != H_EOK) { 681*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 682*0Sstevel@tonic-gate "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 683*0Sstevel@tonic-gate return (DDI_FAILURE); 684*0Sstevel@tonic-gate } 685*0Sstevel@tonic-gate 686*0Sstevel@tonic-gate return (DDI_SUCCESS); 687*0Sstevel@tonic-gate } 688*0Sstevel@tonic-gate 689*0Sstevel@tonic-gate /*ARGSUSED*/ 690*0Sstevel@tonic-gate int 691*0Sstevel@tonic-gate px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 692*0Sstevel@tonic-gate msiqhead_t *msiq_head) 693*0Sstevel@tonic-gate { 694*0Sstevel@tonic-gate uint64_t ret; 695*0Sstevel@tonic-gate 696*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 697*0Sstevel@tonic-gate dip, msiq_id); 698*0Sstevel@tonic-gate 699*0Sstevel@tonic-gate if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 700*0Sstevel@tonic-gate msiq_id, msiq_head)) != H_EOK) { 701*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 702*0Sstevel@tonic-gate "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 703*0Sstevel@tonic-gate return (DDI_FAILURE); 704*0Sstevel@tonic-gate } 705*0Sstevel@tonic-gate 706*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: msiq_head 0x%x\n", 707*0Sstevel@tonic-gate *msiq_head); 708*0Sstevel@tonic-gate 709*0Sstevel@tonic-gate return (DDI_SUCCESS); 710*0Sstevel@tonic-gate } 711*0Sstevel@tonic-gate 712*0Sstevel@tonic-gate /*ARGSUSED*/ 713*0Sstevel@tonic-gate int 714*0Sstevel@tonic-gate px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 715*0Sstevel@tonic-gate msiqhead_t msiq_head) 716*0Sstevel@tonic-gate { 717*0Sstevel@tonic-gate uint64_t ret; 718*0Sstevel@tonic-gate 719*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 720*0Sstevel@tonic-gate "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 721*0Sstevel@tonic-gate 722*0Sstevel@tonic-gate if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 723*0Sstevel@tonic-gate msiq_id, msiq_head)) != H_EOK) { 724*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 725*0Sstevel@tonic-gate "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 726*0Sstevel@tonic-gate return (DDI_FAILURE); 727*0Sstevel@tonic-gate } 728*0Sstevel@tonic-gate 729*0Sstevel@tonic-gate return (DDI_SUCCESS); 730*0Sstevel@tonic-gate } 731*0Sstevel@tonic-gate 732*0Sstevel@tonic-gate /*ARGSUSED*/ 733*0Sstevel@tonic-gate int 734*0Sstevel@tonic-gate px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 735*0Sstevel@tonic-gate msiqtail_t *msiq_tail) 736*0Sstevel@tonic-gate { 737*0Sstevel@tonic-gate uint64_t ret; 738*0Sstevel@tonic-gate 739*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 740*0Sstevel@tonic-gate dip, msiq_id); 741*0Sstevel@tonic-gate 742*0Sstevel@tonic-gate if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 743*0Sstevel@tonic-gate msiq_id, msiq_tail)) != H_EOK) { 744*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, 745*0Sstevel@tonic-gate "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 746*0Sstevel@tonic-gate return (DDI_FAILURE); 747*0Sstevel@tonic-gate } 748*0Sstevel@tonic-gate 749*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 750*0Sstevel@tonic-gate *msiq_tail); 751*0Sstevel@tonic-gate 752*0Sstevel@tonic-gate return (DDI_SUCCESS); 753*0Sstevel@tonic-gate } 754*0Sstevel@tonic-gate 755*0Sstevel@tonic-gate /*ARGSUSED*/ 756*0Sstevel@tonic-gate void 757*0Sstevel@tonic-gate px_lib_get_msiq_rec(dev_info_t *dip, px_msiq_t *msiq_p, msiq_rec_t *msiq_rec_p) 758*0Sstevel@tonic-gate { 759*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 760*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 761*0Sstevel@tonic-gate eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_p->msiq_curr; 762*0Sstevel@tonic-gate 763*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 764*0Sstevel@tonic-gate dip, eq_rec_p); 765*0Sstevel@tonic-gate 766*0Sstevel@tonic-gate if (!eq_rec_p->eq_rec_rid) { 767*0Sstevel@tonic-gate /* Set msiq_rec_rid to zero */ 768*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_rid = 0; 769*0Sstevel@tonic-gate 770*0Sstevel@tonic-gate return; 771*0Sstevel@tonic-gate } 772*0Sstevel@tonic-gate 773*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: EQ RECORD, " 774*0Sstevel@tonic-gate "eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx " 775*0Sstevel@tonic-gate "eq_rec_len 0x%llx eq_rec_addr0 0x%llx " 776*0Sstevel@tonic-gate "eq_rec_addr1 0x%llx eq_rec_data0 0x%llx " 777*0Sstevel@tonic-gate "eq_rec_data1 0x%llx\n", eq_rec_p->eq_rec_rid, 778*0Sstevel@tonic-gate eq_rec_p->eq_rec_fmt_type, eq_rec_p->eq_rec_len, 779*0Sstevel@tonic-gate eq_rec_p->eq_rec_addr0, eq_rec_p->eq_rec_addr1, 780*0Sstevel@tonic-gate eq_rec_p->eq_rec_data0, eq_rec_p->eq_rec_data1); 781*0Sstevel@tonic-gate 782*0Sstevel@tonic-gate /* 783*0Sstevel@tonic-gate * Only upper 4 bits of eq_rec_fmt_type is used 784*0Sstevel@tonic-gate * to identify the EQ record type. 785*0Sstevel@tonic-gate */ 786*0Sstevel@tonic-gate switch (eq_rec_p->eq_rec_fmt_type >> 3) { 787*0Sstevel@tonic-gate case EQ_REC_MSI32: 788*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_type = MSI32_REC; 789*0Sstevel@tonic-gate 790*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 791*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msi.msi_data = 792*0Sstevel@tonic-gate (eq_rec_p->eq_rec_data0 & 0xFF) << 8 | 793*0Sstevel@tonic-gate (eq_rec_p->eq_rec_data0 & 0xFF00) >> 8; 794*0Sstevel@tonic-gate } else { 795*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 796*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msi.msi_data = 797*0Sstevel@tonic-gate eq_rec_p->eq_rec_data0; 798*0Sstevel@tonic-gate } 799*0Sstevel@tonic-gate 800*0Sstevel@tonic-gate break; 801*0Sstevel@tonic-gate case EQ_REC_MSI64: 802*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_type = MSI64_REC; 803*0Sstevel@tonic-gate 804*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 805*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msi.msi_data = 806*0Sstevel@tonic-gate (eq_rec_p->eq_rec_data0 & 0xFF) << 8 | 807*0Sstevel@tonic-gate (eq_rec_p->eq_rec_data0 & 0xFF00) >> 8; 808*0Sstevel@tonic-gate } else { 809*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 810*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msi.msi_data = 811*0Sstevel@tonic-gate eq_rec_p->eq_rec_data0; 812*0Sstevel@tonic-gate } 813*0Sstevel@tonic-gate 814*0Sstevel@tonic-gate break; 815*0Sstevel@tonic-gate case EQ_REC_MSG: 816*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_type = MSG_REC; 817*0Sstevel@tonic-gate 818*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msg.msg_route = 819*0Sstevel@tonic-gate eq_rec_p->eq_rec_fmt_type & 7; 820*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msg.msg_targ = eq_rec_p->eq_rec_rid; 821*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_data.msg.msg_code = eq_rec_p->eq_rec_data0; 822*0Sstevel@tonic-gate break; 823*0Sstevel@tonic-gate default: 824*0Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_lib_get_msiq_rec: " 825*0Sstevel@tonic-gate "0x%lx is an unknown EQ record type", 826*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 827*0Sstevel@tonic-gate eq_rec_p->eq_rec_fmt_type); 828*0Sstevel@tonic-gate break; 829*0Sstevel@tonic-gate } 830*0Sstevel@tonic-gate 831*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_rid = eq_rec_p->eq_rec_rid; 832*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_msi_addr = ((eq_rec_p->eq_rec_addr1 << 16) | 833*0Sstevel@tonic-gate (eq_rec_p->eq_rec_addr0 << 2)); 834*0Sstevel@tonic-gate 835*0Sstevel@tonic-gate /* Zero out eq_rec_rid field */ 836*0Sstevel@tonic-gate eq_rec_p->eq_rec_rid = 0; 837*0Sstevel@tonic-gate } 838*0Sstevel@tonic-gate 839*0Sstevel@tonic-gate /* 840*0Sstevel@tonic-gate * MSI Functions: 841*0Sstevel@tonic-gate */ 842*0Sstevel@tonic-gate /*ARGSUSED*/ 843*0Sstevel@tonic-gate int 844*0Sstevel@tonic-gate px_lib_msi_init(dev_info_t *dip) 845*0Sstevel@tonic-gate { 846*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 847*0Sstevel@tonic-gate px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 848*0Sstevel@tonic-gate uint64_t ret; 849*0Sstevel@tonic-gate 850*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 851*0Sstevel@tonic-gate 852*0Sstevel@tonic-gate if ((ret = hvio_msi_init(DIP_TO_HANDLE(dip), 853*0Sstevel@tonic-gate msi_state_p->msi_addr32, msi_state_p->msi_addr64)) != H_EOK) { 854*0Sstevel@tonic-gate DBG(DBG_LIB_MSIQ, dip, "px_lib_msi_init failed, ret 0x%lx\n", 855*0Sstevel@tonic-gate ret); 856*0Sstevel@tonic-gate return (DDI_FAILURE); 857*0Sstevel@tonic-gate } 858*0Sstevel@tonic-gate 859*0Sstevel@tonic-gate return (DDI_SUCCESS); 860*0Sstevel@tonic-gate } 861*0Sstevel@tonic-gate 862*0Sstevel@tonic-gate /*ARGSUSED*/ 863*0Sstevel@tonic-gate int 864*0Sstevel@tonic-gate px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 865*0Sstevel@tonic-gate msiqid_t *msiq_id) 866*0Sstevel@tonic-gate { 867*0Sstevel@tonic-gate uint64_t ret; 868*0Sstevel@tonic-gate 869*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 870*0Sstevel@tonic-gate dip, msi_num); 871*0Sstevel@tonic-gate 872*0Sstevel@tonic-gate if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 873*0Sstevel@tonic-gate msi_num, msiq_id)) != H_EOK) { 874*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 875*0Sstevel@tonic-gate "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 876*0Sstevel@tonic-gate return (DDI_FAILURE); 877*0Sstevel@tonic-gate } 878*0Sstevel@tonic-gate 879*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 880*0Sstevel@tonic-gate *msiq_id); 881*0Sstevel@tonic-gate 882*0Sstevel@tonic-gate return (DDI_SUCCESS); 883*0Sstevel@tonic-gate } 884*0Sstevel@tonic-gate 885*0Sstevel@tonic-gate /*ARGSUSED*/ 886*0Sstevel@tonic-gate int 887*0Sstevel@tonic-gate px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 888*0Sstevel@tonic-gate msiqid_t msiq_id, msi_type_t msitype) 889*0Sstevel@tonic-gate { 890*0Sstevel@tonic-gate uint64_t ret; 891*0Sstevel@tonic-gate 892*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 893*0Sstevel@tonic-gate "msq_id 0x%x\n", dip, msi_num, msiq_id); 894*0Sstevel@tonic-gate 895*0Sstevel@tonic-gate if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 896*0Sstevel@tonic-gate msi_num, msiq_id)) != H_EOK) { 897*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 898*0Sstevel@tonic-gate "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 899*0Sstevel@tonic-gate return (DDI_FAILURE); 900*0Sstevel@tonic-gate } 901*0Sstevel@tonic-gate 902*0Sstevel@tonic-gate return (DDI_SUCCESS); 903*0Sstevel@tonic-gate } 904*0Sstevel@tonic-gate 905*0Sstevel@tonic-gate /*ARGSUSED*/ 906*0Sstevel@tonic-gate int 907*0Sstevel@tonic-gate px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 908*0Sstevel@tonic-gate pci_msi_valid_state_t *msi_valid_state) 909*0Sstevel@tonic-gate { 910*0Sstevel@tonic-gate uint64_t ret; 911*0Sstevel@tonic-gate 912*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 913*0Sstevel@tonic-gate dip, msi_num); 914*0Sstevel@tonic-gate 915*0Sstevel@tonic-gate if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 916*0Sstevel@tonic-gate msi_num, msi_valid_state)) != H_EOK) { 917*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 918*0Sstevel@tonic-gate "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 919*0Sstevel@tonic-gate return (DDI_FAILURE); 920*0Sstevel@tonic-gate } 921*0Sstevel@tonic-gate 922*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 923*0Sstevel@tonic-gate *msi_valid_state); 924*0Sstevel@tonic-gate 925*0Sstevel@tonic-gate return (DDI_SUCCESS); 926*0Sstevel@tonic-gate } 927*0Sstevel@tonic-gate 928*0Sstevel@tonic-gate /*ARGSUSED*/ 929*0Sstevel@tonic-gate int 930*0Sstevel@tonic-gate px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 931*0Sstevel@tonic-gate pci_msi_valid_state_t msi_valid_state) 932*0Sstevel@tonic-gate { 933*0Sstevel@tonic-gate uint64_t ret; 934*0Sstevel@tonic-gate 935*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 936*0Sstevel@tonic-gate "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 937*0Sstevel@tonic-gate 938*0Sstevel@tonic-gate if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 939*0Sstevel@tonic-gate msi_num, msi_valid_state)) != H_EOK) { 940*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 941*0Sstevel@tonic-gate "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 942*0Sstevel@tonic-gate return (DDI_FAILURE); 943*0Sstevel@tonic-gate } 944*0Sstevel@tonic-gate 945*0Sstevel@tonic-gate return (DDI_SUCCESS); 946*0Sstevel@tonic-gate } 947*0Sstevel@tonic-gate 948*0Sstevel@tonic-gate /*ARGSUSED*/ 949*0Sstevel@tonic-gate int 950*0Sstevel@tonic-gate px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 951*0Sstevel@tonic-gate pci_msi_state_t *msi_state) 952*0Sstevel@tonic-gate { 953*0Sstevel@tonic-gate uint64_t ret; 954*0Sstevel@tonic-gate 955*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 956*0Sstevel@tonic-gate dip, msi_num); 957*0Sstevel@tonic-gate 958*0Sstevel@tonic-gate if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 959*0Sstevel@tonic-gate msi_num, msi_state)) != H_EOK) { 960*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 961*0Sstevel@tonic-gate "hvio_msi_getstate failed, ret 0x%lx\n", ret); 962*0Sstevel@tonic-gate return (DDI_FAILURE); 963*0Sstevel@tonic-gate } 964*0Sstevel@tonic-gate 965*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 966*0Sstevel@tonic-gate *msi_state); 967*0Sstevel@tonic-gate 968*0Sstevel@tonic-gate return (DDI_SUCCESS); 969*0Sstevel@tonic-gate } 970*0Sstevel@tonic-gate 971*0Sstevel@tonic-gate /*ARGSUSED*/ 972*0Sstevel@tonic-gate int 973*0Sstevel@tonic-gate px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 974*0Sstevel@tonic-gate pci_msi_state_t msi_state) 975*0Sstevel@tonic-gate { 976*0Sstevel@tonic-gate uint64_t ret; 977*0Sstevel@tonic-gate 978*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 979*0Sstevel@tonic-gate "msi_state 0x%x\n", dip, msi_num, msi_state); 980*0Sstevel@tonic-gate 981*0Sstevel@tonic-gate if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 982*0Sstevel@tonic-gate msi_num, msi_state)) != H_EOK) { 983*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, 984*0Sstevel@tonic-gate "hvio_msi_setstate failed, ret 0x%lx\n", ret); 985*0Sstevel@tonic-gate return (DDI_FAILURE); 986*0Sstevel@tonic-gate } 987*0Sstevel@tonic-gate 988*0Sstevel@tonic-gate return (DDI_SUCCESS); 989*0Sstevel@tonic-gate } 990*0Sstevel@tonic-gate 991*0Sstevel@tonic-gate /* 992*0Sstevel@tonic-gate * MSG Functions: 993*0Sstevel@tonic-gate */ 994*0Sstevel@tonic-gate /*ARGSUSED*/ 995*0Sstevel@tonic-gate int 996*0Sstevel@tonic-gate px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 997*0Sstevel@tonic-gate msiqid_t *msiq_id) 998*0Sstevel@tonic-gate { 999*0Sstevel@tonic-gate uint64_t ret; 1000*0Sstevel@tonic-gate 1001*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1002*0Sstevel@tonic-gate dip, msg_type); 1003*0Sstevel@tonic-gate 1004*0Sstevel@tonic-gate if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1005*0Sstevel@tonic-gate msg_type, msiq_id)) != H_EOK) { 1006*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, 1007*0Sstevel@tonic-gate "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1008*0Sstevel@tonic-gate return (DDI_FAILURE); 1009*0Sstevel@tonic-gate } 1010*0Sstevel@tonic-gate 1011*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1012*0Sstevel@tonic-gate *msiq_id); 1013*0Sstevel@tonic-gate 1014*0Sstevel@tonic-gate return (DDI_SUCCESS); 1015*0Sstevel@tonic-gate } 1016*0Sstevel@tonic-gate 1017*0Sstevel@tonic-gate /*ARGSUSED*/ 1018*0Sstevel@tonic-gate int 1019*0Sstevel@tonic-gate px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1020*0Sstevel@tonic-gate msiqid_t msiq_id) 1021*0Sstevel@tonic-gate { 1022*0Sstevel@tonic-gate uint64_t ret; 1023*0Sstevel@tonic-gate 1024*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, "px_lib_msi_setstate: dip 0x%p msg_type 0x%x " 1025*0Sstevel@tonic-gate "msiq_id 0x%x\n", dip, msg_type, msiq_id); 1026*0Sstevel@tonic-gate 1027*0Sstevel@tonic-gate if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1028*0Sstevel@tonic-gate msg_type, msiq_id)) != H_EOK) { 1029*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, 1030*0Sstevel@tonic-gate "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1031*0Sstevel@tonic-gate return (DDI_FAILURE); 1032*0Sstevel@tonic-gate } 1033*0Sstevel@tonic-gate 1034*0Sstevel@tonic-gate return (DDI_SUCCESS); 1035*0Sstevel@tonic-gate } 1036*0Sstevel@tonic-gate 1037*0Sstevel@tonic-gate /*ARGSUSED*/ 1038*0Sstevel@tonic-gate int 1039*0Sstevel@tonic-gate px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1040*0Sstevel@tonic-gate pcie_msg_valid_state_t *msg_valid_state) 1041*0Sstevel@tonic-gate { 1042*0Sstevel@tonic-gate uint64_t ret; 1043*0Sstevel@tonic-gate 1044*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1045*0Sstevel@tonic-gate dip, msg_type); 1046*0Sstevel@tonic-gate 1047*0Sstevel@tonic-gate if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1048*0Sstevel@tonic-gate msg_valid_state)) != H_EOK) { 1049*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, 1050*0Sstevel@tonic-gate "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1051*0Sstevel@tonic-gate return (DDI_FAILURE); 1052*0Sstevel@tonic-gate } 1053*0Sstevel@tonic-gate 1054*0Sstevel@tonic-gate DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1055*0Sstevel@tonic-gate *msg_valid_state); 1056*0Sstevel@tonic-gate 1057*0Sstevel@tonic-gate return (DDI_SUCCESS); 1058*0Sstevel@tonic-gate } 1059*0Sstevel@tonic-gate 1060*0Sstevel@tonic-gate /*ARGSUSED*/ 1061*0Sstevel@tonic-gate int 1062*0Sstevel@tonic-gate px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1063*0Sstevel@tonic-gate pcie_msg_valid_state_t msg_valid_state) 1064*0Sstevel@tonic-gate { 1065*0Sstevel@tonic-gate uint64_t ret; 1066*0Sstevel@tonic-gate 1067*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1068*0Sstevel@tonic-gate "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1069*0Sstevel@tonic-gate 1070*0Sstevel@tonic-gate if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1071*0Sstevel@tonic-gate msg_valid_state)) != H_EOK) { 1072*0Sstevel@tonic-gate DBG(DBG_LIB_MSG, dip, 1073*0Sstevel@tonic-gate "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1074*0Sstevel@tonic-gate return (DDI_FAILURE); 1075*0Sstevel@tonic-gate } 1076*0Sstevel@tonic-gate 1077*0Sstevel@tonic-gate return (DDI_SUCCESS); 1078*0Sstevel@tonic-gate } 1079*0Sstevel@tonic-gate 1080*0Sstevel@tonic-gate /* 1081*0Sstevel@tonic-gate * Suspend/Resume Functions: 1082*0Sstevel@tonic-gate * Currently unsupported by hypervisor 1083*0Sstevel@tonic-gate */ 1084*0Sstevel@tonic-gate int 1085*0Sstevel@tonic-gate px_lib_suspend(dev_info_t *dip) 1086*0Sstevel@tonic-gate { 1087*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1088*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1089*0Sstevel@tonic-gate devhandle_t dev_hdl, xbus_dev_hdl; 1090*0Sstevel@tonic-gate uint64_t ret; 1091*0Sstevel@tonic-gate 1092*0Sstevel@tonic-gate DBG(DBG_DETACH, dip, "px_lib_suspend: dip 0x%p\n", dip); 1093*0Sstevel@tonic-gate 1094*0Sstevel@tonic-gate dev_hdl = (devhandle_t)px_p->px_address[PX_REG_CSR]; 1095*0Sstevel@tonic-gate xbus_dev_hdl = (devhandle_t)px_p->px_address[PX_REG_XBC]; 1096*0Sstevel@tonic-gate 1097*0Sstevel@tonic-gate if ((ret = hvio_suspend(dev_hdl, pxu_p)) == H_EOK) { 1098*0Sstevel@tonic-gate px_p->px_cb_p->xbc_attachcnt--; 1099*0Sstevel@tonic-gate if (px_p->px_cb_p->xbc_attachcnt == 0) 1100*0Sstevel@tonic-gate if ((ret = hvio_cb_suspend(xbus_dev_hdl, pxu_p)) 1101*0Sstevel@tonic-gate != H_EOK) 1102*0Sstevel@tonic-gate px_p->px_cb_p->xbc_attachcnt++; 1103*0Sstevel@tonic-gate } 1104*0Sstevel@tonic-gate 1105*0Sstevel@tonic-gate return ((ret != H_EOK) ? DDI_FAILURE: DDI_SUCCESS); 1106*0Sstevel@tonic-gate } 1107*0Sstevel@tonic-gate 1108*0Sstevel@tonic-gate void 1109*0Sstevel@tonic-gate px_lib_resume(dev_info_t *dip) 1110*0Sstevel@tonic-gate { 1111*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1112*0Sstevel@tonic-gate pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1113*0Sstevel@tonic-gate devhandle_t dev_hdl, xbus_dev_hdl; 1114*0Sstevel@tonic-gate devino_t pec_ino = px_p->px_inos[PX_INTR_PEC]; 1115*0Sstevel@tonic-gate devino_t xbc_ino = px_p->px_inos[PX_INTR_XBC]; 1116*0Sstevel@tonic-gate 1117*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 1118*0Sstevel@tonic-gate 1119*0Sstevel@tonic-gate dev_hdl = (devhandle_t)px_p->px_address[PX_REG_CSR]; 1120*0Sstevel@tonic-gate xbus_dev_hdl = (devhandle_t)px_p->px_address[PX_REG_XBC]; 1121*0Sstevel@tonic-gate 1122*0Sstevel@tonic-gate px_p->px_cb_p->xbc_attachcnt++; 1123*0Sstevel@tonic-gate if (px_p->px_cb_p->xbc_attachcnt == 1) 1124*0Sstevel@tonic-gate hvio_cb_resume(dev_hdl, xbus_dev_hdl, xbc_ino, pxu_p); 1125*0Sstevel@tonic-gate hvio_resume(dev_hdl, pec_ino, pxu_p); 1126*0Sstevel@tonic-gate } 1127*0Sstevel@tonic-gate 1128*0Sstevel@tonic-gate /* 1129*0Sstevel@tonic-gate * PCI tool Functions: 1130*0Sstevel@tonic-gate * Currently unsupported by hypervisor 1131*0Sstevel@tonic-gate */ 1132*0Sstevel@tonic-gate /*ARGSUSED*/ 1133*0Sstevel@tonic-gate int 1134*0Sstevel@tonic-gate px_lib_tools_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 1135*0Sstevel@tonic-gate { 1136*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1137*0Sstevel@tonic-gate 1138*0Sstevel@tonic-gate DBG(DBG_TOOLS, dip, "px_lib_tools_dev_reg_ops: dip 0x%p arg 0x%p " 1139*0Sstevel@tonic-gate "cmd 0x%x mode 0x%x\n", dip, arg, cmd, mode); 1140*0Sstevel@tonic-gate 1141*0Sstevel@tonic-gate return (px_dev_reg_ops(dip, arg, cmd, mode, px_p)); 1142*0Sstevel@tonic-gate } 1143*0Sstevel@tonic-gate 1144*0Sstevel@tonic-gate /*ARGSUSED*/ 1145*0Sstevel@tonic-gate int 1146*0Sstevel@tonic-gate px_lib_tools_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 1147*0Sstevel@tonic-gate { 1148*0Sstevel@tonic-gate DBG(DBG_TOOLS, dip, "px_lib_tools_bus_reg_ops: dip 0x%p arg 0x%p " 1149*0Sstevel@tonic-gate "cmd 0x%x mode 0x%x\n", dip, arg, cmd, mode); 1150*0Sstevel@tonic-gate 1151*0Sstevel@tonic-gate return (px_bus_reg_ops(dip, arg, cmd, mode)); 1152*0Sstevel@tonic-gate } 1153*0Sstevel@tonic-gate 1154*0Sstevel@tonic-gate /*ARGSUSED*/ 1155*0Sstevel@tonic-gate int 1156*0Sstevel@tonic-gate px_lib_tools_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 1157*0Sstevel@tonic-gate { 1158*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1159*0Sstevel@tonic-gate 1160*0Sstevel@tonic-gate DBG(DBG_TOOLS, dip, "px_lib_tools_intr_admn: dip 0x%p arg 0x%p " 1161*0Sstevel@tonic-gate "cmd 0x%x mode 0x%x\n", dip, arg, cmd, mode); 1162*0Sstevel@tonic-gate 1163*0Sstevel@tonic-gate return (px_intr_admn(dip, arg, cmd, mode, px_p)); 1164*0Sstevel@tonic-gate } 1165*0Sstevel@tonic-gate 1166*0Sstevel@tonic-gate /* 1167*0Sstevel@tonic-gate * Misc Functions: 1168*0Sstevel@tonic-gate * Currently unsupported by hypervisor 1169*0Sstevel@tonic-gate */ 1170*0Sstevel@tonic-gate uint64_t 1171*0Sstevel@tonic-gate px_lib_get_cb(caddr_t csr) 1172*0Sstevel@tonic-gate { 1173*0Sstevel@tonic-gate return (CSR_XR(csr, JBUS_SCRATCH_1)); 1174*0Sstevel@tonic-gate } 1175*0Sstevel@tonic-gate 1176*0Sstevel@tonic-gate void 1177*0Sstevel@tonic-gate px_lib_set_cb(caddr_t csr, uint64_t val) 1178*0Sstevel@tonic-gate { 1179*0Sstevel@tonic-gate CSR_XS(csr, JBUS_SCRATCH_1, val); 1180*0Sstevel@tonic-gate } 1181*0Sstevel@tonic-gate 1182*0Sstevel@tonic-gate /*ARGSUSED*/ 1183*0Sstevel@tonic-gate int 1184*0Sstevel@tonic-gate px_lib_map_vconfig(dev_info_t *dip, 1185*0Sstevel@tonic-gate ddi_map_req_t *mp, pci_config_offset_t off, 1186*0Sstevel@tonic-gate pci_regspec_t *rp, caddr_t *addrp) 1187*0Sstevel@tonic-gate { 1188*0Sstevel@tonic-gate /* 1189*0Sstevel@tonic-gate * No special config space access services in this layer. 1190*0Sstevel@tonic-gate */ 1191*0Sstevel@tonic-gate return (DDI_FAILURE); 1192*0Sstevel@tonic-gate } 1193*0Sstevel@tonic-gate 1194*0Sstevel@tonic-gate #ifdef DEBUG 1195*0Sstevel@tonic-gate int px_peekfault_cnt = 0; 1196*0Sstevel@tonic-gate int px_pokefault_cnt = 0; 1197*0Sstevel@tonic-gate #endif /* DEBUG */ 1198*0Sstevel@tonic-gate 1199*0Sstevel@tonic-gate /*ARGSUSED*/ 1200*0Sstevel@tonic-gate static int 1201*0Sstevel@tonic-gate px_lib_do_poke(dev_info_t *dip, dev_info_t *rdip, 1202*0Sstevel@tonic-gate peekpoke_ctlops_t *in_args) 1203*0Sstevel@tonic-gate { 1204*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1205*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 1206*0Sstevel@tonic-gate int err = DDI_SUCCESS; 1207*0Sstevel@tonic-gate on_trap_data_t otd; 1208*0Sstevel@tonic-gate 1209*0Sstevel@tonic-gate mutex_enter(&pec_p->pec_pokefault_mutex); 1210*0Sstevel@tonic-gate pec_p->pec_ontrap_data = &otd; 1211*0Sstevel@tonic-gate 1212*0Sstevel@tonic-gate /* Set up protected environment. */ 1213*0Sstevel@tonic-gate if (!on_trap(&otd, OT_DATA_ACCESS)) { 1214*0Sstevel@tonic-gate uintptr_t tramp = otd.ot_trampoline; 1215*0Sstevel@tonic-gate 1216*0Sstevel@tonic-gate otd.ot_trampoline = (uintptr_t)&poke_fault; 1217*0Sstevel@tonic-gate err = do_poke(in_args->size, (void *)in_args->dev_addr, 1218*0Sstevel@tonic-gate (void *)in_args->host_addr); 1219*0Sstevel@tonic-gate otd.ot_trampoline = tramp; 1220*0Sstevel@tonic-gate } else 1221*0Sstevel@tonic-gate err = DDI_FAILURE; 1222*0Sstevel@tonic-gate 1223*0Sstevel@tonic-gate /* 1224*0Sstevel@tonic-gate * Read the async fault register for the PEC to see it sees 1225*0Sstevel@tonic-gate * a master-abort. 1226*0Sstevel@tonic-gate * 1227*0Sstevel@tonic-gate * XXX check if we need to clear errors at this point. 1228*0Sstevel@tonic-gate */ 1229*0Sstevel@tonic-gate if (otd.ot_trap & OT_DATA_ACCESS) 1230*0Sstevel@tonic-gate err = DDI_FAILURE; 1231*0Sstevel@tonic-gate 1232*0Sstevel@tonic-gate /* Take down protected environment. */ 1233*0Sstevel@tonic-gate no_trap(); 1234*0Sstevel@tonic-gate 1235*0Sstevel@tonic-gate pec_p->pec_ontrap_data = NULL; 1236*0Sstevel@tonic-gate mutex_exit(&pec_p->pec_pokefault_mutex); 1237*0Sstevel@tonic-gate 1238*0Sstevel@tonic-gate #ifdef DEBUG 1239*0Sstevel@tonic-gate if (err == DDI_FAILURE) 1240*0Sstevel@tonic-gate px_pokefault_cnt++; 1241*0Sstevel@tonic-gate #endif 1242*0Sstevel@tonic-gate return (err); 1243*0Sstevel@tonic-gate } 1244*0Sstevel@tonic-gate 1245*0Sstevel@tonic-gate /*ARGSUSED*/ 1246*0Sstevel@tonic-gate static int 1247*0Sstevel@tonic-gate px_lib_do_caut_put(dev_info_t *dip, dev_info_t *rdip, 1248*0Sstevel@tonic-gate peekpoke_ctlops_t *cautacc_ctlops_arg) 1249*0Sstevel@tonic-gate { 1250*0Sstevel@tonic-gate size_t size = cautacc_ctlops_arg->size; 1251*0Sstevel@tonic-gate uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1252*0Sstevel@tonic-gate uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1253*0Sstevel@tonic-gate ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1254*0Sstevel@tonic-gate size_t repcount = cautacc_ctlops_arg->repcount; 1255*0Sstevel@tonic-gate uint_t flags = cautacc_ctlops_arg->flags; 1256*0Sstevel@tonic-gate 1257*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1258*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 1259*0Sstevel@tonic-gate int err = DDI_SUCCESS; 1260*0Sstevel@tonic-gate 1261*0Sstevel@tonic-gate /* Use ontrap data in handle set up by FMA */ 1262*0Sstevel@tonic-gate pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1263*0Sstevel@tonic-gate 1264*0Sstevel@tonic-gate hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1265*0Sstevel@tonic-gate i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1266*0Sstevel@tonic-gate 1267*0Sstevel@tonic-gate mutex_enter(&pec_p->pec_pokefault_mutex); 1268*0Sstevel@tonic-gate 1269*0Sstevel@tonic-gate if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1270*0Sstevel@tonic-gate for (; repcount; repcount--) { 1271*0Sstevel@tonic-gate switch (size) { 1272*0Sstevel@tonic-gate 1273*0Sstevel@tonic-gate case sizeof (uint8_t): 1274*0Sstevel@tonic-gate i_ddi_put8(hp, (uint8_t *)dev_addr, 1275*0Sstevel@tonic-gate *(uint8_t *)host_addr); 1276*0Sstevel@tonic-gate break; 1277*0Sstevel@tonic-gate 1278*0Sstevel@tonic-gate case sizeof (uint16_t): 1279*0Sstevel@tonic-gate i_ddi_put16(hp, (uint16_t *)dev_addr, 1280*0Sstevel@tonic-gate *(uint16_t *)host_addr); 1281*0Sstevel@tonic-gate break; 1282*0Sstevel@tonic-gate 1283*0Sstevel@tonic-gate case sizeof (uint32_t): 1284*0Sstevel@tonic-gate i_ddi_put32(hp, (uint32_t *)dev_addr, 1285*0Sstevel@tonic-gate *(uint32_t *)host_addr); 1286*0Sstevel@tonic-gate break; 1287*0Sstevel@tonic-gate 1288*0Sstevel@tonic-gate case sizeof (uint64_t): 1289*0Sstevel@tonic-gate i_ddi_put64(hp, (uint64_t *)dev_addr, 1290*0Sstevel@tonic-gate *(uint64_t *)host_addr); 1291*0Sstevel@tonic-gate break; 1292*0Sstevel@tonic-gate } 1293*0Sstevel@tonic-gate 1294*0Sstevel@tonic-gate host_addr += size; 1295*0Sstevel@tonic-gate 1296*0Sstevel@tonic-gate if (flags == DDI_DEV_AUTOINCR) 1297*0Sstevel@tonic-gate dev_addr += size; 1298*0Sstevel@tonic-gate 1299*0Sstevel@tonic-gate /* 1300*0Sstevel@tonic-gate * Read the async fault register for the PEC to see it 1301*0Sstevel@tonic-gate * sees a master-abort. 1302*0Sstevel@tonic-gate * 1303*0Sstevel@tonic-gate * XXX check if we need to clear errors at this point. 1304*0Sstevel@tonic-gate */ 1305*0Sstevel@tonic-gate if (pec_p->pec_ontrap_data->ot_trap & OT_DATA_ACCESS) { 1306*0Sstevel@tonic-gate err = DDI_FAILURE; 1307*0Sstevel@tonic-gate #ifdef DEBUG 1308*0Sstevel@tonic-gate px_pokefault_cnt++; 1309*0Sstevel@tonic-gate #endif 1310*0Sstevel@tonic-gate break; 1311*0Sstevel@tonic-gate } 1312*0Sstevel@tonic-gate } 1313*0Sstevel@tonic-gate } 1314*0Sstevel@tonic-gate 1315*0Sstevel@tonic-gate i_ddi_notrap((ddi_acc_handle_t)hp); 1316*0Sstevel@tonic-gate pec_p->pec_ontrap_data = NULL; 1317*0Sstevel@tonic-gate mutex_exit(&pec_p->pec_pokefault_mutex); 1318*0Sstevel@tonic-gate i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1319*0Sstevel@tonic-gate hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1320*0Sstevel@tonic-gate 1321*0Sstevel@tonic-gate return (err); 1322*0Sstevel@tonic-gate } 1323*0Sstevel@tonic-gate 1324*0Sstevel@tonic-gate 1325*0Sstevel@tonic-gate int 1326*0Sstevel@tonic-gate px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1327*0Sstevel@tonic-gate peekpoke_ctlops_t *in_args) 1328*0Sstevel@tonic-gate { 1329*0Sstevel@tonic-gate return (in_args->handle ? px_lib_do_caut_put(dip, rdip, in_args) : 1330*0Sstevel@tonic-gate px_lib_do_poke(dip, rdip, in_args)); 1331*0Sstevel@tonic-gate } 1332*0Sstevel@tonic-gate 1333*0Sstevel@tonic-gate 1334*0Sstevel@tonic-gate /*ARGSUSED*/ 1335*0Sstevel@tonic-gate static int 1336*0Sstevel@tonic-gate px_lib_do_peek(dev_info_t *dip, peekpoke_ctlops_t *in_args) 1337*0Sstevel@tonic-gate { 1338*0Sstevel@tonic-gate int err = DDI_SUCCESS; 1339*0Sstevel@tonic-gate on_trap_data_t otd; 1340*0Sstevel@tonic-gate 1341*0Sstevel@tonic-gate if (!on_trap(&otd, OT_DATA_ACCESS)) { 1342*0Sstevel@tonic-gate uintptr_t tramp = otd.ot_trampoline; 1343*0Sstevel@tonic-gate 1344*0Sstevel@tonic-gate otd.ot_trampoline = (uintptr_t)&peek_fault; 1345*0Sstevel@tonic-gate err = do_peek(in_args->size, (void *)in_args->dev_addr, 1346*0Sstevel@tonic-gate (void *)in_args->host_addr); 1347*0Sstevel@tonic-gate otd.ot_trampoline = tramp; 1348*0Sstevel@tonic-gate } else 1349*0Sstevel@tonic-gate err = DDI_FAILURE; 1350*0Sstevel@tonic-gate 1351*0Sstevel@tonic-gate no_trap(); 1352*0Sstevel@tonic-gate 1353*0Sstevel@tonic-gate #ifdef DEBUG 1354*0Sstevel@tonic-gate if (err == DDI_FAILURE) 1355*0Sstevel@tonic-gate px_peekfault_cnt++; 1356*0Sstevel@tonic-gate #endif 1357*0Sstevel@tonic-gate return (err); 1358*0Sstevel@tonic-gate } 1359*0Sstevel@tonic-gate 1360*0Sstevel@tonic-gate 1361*0Sstevel@tonic-gate static int 1362*0Sstevel@tonic-gate px_lib_do_caut_get(dev_info_t *dip, peekpoke_ctlops_t *cautacc_ctlops_arg) 1363*0Sstevel@tonic-gate { 1364*0Sstevel@tonic-gate size_t size = cautacc_ctlops_arg->size; 1365*0Sstevel@tonic-gate uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1366*0Sstevel@tonic-gate uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1367*0Sstevel@tonic-gate ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1368*0Sstevel@tonic-gate size_t repcount = cautacc_ctlops_arg->repcount; 1369*0Sstevel@tonic-gate uint_t flags = cautacc_ctlops_arg->flags; 1370*0Sstevel@tonic-gate 1371*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 1372*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 1373*0Sstevel@tonic-gate int err = DDI_SUCCESS; 1374*0Sstevel@tonic-gate 1375*0Sstevel@tonic-gate hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1376*0Sstevel@tonic-gate i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1377*0Sstevel@tonic-gate 1378*0Sstevel@tonic-gate if (repcount == 1) { 1379*0Sstevel@tonic-gate if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1380*0Sstevel@tonic-gate i_ddi_caut_get(size, (void *)dev_addr, 1381*0Sstevel@tonic-gate (void *)host_addr); 1382*0Sstevel@tonic-gate } else { 1383*0Sstevel@tonic-gate int i; 1384*0Sstevel@tonic-gate uint8_t *ff_addr = (uint8_t *)host_addr; 1385*0Sstevel@tonic-gate for (i = 0; i < size; i++) 1386*0Sstevel@tonic-gate *ff_addr++ = 0xff; 1387*0Sstevel@tonic-gate 1388*0Sstevel@tonic-gate err = DDI_FAILURE; 1389*0Sstevel@tonic-gate #ifdef DEBUG 1390*0Sstevel@tonic-gate px_peekfault_cnt++; 1391*0Sstevel@tonic-gate #endif 1392*0Sstevel@tonic-gate } 1393*0Sstevel@tonic-gate } else { 1394*0Sstevel@tonic-gate if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1395*0Sstevel@tonic-gate for (; repcount; repcount--) { 1396*0Sstevel@tonic-gate i_ddi_caut_get(size, (void *)dev_addr, 1397*0Sstevel@tonic-gate (void *)host_addr); 1398*0Sstevel@tonic-gate 1399*0Sstevel@tonic-gate host_addr += size; 1400*0Sstevel@tonic-gate 1401*0Sstevel@tonic-gate if (flags == DDI_DEV_AUTOINCR) 1402*0Sstevel@tonic-gate dev_addr += size; 1403*0Sstevel@tonic-gate } 1404*0Sstevel@tonic-gate } else { 1405*0Sstevel@tonic-gate err = DDI_FAILURE; 1406*0Sstevel@tonic-gate #ifdef DEBUG 1407*0Sstevel@tonic-gate px_peekfault_cnt++; 1408*0Sstevel@tonic-gate #endif 1409*0Sstevel@tonic-gate } 1410*0Sstevel@tonic-gate } 1411*0Sstevel@tonic-gate 1412*0Sstevel@tonic-gate i_ddi_notrap((ddi_acc_handle_t)hp); 1413*0Sstevel@tonic-gate pec_p->pec_ontrap_data = NULL; 1414*0Sstevel@tonic-gate i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1415*0Sstevel@tonic-gate hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1416*0Sstevel@tonic-gate 1417*0Sstevel@tonic-gate return (err); 1418*0Sstevel@tonic-gate } 1419*0Sstevel@tonic-gate 1420*0Sstevel@tonic-gate /*ARGSUSED*/ 1421*0Sstevel@tonic-gate int 1422*0Sstevel@tonic-gate px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1423*0Sstevel@tonic-gate peekpoke_ctlops_t *in_args, void *result) 1424*0Sstevel@tonic-gate { 1425*0Sstevel@tonic-gate result = (void *)in_args->host_addr; 1426*0Sstevel@tonic-gate return (in_args->handle ? px_lib_do_caut_get(dip, in_args) : 1427*0Sstevel@tonic-gate px_lib_do_peek(dip, in_args)); 1428*0Sstevel@tonic-gate } 1429*0Sstevel@tonic-gate /* 1430*0Sstevel@tonic-gate * implements PPM interface 1431*0Sstevel@tonic-gate */ 1432*0Sstevel@tonic-gate int 1433*0Sstevel@tonic-gate px_lib_pmctl(int cmd, px_t *px_p) 1434*0Sstevel@tonic-gate { 1435*0Sstevel@tonic-gate ASSERT((cmd & ~PPMREQ_MASK) == PPMREQ); 1436*0Sstevel@tonic-gate switch (cmd) { 1437*0Sstevel@tonic-gate case PPMREQ_PRE_PWR_OFF: 1438*0Sstevel@tonic-gate /* 1439*0Sstevel@tonic-gate * Currently there is no device power management for 1440*0Sstevel@tonic-gate * the root complex (fire). When there is we need to make 1441*0Sstevel@tonic-gate * sure that it is at full power before trying to send the 1442*0Sstevel@tonic-gate * PME_Turn_Off message. 1443*0Sstevel@tonic-gate */ 1444*0Sstevel@tonic-gate DBG(DBG_PWR, px_p->px_dip, 1445*0Sstevel@tonic-gate "ioctl: request to send PME_Turn_Off\n"); 1446*0Sstevel@tonic-gate return (px_goto_l23ready(px_p)); 1447*0Sstevel@tonic-gate 1448*0Sstevel@tonic-gate case PPMREQ_PRE_PWR_ON: 1449*0Sstevel@tonic-gate case PPMREQ_POST_PWR_ON: 1450*0Sstevel@tonic-gate /* code to be written for Fire 2.0. return failure for now */ 1451*0Sstevel@tonic-gate return (DDI_FAILURE); 1452*0Sstevel@tonic-gate 1453*0Sstevel@tonic-gate default: 1454*0Sstevel@tonic-gate return (DDI_FAILURE); 1455*0Sstevel@tonic-gate } 1456*0Sstevel@tonic-gate } 1457*0Sstevel@tonic-gate 1458*0Sstevel@tonic-gate /* 1459*0Sstevel@tonic-gate * sends PME_Turn_Off message to put the link in L2/L3 ready state. 1460*0Sstevel@tonic-gate * called by px_ioctl. 1461*0Sstevel@tonic-gate * returns DDI_SUCCESS or DDI_FAILURE 1462*0Sstevel@tonic-gate * 1. Wait for link to be in L1 state (link status reg) 1463*0Sstevel@tonic-gate * 2. write to PME_Turn_off reg to boradcast 1464*0Sstevel@tonic-gate * 3. set timeout 1465*0Sstevel@tonic-gate * 4. If timeout, return failure. 1466*0Sstevel@tonic-gate * 5. If PM_TO_Ack, wait till link is in L2/L3 ready 1467*0Sstevel@tonic-gate */ 1468*0Sstevel@tonic-gate static int 1469*0Sstevel@tonic-gate px_goto_l23ready(px_t *px_p) 1470*0Sstevel@tonic-gate { 1471*0Sstevel@tonic-gate pcie_pwr_t *pwr_p; 1472*0Sstevel@tonic-gate caddr_t csr_base = (caddr_t)px_p->px_address[PX_REG_CSR]; 1473*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 1474*0Sstevel@tonic-gate clock_t end, timeleft; 1475*0Sstevel@tonic-gate 1476*0Sstevel@tonic-gate /* If no PM info, return failure */ 1477*0Sstevel@tonic-gate if (!PCIE_PMINFO(px_p->px_dip) || 1478*0Sstevel@tonic-gate !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1479*0Sstevel@tonic-gate return (DDI_FAILURE); 1480*0Sstevel@tonic-gate 1481*0Sstevel@tonic-gate mutex_enter(&pwr_p->pwr_lock); 1482*0Sstevel@tonic-gate mutex_enter(&pwr_p->pwr_intr_lock); 1483*0Sstevel@tonic-gate /* Clear the PME_To_ACK receieved flag */ 1484*0Sstevel@tonic-gate pwr_p->pwr_flags &= ~PCIE_PMETOACK_RECVD; 1485*0Sstevel@tonic-gate if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) { 1486*0Sstevel@tonic-gate ret = DDI_FAILURE; 1487*0Sstevel@tonic-gate goto l23ready_done; 1488*0Sstevel@tonic-gate } 1489*0Sstevel@tonic-gate pwr_p->pwr_flags |= PCIE_PME_TURNOFF_PENDING; 1490*0Sstevel@tonic-gate 1491*0Sstevel@tonic-gate end = ddi_get_lbolt() + drv_usectohz(px_pme_to_ack_timeout); 1492*0Sstevel@tonic-gate while (!(pwr_p->pwr_flags & PCIE_PMETOACK_RECVD)) { 1493*0Sstevel@tonic-gate timeleft = cv_timedwait(&pwr_p->pwr_cv, 1494*0Sstevel@tonic-gate &pwr_p->pwr_intr_lock, end); 1495*0Sstevel@tonic-gate /* 1496*0Sstevel@tonic-gate * if cv_timedwait returns -1, it is either 1497*0Sstevel@tonic-gate * 1) timed out or 1498*0Sstevel@tonic-gate * 2) there was a pre-mature wakeup but by the time 1499*0Sstevel@tonic-gate * cv_timedwait is called again end < lbolt i.e. 1500*0Sstevel@tonic-gate * end is in the past. 1501*0Sstevel@tonic-gate * 3) By the time we make first cv_timedwait call, 1502*0Sstevel@tonic-gate * end < lbolt is true. 1503*0Sstevel@tonic-gate */ 1504*0Sstevel@tonic-gate if (timeleft == -1) 1505*0Sstevel@tonic-gate break; 1506*0Sstevel@tonic-gate } 1507*0Sstevel@tonic-gate if (!(pwr_p->pwr_flags & PCIE_PMETOACK_RECVD)) { 1508*0Sstevel@tonic-gate /* 1509*0Sstevel@tonic-gate * Either timedout or interrupt didn't get a 1510*0Sstevel@tonic-gate * chance to grab the mutex and set the flag. 1511*0Sstevel@tonic-gate * release the mutex and delay for sometime. 1512*0Sstevel@tonic-gate * This will 1) give a chance for interrupt to 1513*0Sstevel@tonic-gate * set the flag 2) creates a delay between two 1514*0Sstevel@tonic-gate * consequetive requests. 1515*0Sstevel@tonic-gate */ 1516*0Sstevel@tonic-gate mutex_exit(&pwr_p->pwr_intr_lock); 1517*0Sstevel@tonic-gate delay(5); 1518*0Sstevel@tonic-gate mutex_enter(&pwr_p->pwr_intr_lock); 1519*0Sstevel@tonic-gate if (!(pwr_p->pwr_flags & PCIE_PMETOACK_RECVD)) { 1520*0Sstevel@tonic-gate ret = DDI_FAILURE; 1521*0Sstevel@tonic-gate DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1522*0Sstevel@tonic-gate " for PME_TO_ACK\n"); 1523*0Sstevel@tonic-gate } 1524*0Sstevel@tonic-gate } 1525*0Sstevel@tonic-gate /* PME_To_ACK receieved */ 1526*0Sstevel@tonic-gate pwr_p->pwr_flags &= ~(PCIE_PME_TURNOFF_PENDING | PCIE_PMETOACK_RECVD); 1527*0Sstevel@tonic-gate 1528*0Sstevel@tonic-gate /* TBD: wait till link is in L2/L3 ready (link status reg) */ 1529*0Sstevel@tonic-gate 1530*0Sstevel@tonic-gate l23ready_done: 1531*0Sstevel@tonic-gate mutex_exit(&pwr_p->pwr_intr_lock); 1532*0Sstevel@tonic-gate mutex_exit(&pwr_p->pwr_lock); 1533*0Sstevel@tonic-gate return (ret); 1534*0Sstevel@tonic-gate } 1535*0Sstevel@tonic-gate 1536*0Sstevel@tonic-gate 1537*0Sstevel@tonic-gate /* 1538*0Sstevel@tonic-gate * Extract the drivers binding name to identify which chip we're binding to. 1539*0Sstevel@tonic-gate * Whenever a new bus bridge is created, the driver alias entry should be 1540*0Sstevel@tonic-gate * added here to identify the device if needed. If a device isn't added, 1541*0Sstevel@tonic-gate * the identity defaults to PX_CHIP_UNIDENTIFIED. 1542*0Sstevel@tonic-gate */ 1543*0Sstevel@tonic-gate static uint32_t 1544*0Sstevel@tonic-gate px_identity_chip(px_t *px_p) 1545*0Sstevel@tonic-gate { 1546*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 1547*0Sstevel@tonic-gate char *name = ddi_binding_name(dip); 1548*0Sstevel@tonic-gate uint32_t revision = 0; 1549*0Sstevel@tonic-gate 1550*0Sstevel@tonic-gate revision = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1551*0Sstevel@tonic-gate "module-revision#", 0); 1552*0Sstevel@tonic-gate 1553*0Sstevel@tonic-gate /* Check for Fire driver binding name */ 1554*0Sstevel@tonic-gate if (strcmp(name, "pci108e,80f0") == 0) { 1555*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "px_identity_chip: %s%d: " 1556*0Sstevel@tonic-gate "name %s module-revision %d\n", ddi_driver_name(dip), 1557*0Sstevel@tonic-gate ddi_get_instance(dip), name, revision); 1558*0Sstevel@tonic-gate 1559*0Sstevel@tonic-gate return (PX_CHIP_ID(PX_CHIP_FIRE, revision, 0x00)); 1560*0Sstevel@tonic-gate } 1561*0Sstevel@tonic-gate 1562*0Sstevel@tonic-gate DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n", 1563*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), name, revision); 1564*0Sstevel@tonic-gate 1565*0Sstevel@tonic-gate return (PX_CHIP_UNIDENTIFIED); 1566*0Sstevel@tonic-gate } 1567