1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/cmn_err.h> 31*0Sstevel@tonic-gate #include <sys/vmsystm.h> 32*0Sstevel@tonic-gate #include <sys/vmem.h> 33*0Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys() */ 34*0Sstevel@tonic-gate #include <sys/iommutsb.h> 35*0Sstevel@tonic-gate #include <sys/pci.h> 36*0Sstevel@tonic-gate #include <pcie_pwr.h> 37*0Sstevel@tonic-gate #include <px_obj.h> 38*0Sstevel@tonic-gate #include "px_regs.h" 39*0Sstevel@tonic-gate #include "px_csr.h" 40*0Sstevel@tonic-gate #include "px_lib4u.h" 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate /* 43*0Sstevel@tonic-gate * Registers that need to be saved and restored during suspend/resume. 44*0Sstevel@tonic-gate */ 45*0Sstevel@tonic-gate 46*0Sstevel@tonic-gate /* 47*0Sstevel@tonic-gate * Registers in the PEC Module. 48*0Sstevel@tonic-gate * LPU_RESET should be set to 0ull during resume 49*0Sstevel@tonic-gate */ 50*0Sstevel@tonic-gate static uint64_t pec_config_state_regs[] = { 51*0Sstevel@tonic-gate PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, 52*0Sstevel@tonic-gate ILU_ERROR_LOG_ENABLE, 53*0Sstevel@tonic-gate ILU_INTERRUPT_ENABLE, 54*0Sstevel@tonic-gate TLU_CONTROL, 55*0Sstevel@tonic-gate TLU_OTHER_EVENT_LOG_ENABLE, 56*0Sstevel@tonic-gate TLU_OTHER_EVENT_INTERRUPT_ENABLE, 57*0Sstevel@tonic-gate TLU_DEVICE_CONTROL, 58*0Sstevel@tonic-gate TLU_LINK_CONTROL, 59*0Sstevel@tonic-gate TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, 60*0Sstevel@tonic-gate TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE, 61*0Sstevel@tonic-gate TLU_CORRECTABLE_ERROR_LOG_ENABLE, 62*0Sstevel@tonic-gate TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE, 63*0Sstevel@tonic-gate LPU_DEBUG_CONFIG, 64*0Sstevel@tonic-gate LPU_INTERRUPT_MASK, 65*0Sstevel@tonic-gate LPU_LINK_LAYER_CONFIG, 66*0Sstevel@tonic-gate LPU_FLOW_CONTROL_UPDATE_CONTROL, 67*0Sstevel@tonic-gate LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, 68*0Sstevel@tonic-gate LPU_TXLINK_REPLAY_TIMER_THRESHOLD, 69*0Sstevel@tonic-gate LPU_REPLAY_BUFFER_MAX_ADDRESS, 70*0Sstevel@tonic-gate LPU_TXLINK_RETRY_FIFO_POINTER, 71*0Sstevel@tonic-gate LPU_PHY_INTERRUPT_MASK, 72*0Sstevel@tonic-gate LPU_RECEIVE_PHY_INTERRUPT_MASK, 73*0Sstevel@tonic-gate LPU_TRANSMIT_PHY_INTERRUPT_MASK, 74*0Sstevel@tonic-gate LPU_LTSSM_CONFIG2, 75*0Sstevel@tonic-gate LPU_LTSSM_CONFIG3, 76*0Sstevel@tonic-gate LPU_LTSSM_CONFIG4, 77*0Sstevel@tonic-gate LPU_LTSSM_CONFIG5, 78*0Sstevel@tonic-gate LPU_LTSSM_INTERRUPT_MASK, 79*0Sstevel@tonic-gate LPU_GIGABLAZE_GLUE_INTERRUPT_MASK, 80*0Sstevel@tonic-gate DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, 81*0Sstevel@tonic-gate DMC_DEBUG_SELECT_FOR_PORT_A, 82*0Sstevel@tonic-gate DMC_DEBUG_SELECT_FOR_PORT_B 83*0Sstevel@tonic-gate }; 84*0Sstevel@tonic-gate #define PEC_SIZE (sizeof (pec_config_state_regs)) 85*0Sstevel@tonic-gate #define PEC_KEYS (PEC_SIZE / sizeof (uint64_t)) 86*0Sstevel@tonic-gate 87*0Sstevel@tonic-gate /* 88*0Sstevel@tonic-gate * Registers for the MMU module. 89*0Sstevel@tonic-gate * MMU_TTE_CACHE_INVALIDATE needs to be cleared. (-1ull) 90*0Sstevel@tonic-gate */ 91*0Sstevel@tonic-gate static uint64_t mmu_config_state_regs[] = { 92*0Sstevel@tonic-gate MMU_TSB_CONTROL, 93*0Sstevel@tonic-gate MMU_CONTROL_AND_STATUS, 94*0Sstevel@tonic-gate MMU_INTERRUPT_ENABLE 95*0Sstevel@tonic-gate }; 96*0Sstevel@tonic-gate #define MMU_SIZE (sizeof (mmu_config_state_regs)) 97*0Sstevel@tonic-gate #define MMU_KEYS (MMU_SIZE / sizeof (uint64_t)) 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate /* 100*0Sstevel@tonic-gate * Registers for the IB Module 101*0Sstevel@tonic-gate */ 102*0Sstevel@tonic-gate static uint64_t ib_config_state_regs[] = { 103*0Sstevel@tonic-gate IMU_ERROR_LOG_ENABLE, 104*0Sstevel@tonic-gate IMU_INTERRUPT_ENABLE 105*0Sstevel@tonic-gate }; 106*0Sstevel@tonic-gate #define IB_SIZE (sizeof (ib_config_state_regs)) 107*0Sstevel@tonic-gate #define IB_KEYS (IB_SIZE / sizeof (uint64_t)) 108*0Sstevel@tonic-gate #define IB_MAP_SIZE (INTERRUPT_MAPPING_ENTRIES * sizeof (uint64_t)) 109*0Sstevel@tonic-gate 110*0Sstevel@tonic-gate /* 111*0Sstevel@tonic-gate * Registers for the CB module. 112*0Sstevel@tonic-gate * JBC_ERROR_STATUS_CLEAR needs to be cleared. (-1ull) 113*0Sstevel@tonic-gate */ 114*0Sstevel@tonic-gate static uint64_t cb_config_state_regs[] = { 115*0Sstevel@tonic-gate JBUS_PARITY_CONTROL, 116*0Sstevel@tonic-gate JBC_FATAL_RESET_ENABLE, 117*0Sstevel@tonic-gate JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, 118*0Sstevel@tonic-gate JBC_ERROR_LOG_ENABLE, 119*0Sstevel@tonic-gate JBC_INTERRUPT_ENABLE 120*0Sstevel@tonic-gate }; 121*0Sstevel@tonic-gate #define CB_SIZE (sizeof (cb_config_state_regs)) 122*0Sstevel@tonic-gate #define CB_KEYS (CB_SIZE / sizeof (uint64_t)) 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate static uint64_t msiq_config_other_regs[] = { 125*0Sstevel@tonic-gate ERR_COR_MAPPING, 126*0Sstevel@tonic-gate ERR_NONFATAL_MAPPING, 127*0Sstevel@tonic-gate ERR_FATAL_MAPPING, 128*0Sstevel@tonic-gate PM_PME_MAPPING, 129*0Sstevel@tonic-gate PME_TO_ACK_MAPPING, 130*0Sstevel@tonic-gate MSI_32_BIT_ADDRESS, 131*0Sstevel@tonic-gate MSI_64_BIT_ADDRESS 132*0Sstevel@tonic-gate }; 133*0Sstevel@tonic-gate #define MSIQ_OTHER_SIZE (sizeof (msiq_config_other_regs)) 134*0Sstevel@tonic-gate #define MSIQ_OTHER_KEYS (MSIQ_OTHER_SIZE / sizeof (uint64_t)) 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate #define MSIQ_STATE_SIZE (EVENT_QUEUE_STATE_ENTRIES * sizeof (uint64_t)) 137*0Sstevel@tonic-gate #define MSIQ_MAPPING_SIZE (MSI_MAPPING_ENTRIES * sizeof (uint64_t)) 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate static uint64_t msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 140*0Sstevel@tonic-gate static void msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p); 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate /* ARGSUSED */ 143*0Sstevel@tonic-gate void 144*0Sstevel@tonic-gate hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p) 145*0Sstevel@tonic-gate { 146*0Sstevel@tonic-gate uint64_t val; 147*0Sstevel@tonic-gate 148*0Sstevel@tonic-gate /* Check if we need to enable inverted parity */ 149*0Sstevel@tonic-gate val = (1ULL << JBUS_PARITY_CONTROL_P_EN); 150*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBUS_PARITY_CONTROL, val); 151*0Sstevel@tonic-gate DBG(DBG_CB, NULL, "hvio_cb_init, JBUS_PARITY_CONTROL: 0x%llx\n", 152*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBUS_PARITY_CONTROL)); 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate val = (1 << JBC_FATAL_RESET_ENABLE_SPARE_P_INT_EN)| 155*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_MB_PEA_P_INT_EN) | 156*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_CPE_P_INT_EN) | 157*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_APE_P_INT_EN) | 158*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_PIO_CPE_INT_EN) | 159*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_JTCEEW_P_INT_EN) | 160*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_JTCEEI_P_INT_EN) | 161*0Sstevel@tonic-gate (1 << JBC_FATAL_RESET_ENABLE_JTCEER_P_INT_EN); 162*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBC_FATAL_RESET_ENABLE, val); 163*0Sstevel@tonic-gate DBG(DBG_CB, NULL, "hvio_cb_init, JBC_FATAL_RESET_ENABLE: 0x%llx\n", 164*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBC_FATAL_RESET_ENABLE)); 165*0Sstevel@tonic-gate 166*0Sstevel@tonic-gate /* 167*0Sstevel@tonic-gate * Enable merge, jbc and dmc interrupts. 168*0Sstevel@tonic-gate */ 169*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE, -1ull); 170*0Sstevel@tonic-gate DBG(DBG_CB, NULL, 171*0Sstevel@tonic-gate "hvio_cb_init, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 172*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate /* 175*0Sstevel@tonic-gate * Enable all error log bits. 176*0Sstevel@tonic-gate */ 177*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBC_ERROR_LOG_ENABLE, -1ull); 178*0Sstevel@tonic-gate DBG(DBG_CB, NULL, "hvio_cb_init, JBC_ERROR_LOG_ENABLE: 0x%llx\n", 179*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBC_ERROR_LOG_ENABLE)); 180*0Sstevel@tonic-gate 181*0Sstevel@tonic-gate /* 182*0Sstevel@tonic-gate * Enable all interrupts. 183*0Sstevel@tonic-gate */ 184*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBC_INTERRUPT_ENABLE, -1ull); 185*0Sstevel@tonic-gate DBG(DBG_CB, NULL, "hvio_cb_init, JBC_INTERRUPT_ENABLE: 0x%llx\n", 186*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBC_INTERRUPT_ENABLE)); 187*0Sstevel@tonic-gate 188*0Sstevel@tonic-gate /* 189*0Sstevel@tonic-gate * Emit warning for pending errors and flush the logged error 190*0Sstevel@tonic-gate * status register. 191*0Sstevel@tonic-gate */ 192*0Sstevel@tonic-gate val = CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR); 193*0Sstevel@tonic-gate 194*0Sstevel@tonic-gate CSR_XS(xbc_csr_base, JBC_ERROR_STATUS_CLEAR, -1ull); 195*0Sstevel@tonic-gate DBG(DBG_CB, NULL, "hvio_cb_init, JBC_ERROR_STATUS_CLEAR: 0x%llx\n", 196*0Sstevel@tonic-gate CSR_XR(xbc_csr_base, JBC_ERROR_STATUS_CLEAR)); 197*0Sstevel@tonic-gate } 198*0Sstevel@tonic-gate 199*0Sstevel@tonic-gate /* ARGSUSED */ 200*0Sstevel@tonic-gate void 201*0Sstevel@tonic-gate hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p) 202*0Sstevel@tonic-gate { 203*0Sstevel@tonic-gate uint64_t val; 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate /* 206*0Sstevel@tonic-gate * CSR_V IMU_ERROR_LOG_ENABLE Expect Kernel 0x3FF 207*0Sstevel@tonic-gate */ 208*0Sstevel@tonic-gate val = -1ull; 209*0Sstevel@tonic-gate CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, val); 210*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_LOG_ENABLE: 0x%llx\n", 211*0Sstevel@tonic-gate CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE)); 212*0Sstevel@tonic-gate 213*0Sstevel@tonic-gate /* 214*0Sstevel@tonic-gate * CSR_V IMU_INTERRUPT_ENABLE Expect Kernel 0x3FF000003FF 215*0Sstevel@tonic-gate */ 216*0Sstevel@tonic-gate val = -1ull; 217*0Sstevel@tonic-gate CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, val); 218*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_ENABLE: 0x%llx\n", 219*0Sstevel@tonic-gate CSR_XR(csr_base, IMU_INTERRUPT_ENABLE)); 220*0Sstevel@tonic-gate 221*0Sstevel@tonic-gate /* 222*0Sstevel@tonic-gate * CSR_V IMU_INTERRUPT_STATUS Expect HW 0x0 223*0Sstevel@tonic-gate */ 224*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_ib_init - IMU_INTERRUPT_STATUS: 0x%llx\n", 225*0Sstevel@tonic-gate CSR_XR(csr_base, IMU_INTERRUPT_STATUS)); 226*0Sstevel@tonic-gate 227*0Sstevel@tonic-gate /* 228*0Sstevel@tonic-gate * CSR_V IMU_ERROR_STATUS_CLEAR Expect HW 0x0 229*0Sstevel@tonic-gate */ 230*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_ib_init - IMU_ERROR_STATUS_CLEAR: 0x%llx\n", 231*0Sstevel@tonic-gate CSR_XR(csr_base, IMU_ERROR_STATUS_CLEAR)); 232*0Sstevel@tonic-gate } 233*0Sstevel@tonic-gate 234*0Sstevel@tonic-gate /* ARGSUSED */ 235*0Sstevel@tonic-gate static void 236*0Sstevel@tonic-gate ilu_init(caddr_t csr_base, pxu_t *pxu_p) 237*0Sstevel@tonic-gate { 238*0Sstevel@tonic-gate uint64_t val; 239*0Sstevel@tonic-gate 240*0Sstevel@tonic-gate /* 241*0Sstevel@tonic-gate * CSR_V ILU_ERROR_LOG_ENABLE Expect OBP 0x10 242*0Sstevel@tonic-gate */ 243*0Sstevel@tonic-gate 244*0Sstevel@tonic-gate val = 0ull; 245*0Sstevel@tonic-gate val = (1ull << ILU_ERROR_LOG_ENABLE_IHB_PE); 246*0Sstevel@tonic-gate 247*0Sstevel@tonic-gate CSR_XS(csr_base, ILU_ERROR_LOG_ENABLE, val); 248*0Sstevel@tonic-gate DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_LOG_ENABLE: 0x%llx\n", 249*0Sstevel@tonic-gate CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE)); 250*0Sstevel@tonic-gate 251*0Sstevel@tonic-gate /* 252*0Sstevel@tonic-gate * CSR_V ILU_INTERRUPT_ENABLE Expect OBP 0x1000000010 253*0Sstevel@tonic-gate */ 254*0Sstevel@tonic-gate 255*0Sstevel@tonic-gate val = (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 256*0Sstevel@tonic-gate (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate CSR_XS(csr_base, ILU_INTERRUPT_ENABLE, val); 259*0Sstevel@tonic-gate DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_ENABLE: 0x%llx\n", 260*0Sstevel@tonic-gate CSR_XR(csr_base, ILU_INTERRUPT_ENABLE)); 261*0Sstevel@tonic-gate 262*0Sstevel@tonic-gate /* 263*0Sstevel@tonic-gate * CSR_V ILU_INTERRUPT_STATUS Expect HW 0x1000000010 264*0Sstevel@tonic-gate */ 265*0Sstevel@tonic-gate DBG(DBG_ILU, NULL, "ilu_init - ILU_INTERRUPT_STATUS: 0x%llx\n", 266*0Sstevel@tonic-gate CSR_XR(csr_base, ILU_INTERRUPT_STATUS)); 267*0Sstevel@tonic-gate 268*0Sstevel@tonic-gate /* 269*0Sstevel@tonic-gate * CSR_V ILU_ERROR_STATUS_CLEAR Expect HW 0x0 270*0Sstevel@tonic-gate */ 271*0Sstevel@tonic-gate DBG(DBG_ILU, NULL, "ilu_init - ILU_ERROR_STATUS_CLEAR: 0x%llx\n", 272*0Sstevel@tonic-gate CSR_XR(csr_base, ILU_ERROR_STATUS_CLEAR)); 273*0Sstevel@tonic-gate } 274*0Sstevel@tonic-gate 275*0Sstevel@tonic-gate static void 276*0Sstevel@tonic-gate tlu_init(caddr_t csr_base, pxu_t *pxu_p) 277*0Sstevel@tonic-gate { 278*0Sstevel@tonic-gate uint64_t val; 279*0Sstevel@tonic-gate 280*0Sstevel@tonic-gate /* 281*0Sstevel@tonic-gate * CSR_V TLU_CONTROL Expect OBP ??? 282*0Sstevel@tonic-gate */ 283*0Sstevel@tonic-gate 284*0Sstevel@tonic-gate /* 285*0Sstevel@tonic-gate * L0s entry default timer value - 7.0 us 286*0Sstevel@tonic-gate * Completion timeout select default value - 67.1 ms and 287*0Sstevel@tonic-gate * OBP will set this value. 288*0Sstevel@tonic-gate * 289*0Sstevel@tonic-gate * Configuration - Bit 0 should always be 0 for upstream port. 290*0Sstevel@tonic-gate * Bit 1 is clock - how is this related to the clock bit in TLU 291*0Sstevel@tonic-gate * Link Control register? Both are hardware dependent and likely 292*0Sstevel@tonic-gate * set by OBP. 293*0Sstevel@tonic-gate * 294*0Sstevel@tonic-gate * Disable non-posted write bit - ordering by setting 295*0Sstevel@tonic-gate * NPWR_EN bit to force serialization of writes. 296*0Sstevel@tonic-gate */ 297*0Sstevel@tonic-gate val = CSR_XR(csr_base, TLU_CONTROL); 298*0Sstevel@tonic-gate 299*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 300*0Sstevel@tonic-gate val |= (TLU_CONTROL_L0S_TIM_DEFAULT << 301*0Sstevel@tonic-gate FIRE10_TLU_CONTROL_L0S_TIM) | 302*0Sstevel@tonic-gate (1ull << FIRE10_TLU_CONTROL_NPWR_EN) | 303*0Sstevel@tonic-gate TLU_CONTROL_CONFIG_DEFAULT; 304*0Sstevel@tonic-gate } else { 305*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 306*0Sstevel@tonic-gate val |= (TLU_CONTROL_L0S_TIM_DEFAULT << TLU_CONTROL_L0S_TIM) | 307*0Sstevel@tonic-gate (1ull << TLU_CONTROL_NPWR_EN) | TLU_CONTROL_CONFIG_DEFAULT; 308*0Sstevel@tonic-gate } 309*0Sstevel@tonic-gate 310*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_CONTROL, val); 311*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_CONTROL: 0x%llx\n", 312*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_CONTROL)); 313*0Sstevel@tonic-gate 314*0Sstevel@tonic-gate /* 315*0Sstevel@tonic-gate * CSR_V TLU_STATUS Expect HW 0x4 316*0Sstevel@tonic-gate */ 317*0Sstevel@tonic-gate 318*0Sstevel@tonic-gate /* 319*0Sstevel@tonic-gate * Only bit [7:0] are currently defined. Bits [2:0] 320*0Sstevel@tonic-gate * are the state, which should likely be in state active, 321*0Sstevel@tonic-gate * 100b. Bit three is 'recovery', which is not understood. 322*0Sstevel@tonic-gate * All other bits are reserved. 323*0Sstevel@tonic-gate */ 324*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_STATUS: 0x%llx\n", 325*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_STATUS)); 326*0Sstevel@tonic-gate 327*0Sstevel@tonic-gate /* 328*0Sstevel@tonic-gate * CSR_V TLU_PME_TURN_OFF_GENERATE Expect HW 0x0 329*0Sstevel@tonic-gate */ 330*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_PME_TURN_OFF_GENERATE: 0x%llx\n", 331*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE)); 332*0Sstevel@tonic-gate 333*0Sstevel@tonic-gate /* 334*0Sstevel@tonic-gate * CSR_V TLU_INGRESS_CREDITS_INITIAL Expect HW 0x10000200C0 335*0Sstevel@tonic-gate */ 336*0Sstevel@tonic-gate 337*0Sstevel@tonic-gate /* 338*0Sstevel@tonic-gate * Ingress credits initial register. Bits [39:32] should be 339*0Sstevel@tonic-gate * 0x10, bits [19:12] should be 0x20, and bits [11:0] should 340*0Sstevel@tonic-gate * be 0xC0. These are the reset values, and should be set by 341*0Sstevel@tonic-gate * HW. 342*0Sstevel@tonic-gate */ 343*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_INGRESS_CREDITS_INITIAL: 0x%llx\n", 344*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_INGRESS_CREDITS_INITIAL)); 345*0Sstevel@tonic-gate 346*0Sstevel@tonic-gate /* 347*0Sstevel@tonic-gate * CSR_V TLU_DIAGNOSTIC Expect HW 0x0 348*0Sstevel@tonic-gate */ 349*0Sstevel@tonic-gate 350*0Sstevel@tonic-gate /* 351*0Sstevel@tonic-gate * Diagnostic register - always zero unless we are debugging. 352*0Sstevel@tonic-gate */ 353*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DIAGNOSTIC: 0x%llx\n", 354*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DIAGNOSTIC)); 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate /* 357*0Sstevel@tonic-gate * CSR_V TLU_EGRESS_CREDITS_CONSUMED Expect HW 0x0 358*0Sstevel@tonic-gate */ 359*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDITS_CONSUMED: 0x%llx\n", 360*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_EGRESS_CREDITS_CONSUMED)); 361*0Sstevel@tonic-gate 362*0Sstevel@tonic-gate /* 363*0Sstevel@tonic-gate * CSR_V TLU_EGRESS_CREDIT_LIMIT Expect HW 0x0 364*0Sstevel@tonic-gate */ 365*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_CREDIT_LIMIT: 0x%llx\n", 366*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_EGRESS_CREDIT_LIMIT)); 367*0Sstevel@tonic-gate 368*0Sstevel@tonic-gate /* 369*0Sstevel@tonic-gate * CSR_V TLU_EGRESS_RETRY_BUFFER Expect HW 0x0 370*0Sstevel@tonic-gate */ 371*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_EGRESS_RETRY_BUFFER: 0x%llx\n", 372*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_EGRESS_RETRY_BUFFER)); 373*0Sstevel@tonic-gate 374*0Sstevel@tonic-gate /* 375*0Sstevel@tonic-gate * CSR_V TLU_INGRESS_CREDITS_ALLOCATED Expected HW 0x0 376*0Sstevel@tonic-gate */ 377*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 378*0Sstevel@tonic-gate "tlu_init - TLU_INGRESS_CREDITS_ALLOCATED: 0x%llx\n", 379*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_INGRESS_CREDITS_ALLOCATED)); 380*0Sstevel@tonic-gate 381*0Sstevel@tonic-gate /* 382*0Sstevel@tonic-gate * CSR_V TLU_INGRESS_CREDITS_RECEIVED Expected HW 0x0 383*0Sstevel@tonic-gate */ 384*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 385*0Sstevel@tonic-gate "tlu_init - TLU_INGRESS_CREDITS_RECEIVED: 0x%llx\n", 386*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_INGRESS_CREDITS_RECEIVED)); 387*0Sstevel@tonic-gate 388*0Sstevel@tonic-gate /* 389*0Sstevel@tonic-gate * CSR_V TLU_OTHER_EVENT_LOG_ENABLE Expected HW 0x7FF0F 390*0Sstevel@tonic-gate */ 391*0Sstevel@tonic-gate 392*0Sstevel@tonic-gate /* 393*0Sstevel@tonic-gate * First of a 'guilty five'. Problem now is that the orde 394*0Sstevel@tonic-gate * seems to different - some are log enable first then 395*0Sstevel@tonic-gate * interrupt enable, others are have them reversed. For 396*0Sstevel@tonic-gate * now I'll do them independently before creating a common 397*0Sstevel@tonic-gate * framework for them all. 398*0Sstevel@tonic-gate */ 399*0Sstevel@tonic-gate 400*0Sstevel@tonic-gate val = -1ull; 401*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_OTHER_EVENT_LOG_ENABLE, val); 402*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_OTHER_EVENT_LOG_ENABLE: 0x%llx\n", 403*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE)); 404*0Sstevel@tonic-gate 405*0Sstevel@tonic-gate /* 406*0Sstevel@tonic-gate * CSR_V TLU_OTHER_EVENT_INTERRUPT_ENABLE OBP 0x7FF0F0007FF0F 407*0Sstevel@tonic-gate */ 408*0Sstevel@tonic-gate 409*0Sstevel@tonic-gate /* 410*0Sstevel@tonic-gate * Second of five. Bits [55-32] enable secondary other event 411*0Sstevel@tonic-gate * interrupt enables, bit [23:0] enable primatry other event 412*0Sstevel@tonic-gate * interrupt enables. 413*0Sstevel@tonic-gate */ 414*0Sstevel@tonic-gate 415*0Sstevel@tonic-gate val = -1ull; 416*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE, val); 417*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 418*0Sstevel@tonic-gate "tlu_init - TLU_OTHER_EVENT_INTERRUPT_ENABLE: 0x%llx\n", 419*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE)); 420*0Sstevel@tonic-gate 421*0Sstevel@tonic-gate /* 422*0Sstevel@tonic-gate * CSR_V TLU_OTHER_EVENT_INTERRUPT_STATUS Expect HW 0x0 423*0Sstevel@tonic-gate */ 424*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 425*0Sstevel@tonic-gate "tlu_init - TLU_OTHER_EVENT_INTERRUPT_STATUS: 0x%llx\n", 426*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_STATUS)); 427*0Sstevel@tonic-gate 428*0Sstevel@tonic-gate /* 429*0Sstevel@tonic-gate * CSR_V TLU_OTHER_EVENT_STATUS_CLEAR Expect HW 0x0 430*0Sstevel@tonic-gate */ 431*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 432*0Sstevel@tonic-gate "tlu_init - TLU_OTHER_EVENT_STATUS_CLEAR: 0x%llx\n", 433*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_CLEAR)); 434*0Sstevel@tonic-gate 435*0Sstevel@tonic-gate /* 436*0Sstevel@tonic-gate * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 437*0Sstevel@tonic-gate */ 438*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 439*0Sstevel@tonic-gate "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 440*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG)); 441*0Sstevel@tonic-gate 442*0Sstevel@tonic-gate /* 443*0Sstevel@tonic-gate * CSR_V TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 444*0Sstevel@tonic-gate */ 445*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 446*0Sstevel@tonic-gate "tlu_init - TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 447*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG)); 448*0Sstevel@tonic-gate 449*0Sstevel@tonic-gate /* 450*0Sstevel@tonic-gate * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG Expect HW 0x0 451*0Sstevel@tonic-gate */ 452*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 453*0Sstevel@tonic-gate "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG: 0x%llx\n", 454*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG)); 455*0Sstevel@tonic-gate 456*0Sstevel@tonic-gate /* 457*0Sstevel@tonic-gate * CSR_V TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG Expect HW 0x0 458*0Sstevel@tonic-gate */ 459*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 460*0Sstevel@tonic-gate "tlu_init - TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG: 0x%llx\n", 461*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG)); 462*0Sstevel@tonic-gate 463*0Sstevel@tonic-gate /* 464*0Sstevel@tonic-gate * CSR_V TLU_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 465*0Sstevel@tonic-gate */ 466*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 467*0Sstevel@tonic-gate "tlu_init - TLU_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 468*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_SELECT)); 469*0Sstevel@tonic-gate 470*0Sstevel@tonic-gate /* 471*0Sstevel@tonic-gate * CSR_V TLU_PERFORMANCE_COUNTER_ZERO Expect HW 0x0 472*0Sstevel@tonic-gate */ 473*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 474*0Sstevel@tonic-gate "tlu_init - TLU_PERFORMANCE_COUNTER_ZERO: 0x%llx\n", 475*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ZERO)); 476*0Sstevel@tonic-gate 477*0Sstevel@tonic-gate /* 478*0Sstevel@tonic-gate * CSR_V TLU_PERFORMANCE_COUNTER_ONE Expect HW 0x0 479*0Sstevel@tonic-gate */ 480*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_ONE: 0x%llx\n", 481*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_ONE)); 482*0Sstevel@tonic-gate 483*0Sstevel@tonic-gate /* 484*0Sstevel@tonic-gate * CSR_V TLU_PERFORMANCE_COUNTER_TWO Expect HW 0x0 485*0Sstevel@tonic-gate */ 486*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_PERFORMANCE_COUNTER_TWO: 0x%llx\n", 487*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_PERFORMANCE_COUNTER_TWO)); 488*0Sstevel@tonic-gate 489*0Sstevel@tonic-gate /* 490*0Sstevel@tonic-gate * CSR_V TLU_DEBUG_SELECT_A Expect HW 0x0 491*0Sstevel@tonic-gate */ 492*0Sstevel@tonic-gate 493*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_A: 0x%llx\n", 494*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DEBUG_SELECT_A)); 495*0Sstevel@tonic-gate 496*0Sstevel@tonic-gate /* 497*0Sstevel@tonic-gate * CSR_V TLU_DEBUG_SELECT_B Expect HW 0x0 498*0Sstevel@tonic-gate */ 499*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DEBUG_SELECT_B: 0x%llx\n", 500*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DEBUG_SELECT_B)); 501*0Sstevel@tonic-gate 502*0Sstevel@tonic-gate /* 503*0Sstevel@tonic-gate * CSR_V TLU_DEVICE_CAPABILITIES Expect HW 0xFC2 504*0Sstevel@tonic-gate */ 505*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CAPABILITIES: 0x%llx\n", 506*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DEVICE_CAPABILITIES)); 507*0Sstevel@tonic-gate 508*0Sstevel@tonic-gate /* 509*0Sstevel@tonic-gate * CSR_V TLU_DEVICE_CONTROL Expect HW 0x0 510*0Sstevel@tonic-gate */ 511*0Sstevel@tonic-gate 512*0Sstevel@tonic-gate /* 513*0Sstevel@tonic-gate * Bits [14:12] are the Max Read Request Size, which is always 64 514*0Sstevel@tonic-gate * bytes which is 000b. Bits [7:5] are Max Payload Size, which 515*0Sstevel@tonic-gate * start at 128 bytes which is 000b. This may be revisited if 516*0Sstevel@tonic-gate * init_child finds greater values. 517*0Sstevel@tonic-gate */ 518*0Sstevel@tonic-gate val = 0x0ull; 519*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_DEVICE_CONTROL, val); 520*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_CONTROL: 0x%llx\n", 521*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DEVICE_CONTROL)); 522*0Sstevel@tonic-gate 523*0Sstevel@tonic-gate /* 524*0Sstevel@tonic-gate * CSR_V TLU_DEVICE_STATUS Expect HW 0x0 525*0Sstevel@tonic-gate */ 526*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_DEVICE_STATUS: 0x%llx\n", 527*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_DEVICE_STATUS)); 528*0Sstevel@tonic-gate 529*0Sstevel@tonic-gate /* 530*0Sstevel@tonic-gate * CSR_V TLU_LINK_CAPABILITIES Expect HW 0x15C81 531*0Sstevel@tonic-gate */ 532*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CAPABILITIES: 0x%llx\n", 533*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_LINK_CAPABILITIES)); 534*0Sstevel@tonic-gate 535*0Sstevel@tonic-gate /* 536*0Sstevel@tonic-gate * CSR_V TLU_LINK_CONTROL Expect OBP 0x40 537*0Sstevel@tonic-gate */ 538*0Sstevel@tonic-gate 539*0Sstevel@tonic-gate /* 540*0Sstevel@tonic-gate * The CLOCK bit should be set by OBP if the hardware dictates, 541*0Sstevel@tonic-gate * and if it is set then ASPM should be used since then L0s exit 542*0Sstevel@tonic-gate * latency should be lower than L1 exit latency. 543*0Sstevel@tonic-gate * 544*0Sstevel@tonic-gate * Note that we will not enable power management during bringup 545*0Sstevel@tonic-gate * since it has not been test and is creating some problems in 546*0Sstevel@tonic-gate * simulation. 547*0Sstevel@tonic-gate */ 548*0Sstevel@tonic-gate val = (1ull << TLU_LINK_CONTROL_CLOCK); 549*0Sstevel@tonic-gate 550*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_LINK_CONTROL, val); 551*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_CONTROL: 0x%llx\n", 552*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_LINK_CONTROL)); 553*0Sstevel@tonic-gate 554*0Sstevel@tonic-gate /* 555*0Sstevel@tonic-gate * CSR_V TLU_LINK_STATUS Expect OBP 0x1011 556*0Sstevel@tonic-gate */ 557*0Sstevel@tonic-gate 558*0Sstevel@tonic-gate /* 559*0Sstevel@tonic-gate * Not sure if HW or OBP will be setting this read only 560*0Sstevel@tonic-gate * register. Bit 12 is Clock, and it should always be 1 561*0Sstevel@tonic-gate * signifying that the component uses the same physical 562*0Sstevel@tonic-gate * clock as the platform. Bits [9:4] are for the width, 563*0Sstevel@tonic-gate * with the expected value above signifying a x1 width. 564*0Sstevel@tonic-gate * Bits [3:0] are the speed, with 1b signifying 2.5 Gb/s, 565*0Sstevel@tonic-gate * the only speed as yet supported by the PCI-E spec. 566*0Sstevel@tonic-gate */ 567*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_LINK_STATUS: 0x%llx\n", 568*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_LINK_STATUS)); 569*0Sstevel@tonic-gate 570*0Sstevel@tonic-gate /* 571*0Sstevel@tonic-gate * CSR_V TLU_SLOT_CAPABILITIES Expect OBP ??? 572*0Sstevel@tonic-gate */ 573*0Sstevel@tonic-gate 574*0Sstevel@tonic-gate /* 575*0Sstevel@tonic-gate * Power Limits for the slots. Will be platform 576*0Sstevel@tonic-gate * dependent, and OBP will need to set after consulting 577*0Sstevel@tonic-gate * with the HW guys. 578*0Sstevel@tonic-gate * 579*0Sstevel@tonic-gate * Bits [16:15] are power limit scale, which most likely 580*0Sstevel@tonic-gate * will be 0b signifying 1x. Bits [14:7] are the Set 581*0Sstevel@tonic-gate * Power Limit Value, which is a number which is multiplied 582*0Sstevel@tonic-gate * by the power limit scale to get the actual power limit. 583*0Sstevel@tonic-gate */ 584*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, "tlu_init - TLU_SLOT_CAPABILITIES: 0x%llx\n", 585*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_SLOT_CAPABILITIES)); 586*0Sstevel@tonic-gate 587*0Sstevel@tonic-gate /* 588*0Sstevel@tonic-gate * CSR_V TLU_UNCORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x17F011 589*0Sstevel@tonic-gate */ 590*0Sstevel@tonic-gate 591*0Sstevel@tonic-gate /* 592*0Sstevel@tonic-gate * First of a 'guilty five'. See note for Other Event Log. 593*0Sstevel@tonic-gate */ 594*0Sstevel@tonic-gate val = -1ull; 595*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE, val); 596*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 597*0Sstevel@tonic-gate "tlu_init - TLU_UNCORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 598*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE)); 599*0Sstevel@tonic-gate 600*0Sstevel@tonic-gate /* 601*0Sstevel@tonic-gate * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE 602*0Sstevel@tonic-gate * Expect Kernel 0x17F0110017F011 603*0Sstevel@tonic-gate */ 604*0Sstevel@tonic-gate 605*0Sstevel@tonic-gate /* 606*0Sstevel@tonic-gate * Second of a 'guilty five'. Needs the value in both bits [52:32] 607*0Sstevel@tonic-gate * and bits [20:0] for primary and secondary error interrupts. 608*0Sstevel@tonic-gate */ 609*0Sstevel@tonic-gate val = -1ull; 610*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE, val); 611*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 612*0Sstevel@tonic-gate "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 613*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE)); 614*0Sstevel@tonic-gate 615*0Sstevel@tonic-gate /* 616*0Sstevel@tonic-gate * CSR_V TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 617*0Sstevel@tonic-gate */ 618*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 619*0Sstevel@tonic-gate "tlu_init - TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 620*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_STATUS)); 621*0Sstevel@tonic-gate 622*0Sstevel@tonic-gate /* 623*0Sstevel@tonic-gate * CSR_V TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 624*0Sstevel@tonic-gate */ 625*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 626*0Sstevel@tonic-gate "tlu_init - TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 627*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR)); 628*0Sstevel@tonic-gate 629*0Sstevel@tonic-gate /* 630*0Sstevel@tonic-gate * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 631*0Sstevel@tonic-gate */ 632*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 633*0Sstevel@tonic-gate "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 634*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG)); 635*0Sstevel@tonic-gate 636*0Sstevel@tonic-gate /* 637*0Sstevel@tonic-gate * CSR_V TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 638*0Sstevel@tonic-gate */ 639*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 640*0Sstevel@tonic-gate "tlu_init - TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 641*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG)); 642*0Sstevel@tonic-gate 643*0Sstevel@tonic-gate /* 644*0Sstevel@tonic-gate * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG HW 0x0 645*0Sstevel@tonic-gate */ 646*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 647*0Sstevel@tonic-gate "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG: 0x%llx\n", 648*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG)); 649*0Sstevel@tonic-gate 650*0Sstevel@tonic-gate /* 651*0Sstevel@tonic-gate * CSR_V TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG HW 0x0 652*0Sstevel@tonic-gate */ 653*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 654*0Sstevel@tonic-gate "tlu_init - TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG: 0x%llx\n", 655*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG)); 656*0Sstevel@tonic-gate 657*0Sstevel@tonic-gate /* 658*0Sstevel@tonic-gate * CSR_V TLU_CORRECTABLE_ERROR_LOG_ENABLE Expect Kernel 0x11C1 659*0Sstevel@tonic-gate */ 660*0Sstevel@tonic-gate 661*0Sstevel@tonic-gate /* 662*0Sstevel@tonic-gate * Another set of 'guilty five'. 663*0Sstevel@tonic-gate */ 664*0Sstevel@tonic-gate 665*0Sstevel@tonic-gate val = -1ull; 666*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE, val); 667*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 668*0Sstevel@tonic-gate "tlu_init - TLU_CORRECTABLE_ERROR_LOG_ENABLE: 0x%llx\n", 669*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE)); 670*0Sstevel@tonic-gate 671*0Sstevel@tonic-gate /* 672*0Sstevel@tonic-gate * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE Kernel 0x11C1000011C1 673*0Sstevel@tonic-gate */ 674*0Sstevel@tonic-gate 675*0Sstevel@tonic-gate /* 676*0Sstevel@tonic-gate * Bits [44:32] for secondary error, bits [12:0] for primary errors. 677*0Sstevel@tonic-gate */ 678*0Sstevel@tonic-gate val = -1ull; 679*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE, val); 680*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 681*0Sstevel@tonic-gate "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE: 0x%llx\n", 682*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE)); 683*0Sstevel@tonic-gate 684*0Sstevel@tonic-gate /* 685*0Sstevel@tonic-gate * CSR_V TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS Expect HW 0x0 686*0Sstevel@tonic-gate */ 687*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 688*0Sstevel@tonic-gate "tlu_init - TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS: 0x%llx\n", 689*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_STATUS)); 690*0Sstevel@tonic-gate 691*0Sstevel@tonic-gate /* 692*0Sstevel@tonic-gate * CSR_V TLU_CORRECTABLE_ERROR_STATUS_CLEAR Expect HW 0x0 693*0Sstevel@tonic-gate */ 694*0Sstevel@tonic-gate DBG(DBG_TLU, NULL, 695*0Sstevel@tonic-gate "tlu_init - TLU_CORRECTABLE_ERROR_STATUS_CLEAR: 0x%llx\n", 696*0Sstevel@tonic-gate CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_CLEAR)); 697*0Sstevel@tonic-gate } 698*0Sstevel@tonic-gate 699*0Sstevel@tonic-gate static void 700*0Sstevel@tonic-gate lpu_init(caddr_t csr_base, pxu_t *pxu_p) 701*0Sstevel@tonic-gate { 702*0Sstevel@tonic-gate /* Variables used to set the ACKNAK Latency Timer and Replay Timer */ 703*0Sstevel@tonic-gate int link_width, max_payload; 704*0Sstevel@tonic-gate 705*0Sstevel@tonic-gate uint64_t val; 706*0Sstevel@tonic-gate 707*0Sstevel@tonic-gate /* 708*0Sstevel@tonic-gate * ACKNAK Latency Threshold Table. 709*0Sstevel@tonic-gate * See Fire PRM 1.0 sections 1.2.11.1, table 1-17. 710*0Sstevel@tonic-gate */ 711*0Sstevel@tonic-gate int fire10_acknak_timer_table[LINK_MAX_PKT_ARR_SIZE] 712*0Sstevel@tonic-gate [LINK_WIDTH_ARR_SIZE] = { 713*0Sstevel@tonic-gate {0xED, 0x76, 0x70, 0x58}, 714*0Sstevel@tonic-gate {0x1A0, 0x76, 0x6B, 0x61}, 715*0Sstevel@tonic-gate {0x22F, 0x9A, 0x6A, 0x6A}, 716*0Sstevel@tonic-gate {0x42F, 0x11A, 0x96, 0x96}, 717*0Sstevel@tonic-gate {0x82F, 0x21A, 0x116, 0x116}, 718*0Sstevel@tonic-gate {0x102F, 0x41A, 0x216, 0x216} 719*0Sstevel@tonic-gate }; 720*0Sstevel@tonic-gate 721*0Sstevel@tonic-gate /* 722*0Sstevel@tonic-gate * TxLink Replay Timer Latency Table 723*0Sstevel@tonic-gate * See Fire PRM 1.0 sections 1.2.11.2, table 1-18. 724*0Sstevel@tonic-gate */ 725*0Sstevel@tonic-gate int fire10_replay_timer_table[LINK_MAX_PKT_ARR_SIZE] 726*0Sstevel@tonic-gate [LINK_WIDTH_ARR_SIZE] = { 727*0Sstevel@tonic-gate {0x2C7, 0x108, 0xF6, 0xBD}, 728*0Sstevel@tonic-gate {0x4E0, 0x162, 0x141, 0xF1}, 729*0Sstevel@tonic-gate {0x68D, 0x1CE, 0x102, 0x102}, 730*0Sstevel@tonic-gate {0xC8D, 0x34E, 0x1C2, 0x1C2}, 731*0Sstevel@tonic-gate {0x188D, 0x64E, 0x342, 0x342}, 732*0Sstevel@tonic-gate {0x308D, 0xC4E, 0x642, 0x642} 733*0Sstevel@tonic-gate }; 734*0Sstevel@tonic-gate 735*0Sstevel@tonic-gate /* 736*0Sstevel@tonic-gate * ACKNAK Latency Threshold Table. 737*0Sstevel@tonic-gate * See Fire PRM 2.0 section 1.2.12.2, table 1-17. 738*0Sstevel@tonic-gate */ 739*0Sstevel@tonic-gate int acknak_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE] = { 740*0Sstevel@tonic-gate {0xED, 0x49, 0x43, 0x30}, 741*0Sstevel@tonic-gate {0x1A0, 0x76, 0x6B, 0x48}, 742*0Sstevel@tonic-gate {0x22F, 0x9A, 0x56, 0x56}, 743*0Sstevel@tonic-gate {0x42F, 0x11A, 0x96, 0x96}, 744*0Sstevel@tonic-gate {0x82F, 0x21A, 0x116, 0x116}, 745*0Sstevel@tonic-gate {0x102F, 0x41A, 0x216, 0x216} 746*0Sstevel@tonic-gate }; 747*0Sstevel@tonic-gate 748*0Sstevel@tonic-gate /* 749*0Sstevel@tonic-gate * TxLink Replay Timer Latency Table 750*0Sstevel@tonic-gate * See Fire PRM 2.0 sections 1.2.12.3, table 1-18. 751*0Sstevel@tonic-gate */ 752*0Sstevel@tonic-gate int replay_timer_table[LINK_MAX_PKT_ARR_SIZE][LINK_WIDTH_ARR_SIZE] = { 753*0Sstevel@tonic-gate {0x379, 0x112, 0xFC, 0xB4}, 754*0Sstevel@tonic-gate {0x618, 0x1BA, 0x192, 0x10E}, 755*0Sstevel@tonic-gate {0x831, 0x242, 0x143, 0x143}, 756*0Sstevel@tonic-gate {0xFB1, 0x422, 0x233, 0x233}, 757*0Sstevel@tonic-gate {0x1EB0, 0x7E1, 0x412, 0x412}, 758*0Sstevel@tonic-gate {0x3CB0, 0xF61, 0x7D2, 0x7D2} 759*0Sstevel@tonic-gate }; 760*0Sstevel@tonic-gate /* 761*0Sstevel@tonic-gate * Get the Link Width. See table above LINK_WIDTH_ARR_SIZE #define 762*0Sstevel@tonic-gate * Only Link Widths of x1, x4, and x8 are supported. 763*0Sstevel@tonic-gate * If any width is reported other than x8, set default to x8. 764*0Sstevel@tonic-gate */ 765*0Sstevel@tonic-gate link_width = CSR_FR(csr_base, TLU_LINK_STATUS, WIDTH); 766*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - Link Width: x%d\n", link_width); 767*0Sstevel@tonic-gate 768*0Sstevel@tonic-gate /* 769*0Sstevel@tonic-gate * Convert link_width to match timer array configuration. 770*0Sstevel@tonic-gate */ 771*0Sstevel@tonic-gate switch (link_width) { 772*0Sstevel@tonic-gate case 1: 773*0Sstevel@tonic-gate link_width = 0; 774*0Sstevel@tonic-gate break; 775*0Sstevel@tonic-gate case 4: 776*0Sstevel@tonic-gate link_width = 1; 777*0Sstevel@tonic-gate break; 778*0Sstevel@tonic-gate case 8: 779*0Sstevel@tonic-gate link_width = 2; 780*0Sstevel@tonic-gate break; 781*0Sstevel@tonic-gate case 16: 782*0Sstevel@tonic-gate link_width = 3; 783*0Sstevel@tonic-gate break; 784*0Sstevel@tonic-gate default: 785*0Sstevel@tonic-gate link_width = 0; 786*0Sstevel@tonic-gate } 787*0Sstevel@tonic-gate 788*0Sstevel@tonic-gate /* 789*0Sstevel@tonic-gate * Get the Max Payload Size. 790*0Sstevel@tonic-gate * See table above LINK_MAX_PKT_ARR_SIZE #define 791*0Sstevel@tonic-gate */ 792*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 793*0Sstevel@tonic-gate max_payload = CSR_FR(csr_base, 794*0Sstevel@tonic-gate FIRE10_LPU_LINK_LAYER_CONFIG, MAX_PAYLOAD); 795*0Sstevel@tonic-gate } else { 796*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 797*0Sstevel@tonic-gate max_payload = ((CSR_FR(csr_base, TLU_CONTROL, CONFIG) & 798*0Sstevel@tonic-gate TLU_CONTROL_MPS_MASK) >> TLU_CONTROL_MPS_SHIFT); 799*0Sstevel@tonic-gate } 800*0Sstevel@tonic-gate 801*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - May Payload: %d\n", 802*0Sstevel@tonic-gate (0x80 << max_payload)); 803*0Sstevel@tonic-gate 804*0Sstevel@tonic-gate /* Make sure the packet size is not greater than 4096 */ 805*0Sstevel@tonic-gate max_payload = (max_payload >= LINK_MAX_PKT_ARR_SIZE) ? 806*0Sstevel@tonic-gate (LINK_MAX_PKT_ARR_SIZE - 1) : max_payload; 807*0Sstevel@tonic-gate 808*0Sstevel@tonic-gate /* 809*0Sstevel@tonic-gate * CSR_V LPU_ID Expect HW 0x0 810*0Sstevel@tonic-gate */ 811*0Sstevel@tonic-gate 812*0Sstevel@tonic-gate /* 813*0Sstevel@tonic-gate * This register has link id, phy id and gigablaze id. 814*0Sstevel@tonic-gate * Should be set by HW. 815*0Sstevel@tonic-gate */ 816*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_ID: 0x%llx\n", 817*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_ID)); 818*0Sstevel@tonic-gate 819*0Sstevel@tonic-gate /* 820*0Sstevel@tonic-gate * CSR_V LPU_RESET Expect Kernel 0x0 821*0Sstevel@tonic-gate */ 822*0Sstevel@tonic-gate 823*0Sstevel@tonic-gate /* 824*0Sstevel@tonic-gate * No reason to have any reset bits high until an error is 825*0Sstevel@tonic-gate * detected on the link. 826*0Sstevel@tonic-gate */ 827*0Sstevel@tonic-gate val = 0ull; 828*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_RESET, val); 829*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RESET: 0x%llx\n", 830*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RESET)); 831*0Sstevel@tonic-gate 832*0Sstevel@tonic-gate /* 833*0Sstevel@tonic-gate * CSR_V LPU_DEBUG_STATUS Expect HW 0x0 834*0Sstevel@tonic-gate */ 835*0Sstevel@tonic-gate 836*0Sstevel@tonic-gate /* 837*0Sstevel@tonic-gate * Bits [15:8] are Debug B, and bit [7:0] are Debug A. 838*0Sstevel@tonic-gate * They are read-only. What do the 8 bits mean, and 839*0Sstevel@tonic-gate * how do they get set if they are read only? 840*0Sstevel@tonic-gate */ 841*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_STATUS: 0x%llx\n", 842*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_DEBUG_STATUS)); 843*0Sstevel@tonic-gate 844*0Sstevel@tonic-gate /* 845*0Sstevel@tonic-gate * CSR_V LPU_DEBUG_CONFIG Expect Kernel 0x0 846*0Sstevel@tonic-gate */ 847*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_DEBUG_CONFIG: 0x%llx\n", 848*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_DEBUG_CONFIG)); 849*0Sstevel@tonic-gate 850*0Sstevel@tonic-gate /* 851*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONTROL Expect HW 0x0 852*0Sstevel@tonic-gate */ 853*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONTROL: 0x%llx\n", 854*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONTROL)); 855*0Sstevel@tonic-gate 856*0Sstevel@tonic-gate /* 857*0Sstevel@tonic-gate * CSR_V LPU_LINK_STATUS Expect HW 0x101 858*0Sstevel@tonic-gate */ 859*0Sstevel@tonic-gate 860*0Sstevel@tonic-gate /* 861*0Sstevel@tonic-gate * This register has bits [9:4] for link width, and the 862*0Sstevel@tonic-gate * default 0x10, means a width of x16. The problem is 863*0Sstevel@tonic-gate * this width is not supported according to the TLU 864*0Sstevel@tonic-gate * link status register. 865*0Sstevel@tonic-gate */ 866*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_STATUS: 0x%llx\n", 867*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_STATUS)); 868*0Sstevel@tonic-gate 869*0Sstevel@tonic-gate /* 870*0Sstevel@tonic-gate * CSR_V LPU_INTERRUPT_STATUS Expect HW 0x0 871*0Sstevel@tonic-gate */ 872*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_STATUS: 0x%llx\n", 873*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_INTERRUPT_STATUS)); 874*0Sstevel@tonic-gate 875*0Sstevel@tonic-gate /* 876*0Sstevel@tonic-gate * CSR_V LPU_INTERRUPT_MASK Expect HW 0x0 877*0Sstevel@tonic-gate */ 878*0Sstevel@tonic-gate val = 0ull; 879*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_INTERRUPT_MASK, val); 880*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_INTERRUPT_MASK: 0x%llx\n", 881*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_INTERRUPT_MASK)); 882*0Sstevel@tonic-gate 883*0Sstevel@tonic-gate /* 884*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER_SELECT Expect HW 0x0 885*0Sstevel@tonic-gate */ 886*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 887*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_SELECT: 0x%llx\n", 888*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_SELECT)); 889*0Sstevel@tonic-gate 890*0Sstevel@tonic-gate /* 891*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER_CONTROL Expect HW 0x0 892*0Sstevel@tonic-gate */ 893*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 894*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER_CONTROL: 0x%llx\n", 895*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER_CONTROL)); 896*0Sstevel@tonic-gate 897*0Sstevel@tonic-gate /* 898*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER1 Expect HW 0x0 899*0Sstevel@tonic-gate */ 900*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 901*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1: 0x%llx\n", 902*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1)); 903*0Sstevel@tonic-gate 904*0Sstevel@tonic-gate /* 905*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER1_TEST Expect HW 0x0 906*0Sstevel@tonic-gate */ 907*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 908*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER1_TEST: 0x%llx\n", 909*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER1_TEST)); 910*0Sstevel@tonic-gate 911*0Sstevel@tonic-gate /* 912*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER2 Expect HW 0x0 913*0Sstevel@tonic-gate */ 914*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 915*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2: 0x%llx\n", 916*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2)); 917*0Sstevel@tonic-gate 918*0Sstevel@tonic-gate /* 919*0Sstevel@tonic-gate * CSR_V LPU_LINK_PERFORMANCE_COUNTER2_TEST Expect HW 0x0 920*0Sstevel@tonic-gate */ 921*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 922*0Sstevel@tonic-gate "lpu_init - LPU_LINK_PERFORMANCE_COUNTER2_TEST: 0x%llx\n", 923*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_PERFORMANCE_COUNTER2_TEST)); 924*0Sstevel@tonic-gate 925*0Sstevel@tonic-gate /* 926*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_CONFIG Expect HW 0x100 927*0Sstevel@tonic-gate */ 928*0Sstevel@tonic-gate 929*0Sstevel@tonic-gate /* 930*0Sstevel@tonic-gate * This is another place where Max Payload can be set, 931*0Sstevel@tonic-gate * this time for the link layer. It will be set to 932*0Sstevel@tonic-gate * 128B, which is the default, but this will need to 933*0Sstevel@tonic-gate * be revisited. 934*0Sstevel@tonic-gate */ 935*0Sstevel@tonic-gate val = (1ull << LPU_LINK_LAYER_CONFIG_VC0_EN); 936*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LINK_LAYER_CONFIG, val); 937*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_CONFIG: 0x%llx\n", 938*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_LAYER_CONFIG)); 939*0Sstevel@tonic-gate 940*0Sstevel@tonic-gate /* 941*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_STATUS Expect OBP 0x5 942*0Sstevel@tonic-gate */ 943*0Sstevel@tonic-gate 944*0Sstevel@tonic-gate /* 945*0Sstevel@tonic-gate * Another R/W status register. Bit 3, DL up Status, will 946*0Sstevel@tonic-gate * be set high. The link state machine status bits [2:0] 947*0Sstevel@tonic-gate * are set to 0x1, but the status bits are not defined in the 948*0Sstevel@tonic-gate * PRM. What does 0x1 mean, what others values are possible 949*0Sstevel@tonic-gate * and what are thier meanings? 950*0Sstevel@tonic-gate * 951*0Sstevel@tonic-gate * This register has been giving us problems in simulation. 952*0Sstevel@tonic-gate * It has been mentioned that software should not program 953*0Sstevel@tonic-gate * any registers with WE bits except during debug. So 954*0Sstevel@tonic-gate * this register will no longer be programmed. 955*0Sstevel@tonic-gate */ 956*0Sstevel@tonic-gate 957*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LINK_LAYER_STATUS: 0x%llx\n", 958*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_LAYER_STATUS)); 959*0Sstevel@tonic-gate 960*0Sstevel@tonic-gate /* 961*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS Expect HW 0x0 962*0Sstevel@tonic-gate */ 963*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 964*0Sstevel@tonic-gate "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 965*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS)); 966*0Sstevel@tonic-gate 967*0Sstevel@tonic-gate /* 968*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 969*0Sstevel@tonic-gate */ 970*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 971*0Sstevel@tonic-gate "lpu_init - LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 972*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_AND_STATUS_TEST)); 973*0Sstevel@tonic-gate 974*0Sstevel@tonic-gate /* 975*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_INTERRUPT_MASK Expect OBP 0x0 976*0Sstevel@tonic-gate */ 977*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 978*0Sstevel@tonic-gate "lpu_init - LPU_LINK_LAYER_INTERRUPT_MASK: 0x%llx\n", 979*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LINK_LAYER_INTERRUPT_MASK)); 980*0Sstevel@tonic-gate 981*0Sstevel@tonic-gate /* 982*0Sstevel@tonic-gate * CSR_V LPU_FLOW_CONTROL_UPDATE_CONTROL Expect OBP 0x7 983*0Sstevel@tonic-gate */ 984*0Sstevel@tonic-gate 985*0Sstevel@tonic-gate /* 986*0Sstevel@tonic-gate * The PRM says that only the first two bits will be set 987*0Sstevel@tonic-gate * high by default, which will enable flow control for 988*0Sstevel@tonic-gate * posted and non-posted updates, but NOT completetion 989*0Sstevel@tonic-gate * updates. 990*0Sstevel@tonic-gate */ 991*0Sstevel@tonic-gate val = (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_NP_EN) | 992*0Sstevel@tonic-gate (1ull << LPU_FLOW_CONTROL_UPDATE_CONTROL_FC0_U_P_EN); 993*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL, val); 994*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 995*0Sstevel@tonic-gate "lpu_init - LPU_FLOW_CONTROL_UPDATE_CONTROL: 0x%llx\n", 996*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_FLOW_CONTROL_UPDATE_CONTROL)); 997*0Sstevel@tonic-gate 998*0Sstevel@tonic-gate /* 999*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE 1000*0Sstevel@tonic-gate * Expect OBP 0x1D4C 1001*0Sstevel@tonic-gate */ 1002*0Sstevel@tonic-gate 1003*0Sstevel@tonic-gate /* 1004*0Sstevel@tonic-gate * This should be set by OBP. We'll check to make sure. 1005*0Sstevel@tonic-gate */ 1006*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1007*0Sstevel@tonic-gate "lpu_init - " 1008*0Sstevel@tonic-gate "LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE: 0x%llx\n", 1009*0Sstevel@tonic-gate CSR_XR(csr_base, 1010*0Sstevel@tonic-gate LPU_LINK_LAYER_FLOW_CONTROL_UPDATE_TIMEOUT_VALUE)); 1011*0Sstevel@tonic-gate 1012*0Sstevel@tonic-gate /* 1013*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0 Expect OBP ??? 1014*0Sstevel@tonic-gate */ 1015*0Sstevel@tonic-gate 1016*0Sstevel@tonic-gate /* 1017*0Sstevel@tonic-gate * This register has Flow Control Update Timer values for 1018*0Sstevel@tonic-gate * non-posted and posted requests, bits [30:16] and bits 1019*0Sstevel@tonic-gate * [14:0], respectively. These are read-only to SW so 1020*0Sstevel@tonic-gate * either HW or OBP needs to set them. 1021*0Sstevel@tonic-gate */ 1022*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1023*0Sstevel@tonic-gate "lpu_init - " 1024*0Sstevel@tonic-gate "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0: 0x%llx\n", 1025*0Sstevel@tonic-gate CSR_XR(csr_base, 1026*0Sstevel@tonic-gate LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER0)); 1027*0Sstevel@tonic-gate 1028*0Sstevel@tonic-gate /* 1029*0Sstevel@tonic-gate * CSR_V LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1 Expect OBP ??? 1030*0Sstevel@tonic-gate */ 1031*0Sstevel@tonic-gate 1032*0Sstevel@tonic-gate /* 1033*0Sstevel@tonic-gate * Same as timer0 register above, except for bits [14:0] 1034*0Sstevel@tonic-gate * have the timer values for completetions. Read-only to 1035*0Sstevel@tonic-gate * SW; OBP or HW need to set it. 1036*0Sstevel@tonic-gate */ 1037*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1038*0Sstevel@tonic-gate "lpu_init - " 1039*0Sstevel@tonic-gate "LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1: 0x%llx\n", 1040*0Sstevel@tonic-gate CSR_XR(csr_base, 1041*0Sstevel@tonic-gate LPU_LINK_LAYER_VC0_FLOW_CONTROL_UPDATE_TIMER1)); 1042*0Sstevel@tonic-gate 1043*0Sstevel@tonic-gate /* 1044*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD 1045*0Sstevel@tonic-gate */ 1046*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 1047*0Sstevel@tonic-gate val = fire10_acknak_timer_table[max_payload][link_width]; 1048*0Sstevel@tonic-gate } else { 1049*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 1050*0Sstevel@tonic-gate val = acknak_timer_table[max_payload][link_width]; 1051*0Sstevel@tonic-gate } 1052*0Sstevel@tonic-gate 1053*0Sstevel@tonic-gate CSR_XS(csr_base, 1054*0Sstevel@tonic-gate LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD, val); 1055*0Sstevel@tonic-gate 1056*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - " 1057*0Sstevel@tonic-gate "LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD: 0x%llx\n", 1058*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_FREQUENT_NAK_LATENCY_TIMER_THRESHOLD)); 1059*0Sstevel@tonic-gate 1060*0Sstevel@tonic-gate /* 1061*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_ACKNAK_LATENCY_TIMER Expect HW 0x0 1062*0Sstevel@tonic-gate */ 1063*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1064*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_ACKNAK_LATENCY_TIMER: 0x%llx\n", 1065*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_ACKNAK_LATENCY_TIMER)); 1066*0Sstevel@tonic-gate 1067*0Sstevel@tonic-gate /* 1068*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_REPLAY_TIMER_THRESHOLD 1069*0Sstevel@tonic-gate */ 1070*0Sstevel@tonic-gate if (pxu_p->chip_id == FIRE_VER_10) { 1071*0Sstevel@tonic-gate val = fire10_replay_timer_table[max_payload][link_width]; 1072*0Sstevel@tonic-gate } else { 1073*0Sstevel@tonic-gate /* Default case is FIRE2.0 */ 1074*0Sstevel@tonic-gate val = replay_timer_table[max_payload][link_width]; 1075*0Sstevel@tonic-gate } 1076*0Sstevel@tonic-gate 1077*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD, val); 1078*0Sstevel@tonic-gate 1079*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1080*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_REPLAY_TIMER_THRESHOLD: 0x%llx\n", 1081*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER_THRESHOLD)); 1082*0Sstevel@tonic-gate 1083*0Sstevel@tonic-gate /* 1084*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_REPLAY_TIMER Expect HW 0x0 1085*0Sstevel@tonic-gate */ 1086*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_REPLAY_TIMER: 0x%llx\n", 1087*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_REPLAY_TIMER)); 1088*0Sstevel@tonic-gate 1089*0Sstevel@tonic-gate /* 1090*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_REPLAY_NUMBER_STATUS Expect OBP 0x3 1091*0Sstevel@tonic-gate */ 1092*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1093*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_REPLAY_NUMBER_STATUS: 0x%llx\n", 1094*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_REPLAY_NUMBER_STATUS)); 1095*0Sstevel@tonic-gate 1096*0Sstevel@tonic-gate /* 1097*0Sstevel@tonic-gate * CSR_V LPU_REPLAY_BUFFER_MAX_ADDRESS Expect OBP 0xB3F 1098*0Sstevel@tonic-gate */ 1099*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1100*0Sstevel@tonic-gate "lpu_init - LPU_REPLAY_BUFFER_MAX_ADDRESS: 0x%llx\n", 1101*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_REPLAY_BUFFER_MAX_ADDRESS)); 1102*0Sstevel@tonic-gate 1103*0Sstevel@tonic-gate /* 1104*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_RETRY_FIFO_POINTER Expect OBP 0xFFFF0000 1105*0Sstevel@tonic-gate */ 1106*0Sstevel@tonic-gate val = ((LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT << 1107*0Sstevel@tonic-gate LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR) | 1108*0Sstevel@tonic-gate (LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT << 1109*0Sstevel@tonic-gate LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR)); 1110*0Sstevel@tonic-gate 1111*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER, val); 1112*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1113*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_RETRY_FIFO_POINTER: 0x%llx\n", 1114*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_POINTER)); 1115*0Sstevel@tonic-gate 1116*0Sstevel@tonic-gate /* 1117*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_RETRY_FIFO_R_W_POINTER Expect OBP 0x0 1118*0Sstevel@tonic-gate */ 1119*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1120*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_RETRY_FIFO_R_W_POINTER: 0x%llx\n", 1121*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_R_W_POINTER)); 1122*0Sstevel@tonic-gate 1123*0Sstevel@tonic-gate /* 1124*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_RETRY_FIFO_CREDIT Expect HW 0x1580 1125*0Sstevel@tonic-gate */ 1126*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1127*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_RETRY_FIFO_CREDIT: 0x%llx\n", 1128*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_RETRY_FIFO_CREDIT)); 1129*0Sstevel@tonic-gate 1130*0Sstevel@tonic-gate /* 1131*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_COUNTER Expect OBP 0xFFF0000 1132*0Sstevel@tonic-gate */ 1133*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_SEQUENCE_COUNTER: 0x%llx\n", 1134*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNTER)); 1135*0Sstevel@tonic-gate 1136*0Sstevel@tonic-gate /* 1137*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER Expect HW 0xFFF 1138*0Sstevel@tonic-gate */ 1139*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1140*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER: 0x%llx\n", 1141*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_ACK_SENT_SEQUENCE_NUMBER)); 1142*0Sstevel@tonic-gate 1143*0Sstevel@tonic-gate /* 1144*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR Expect OBP 0x157 1145*0Sstevel@tonic-gate */ 1146*0Sstevel@tonic-gate 1147*0Sstevel@tonic-gate /* 1148*0Sstevel@tonic-gate * Test only register. Will not be programmed. 1149*0Sstevel@tonic-gate */ 1150*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1151*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR: 0x%llx\n", 1152*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR)); 1153*0Sstevel@tonic-gate 1154*0Sstevel@tonic-gate /* 1155*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS Expect HW 0xFFF0000 1156*0Sstevel@tonic-gate */ 1157*0Sstevel@tonic-gate 1158*0Sstevel@tonic-gate /* 1159*0Sstevel@tonic-gate * Test only register. Will not be programmed. 1160*0Sstevel@tonic-gate */ 1161*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1162*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS: 0x%llx\n", 1163*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS)); 1164*0Sstevel@tonic-gate 1165*0Sstevel@tonic-gate /* 1166*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS Expect HW 0x0 1167*0Sstevel@tonic-gate */ 1168*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1169*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS: 0x%llx\n", 1170*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_COUNT_R_W_POINTERS)); 1171*0Sstevel@tonic-gate 1172*0Sstevel@tonic-gate /* 1173*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_TEST_CONTROL Expect HW 0x0 1174*0Sstevel@tonic-gate */ 1175*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_TEST_CONTROL: 0x%llx\n", 1176*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_TEST_CONTROL)); 1177*0Sstevel@tonic-gate 1178*0Sstevel@tonic-gate /* 1179*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_ADDRESS_CONTROL Expect HW 0x0 1180*0Sstevel@tonic-gate */ 1181*0Sstevel@tonic-gate 1182*0Sstevel@tonic-gate /* 1183*0Sstevel@tonic-gate * Test only register. Will not be programmed. 1184*0Sstevel@tonic-gate */ 1185*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1186*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_ADDRESS_CONTROL: 0x%llx\n", 1187*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_ADDRESS_CONTROL)); 1188*0Sstevel@tonic-gate 1189*0Sstevel@tonic-gate /* 1190*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD0 Expect HW 0x0 1191*0Sstevel@tonic-gate */ 1192*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1193*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD0: 0x%llx\n", 1194*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD0)); 1195*0Sstevel@tonic-gate 1196*0Sstevel@tonic-gate /* 1197*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD1 Expect HW 0x0 1198*0Sstevel@tonic-gate */ 1199*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1200*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD1: 0x%llx\n", 1201*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD1)); 1202*0Sstevel@tonic-gate 1203*0Sstevel@tonic-gate /* 1204*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD2 Expect HW 0x0 1205*0Sstevel@tonic-gate */ 1206*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1207*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD2: 0x%llx\n", 1208*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD2)); 1209*0Sstevel@tonic-gate 1210*0Sstevel@tonic-gate /* 1211*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD3 Expect HW 0x0 1212*0Sstevel@tonic-gate */ 1213*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1214*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD3: 0x%llx\n", 1215*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD3)); 1216*0Sstevel@tonic-gate 1217*0Sstevel@tonic-gate /* 1218*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_MEMORY_DATA_LOAD4 Expect HW 0x0 1219*0Sstevel@tonic-gate */ 1220*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1221*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_MEMORY_DATA_LOAD4: 0x%llx\n", 1222*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_MEMORY_DATA_LOAD4)); 1223*0Sstevel@tonic-gate 1224*0Sstevel@tonic-gate /* 1225*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_RETRY_DATA_COUNT Expect HW 0x0 1226*0Sstevel@tonic-gate */ 1227*0Sstevel@tonic-gate 1228*0Sstevel@tonic-gate /* 1229*0Sstevel@tonic-gate * Test only register. Will not be programmed. 1230*0Sstevel@tonic-gate */ 1231*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TXLINK_RETRY_DATA_COUNT: 0x%llx\n", 1232*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_RETRY_DATA_COUNT)); 1233*0Sstevel@tonic-gate 1234*0Sstevel@tonic-gate /* 1235*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_COUNT Expect HW 0x0 1236*0Sstevel@tonic-gate */ 1237*0Sstevel@tonic-gate 1238*0Sstevel@tonic-gate /* 1239*0Sstevel@tonic-gate * Test only register. Will not be programmed. 1240*0Sstevel@tonic-gate */ 1241*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1242*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_COUNT: 0x%llx\n", 1243*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_COUNT)); 1244*0Sstevel@tonic-gate 1245*0Sstevel@tonic-gate /* 1246*0Sstevel@tonic-gate * CSR_V LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA Expect HW 0x0 1247*0Sstevel@tonic-gate */ 1248*0Sstevel@tonic-gate 1249*0Sstevel@tonic-gate /* 1250*0Sstevel@tonic-gate * Test only register. 1251*0Sstevel@tonic-gate */ 1252*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1253*0Sstevel@tonic-gate "lpu_init - LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA: 0x%llx\n", 1254*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TXLINK_SEQUENCE_BUFFER_BOTTOM_DATA)); 1255*0Sstevel@tonic-gate 1256*0Sstevel@tonic-gate /* 1257*0Sstevel@tonic-gate * CSR_V LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER Expect HW 0x0 1258*0Sstevel@tonic-gate */ 1259*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - " 1260*0Sstevel@tonic-gate "LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER: 0x%llx\n", 1261*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RXLINK_NEXT_RECEIVE_SEQUENCE_1_COUNTER)); 1262*0Sstevel@tonic-gate 1263*0Sstevel@tonic-gate /* 1264*0Sstevel@tonic-gate * CSR_V LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED Expect HW 0x0 1265*0Sstevel@tonic-gate */ 1266*0Sstevel@tonic-gate 1267*0Sstevel@tonic-gate /* 1268*0Sstevel@tonic-gate * test only register. 1269*0Sstevel@tonic-gate */ 1270*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1271*0Sstevel@tonic-gate "lpu_init - LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED: 0x%llx\n", 1272*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RXLINK_UNSUPPORTED_DLLP_RECEIVED)); 1273*0Sstevel@tonic-gate 1274*0Sstevel@tonic-gate /* 1275*0Sstevel@tonic-gate * CSR_V LPU_RXLINK_TEST_CONTROL Expect HW 0x0 1276*0Sstevel@tonic-gate */ 1277*0Sstevel@tonic-gate 1278*0Sstevel@tonic-gate /* 1279*0Sstevel@tonic-gate * test only register. 1280*0Sstevel@tonic-gate */ 1281*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RXLINK_TEST_CONTROL: 0x%llx\n", 1282*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RXLINK_TEST_CONTROL)); 1283*0Sstevel@tonic-gate 1284*0Sstevel@tonic-gate /* 1285*0Sstevel@tonic-gate * CSR_V LPU_PHYSICAL_LAYER_CONFIGURATION Expect HW 0x10 1286*0Sstevel@tonic-gate */ 1287*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1288*0Sstevel@tonic-gate "lpu_init - LPU_PHYSICAL_LAYER_CONFIGURATION: 0x%llx\n", 1289*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_PHYSICAL_LAYER_CONFIGURATION)); 1290*0Sstevel@tonic-gate 1291*0Sstevel@tonic-gate /* 1292*0Sstevel@tonic-gate * CSR_V LPU_PHY_LAYER_STATUS Expect HW 0x0 1293*0Sstevel@tonic-gate */ 1294*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_LAYER_STATUS: 0x%llx\n", 1295*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_PHY_LAYER_STATUS)); 1296*0Sstevel@tonic-gate 1297*0Sstevel@tonic-gate /* 1298*0Sstevel@tonic-gate * CSR_V LPU_PHY_LAYER_INTERRUPT_AND_STATUS Expect HW 0x0 1299*0Sstevel@tonic-gate */ 1300*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1301*0Sstevel@tonic-gate "lpu_init - LPU_PHY_LAYER_INTERRUPT_AND_STATUS: 0x%llx\n", 1302*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_PHY_LAYER_INTERRUPT_AND_STATUS)); 1303*0Sstevel@tonic-gate 1304*0Sstevel@tonic-gate /* 1305*0Sstevel@tonic-gate * CSR_V LPU_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1306*0Sstevel@tonic-gate */ 1307*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1308*0Sstevel@tonic-gate "lpu_init - LPU_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1309*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_PHY_INTERRUPT_AND_STATUS_TEST)); 1310*0Sstevel@tonic-gate 1311*0Sstevel@tonic-gate /* 1312*0Sstevel@tonic-gate * CSR_V LPU_PHY_INTERRUPT_MASK Expect HW 0x0 1313*0Sstevel@tonic-gate */ 1314*0Sstevel@tonic-gate 1315*0Sstevel@tonic-gate val = 0ull; 1316*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_PHY_INTERRUPT_MASK, val); 1317*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_PHY_INTERRUPT_MASK: 0x%llx\n", 1318*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_PHY_INTERRUPT_MASK)); 1319*0Sstevel@tonic-gate 1320*0Sstevel@tonic-gate /* 1321*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_CONFIG Expect HW 0x0 1322*0Sstevel@tonic-gate */ 1323*0Sstevel@tonic-gate 1324*0Sstevel@tonic-gate /* 1325*0Sstevel@tonic-gate * This also needs some explanation. What is the best value 1326*0Sstevel@tonic-gate * for the water mark? Test mode enables which test mode? 1327*0Sstevel@tonic-gate * Programming model needed for the Receiver Reset Lane N 1328*0Sstevel@tonic-gate * bits. 1329*0Sstevel@tonic-gate */ 1330*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_CONFIG: 0x%llx\n", 1331*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_CONFIG)); 1332*0Sstevel@tonic-gate 1333*0Sstevel@tonic-gate /* 1334*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_STATUS1 Expect HW 0x0 1335*0Sstevel@tonic-gate */ 1336*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS1: 0x%llx\n", 1337*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS1)); 1338*0Sstevel@tonic-gate 1339*0Sstevel@tonic-gate /* 1340*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_STATUS2 Expect HW 0x0 1341*0Sstevel@tonic-gate */ 1342*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS2: 0x%llx\n", 1343*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS2)); 1344*0Sstevel@tonic-gate 1345*0Sstevel@tonic-gate /* 1346*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_STATUS3 Expect HW 0x0 1347*0Sstevel@tonic-gate */ 1348*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_RECEIVE_PHY_STATUS3: 0x%llx\n", 1349*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_STATUS3)); 1350*0Sstevel@tonic-gate 1351*0Sstevel@tonic-gate /* 1352*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS Expect HW 0x0 1353*0Sstevel@tonic-gate */ 1354*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1355*0Sstevel@tonic-gate "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1356*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS)); 1357*0Sstevel@tonic-gate 1358*0Sstevel@tonic-gate /* 1359*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1360*0Sstevel@tonic-gate */ 1361*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1362*0Sstevel@tonic-gate "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1363*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_TEST)); 1364*0Sstevel@tonic-gate 1365*0Sstevel@tonic-gate /* 1366*0Sstevel@tonic-gate * CSR_V LPU_RECEIVE_PHY_INTERRUPT_MASK Expect OBP 0x0 1367*0Sstevel@tonic-gate */ 1368*0Sstevel@tonic-gate val = 0ull; 1369*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_RECEIVE_PHY_INTERRUPT_MASK, val); 1370*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1371*0Sstevel@tonic-gate "lpu_init - LPU_RECEIVE_PHY_INTERRUPT_MASK: 0x%llx\n", 1372*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_RECEIVE_PHY_INTERRUPT_MASK)); 1373*0Sstevel@tonic-gate 1374*0Sstevel@tonic-gate /* 1375*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_CONFIG Expect HW 0x0 1376*0Sstevel@tonic-gate */ 1377*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_CONFIG: 0x%llx\n", 1378*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TRANSMIT_PHY_CONFIG)); 1379*0Sstevel@tonic-gate 1380*0Sstevel@tonic-gate /* 1381*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_STATUS Expect HW 0x0 1382*0Sstevel@tonic-gate */ 1383*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS: 0x%llx\n", 1384*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS)); 1385*0Sstevel@tonic-gate 1386*0Sstevel@tonic-gate /* 1387*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS Expect HW 0x0 1388*0Sstevel@tonic-gate */ 1389*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1390*0Sstevel@tonic-gate "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS: 0x%llx\n", 1391*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS)); 1392*0Sstevel@tonic-gate 1393*0Sstevel@tonic-gate /* 1394*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1395*0Sstevel@tonic-gate */ 1396*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1397*0Sstevel@tonic-gate "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1398*0Sstevel@tonic-gate CSR_XR(csr_base, 1399*0Sstevel@tonic-gate LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_TEST)); 1400*0Sstevel@tonic-gate 1401*0Sstevel@tonic-gate /* 1402*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_INTERRUPT_MASK Expect HW 0x0 1403*0Sstevel@tonic-gate */ 1404*0Sstevel@tonic-gate val = 0ull; 1405*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_MASK, val); 1406*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1407*0Sstevel@tonic-gate "lpu_init - LPU_TRANSMIT_PHY_INTERRUPT_MASK: 0x%llx\n", 1408*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TRANSMIT_PHY_INTERRUPT_MASK)); 1409*0Sstevel@tonic-gate 1410*0Sstevel@tonic-gate /* 1411*0Sstevel@tonic-gate * CSR_V LPU_TRANSMIT_PHY_STATUS_2 Expect HW 0x0 1412*0Sstevel@tonic-gate */ 1413*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_TRANSMIT_PHY_STATUS_2: 0x%llx\n", 1414*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_TRANSMIT_PHY_STATUS_2)); 1415*0Sstevel@tonic-gate 1416*0Sstevel@tonic-gate /* 1417*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONFIG1 Expect OBP 0x205 1418*0Sstevel@tonic-gate */ 1419*0Sstevel@tonic-gate 1420*0Sstevel@tonic-gate /* 1421*0Sstevel@tonic-gate * The new PRM has values for LTSSM 8 ns timeout value and 1422*0Sstevel@tonic-gate * LTSSM 20 ns timeout value. But what do these values mean? 1423*0Sstevel@tonic-gate * Most of the other bits are questions as well. 1424*0Sstevel@tonic-gate * 1425*0Sstevel@tonic-gate * As such we will use the reset value. 1426*0Sstevel@tonic-gate */ 1427*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG1: 0x%llx\n", 1428*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONFIG1)); 1429*0Sstevel@tonic-gate 1430*0Sstevel@tonic-gate /* 1431*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONFIG2 Expect OBP 0x2DC6C0 1432*0Sstevel@tonic-gate */ 1433*0Sstevel@tonic-gate 1434*0Sstevel@tonic-gate /* 1435*0Sstevel@tonic-gate * Again, what does '12 ms timeout value mean'? 1436*0Sstevel@tonic-gate */ 1437*0Sstevel@tonic-gate val = (LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT << 1438*0Sstevel@tonic-gate LPU_LTSSM_CONFIG2_LTSSM_12_TO); 1439*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LTSSM_CONFIG2, val); 1440*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG2: 0x%llx\n", 1441*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONFIG2)); 1442*0Sstevel@tonic-gate 1443*0Sstevel@tonic-gate /* 1444*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONFIG3 Expect OBP 0x7A120 1445*0Sstevel@tonic-gate */ 1446*0Sstevel@tonic-gate val = (LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT << 1447*0Sstevel@tonic-gate LPU_LTSSM_CONFIG3_LTSSM_2_TO); 1448*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LTSSM_CONFIG3, val); 1449*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG3: 0x%llx\n", 1450*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONFIG3)); 1451*0Sstevel@tonic-gate 1452*0Sstevel@tonic-gate /* 1453*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONFIG4 Expect OBP 0x21300 1454*0Sstevel@tonic-gate * 1455*0Sstevel@tonic-gate * XXX fix LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT & 1456*0Sstevel@tonic-gate * LPU_LTSSM_CONFIG4_N_FTS_DEFAULT in px_pec.h 1457*0Sstevel@tonic-gate */ 1458*0Sstevel@tonic-gate val = ((LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT << 1459*0Sstevel@tonic-gate LPU_LTSSM_CONFIG4_DATA_RATE) | 1460*0Sstevel@tonic-gate (LPU_LTSSM_CONFIG4_N_FTS_DEFAULT << 1461*0Sstevel@tonic-gate LPU_LTSSM_CONFIG4_N_FTS)); 1462*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LTSSM_CONFIG4, val); 1463*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG4: 0x%llx\n", 1464*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONFIG4)); 1465*0Sstevel@tonic-gate 1466*0Sstevel@tonic-gate /* 1467*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_CONFIG5 Expect OBP 0x0 1468*0Sstevel@tonic-gate */ 1469*0Sstevel@tonic-gate val = 0ull; 1470*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LTSSM_CONFIG5, val); 1471*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_CONFIG5: 0x%llx\n", 1472*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_CONFIG5)); 1473*0Sstevel@tonic-gate 1474*0Sstevel@tonic-gate /* 1475*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_STATUS1 Expect OBP 0x0 1476*0Sstevel@tonic-gate */ 1477*0Sstevel@tonic-gate 1478*0Sstevel@tonic-gate /* 1479*0Sstevel@tonic-gate * LTSSM Status registers are test only. 1480*0Sstevel@tonic-gate */ 1481*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS1: 0x%llx\n", 1482*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_STATUS1)); 1483*0Sstevel@tonic-gate 1484*0Sstevel@tonic-gate /* 1485*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_STATUS2 Expect OBP 0x0 1486*0Sstevel@tonic-gate */ 1487*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_STATUS2: 0x%llx\n", 1488*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_STATUS2)); 1489*0Sstevel@tonic-gate 1490*0Sstevel@tonic-gate /* 1491*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS Expect HW 0x0 1492*0Sstevel@tonic-gate */ 1493*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1494*0Sstevel@tonic-gate "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS: 0x%llx\n", 1495*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS)); 1496*0Sstevel@tonic-gate 1497*0Sstevel@tonic-gate /* 1498*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_INTERRUPT_AND_STATUS_TEST Expect HW 0x0 1499*0Sstevel@tonic-gate */ 1500*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1501*0Sstevel@tonic-gate "lpu_init - LPU_LTSSM_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1502*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_AND_STATUS_TEST)); 1503*0Sstevel@tonic-gate 1504*0Sstevel@tonic-gate /* 1505*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_INTERRUPT_MASK Expect HW 0x0 1506*0Sstevel@tonic-gate */ 1507*0Sstevel@tonic-gate val = 0ull; 1508*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_LTSSM_INTERRUPT_MASK, val); 1509*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_LTSSM_INTERRUPT_MASK: 0x%llx\n", 1510*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_INTERRUPT_MASK)); 1511*0Sstevel@tonic-gate 1512*0Sstevel@tonic-gate /* 1513*0Sstevel@tonic-gate * CSR_V LPU_LTSSM_STATUS_WRITE_ENABLE Expect OBP 0x0 1514*0Sstevel@tonic-gate */ 1515*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1516*0Sstevel@tonic-gate "lpu_init - LPU_LTSSM_STATUS_WRITE_ENABLE: 0x%llx\n", 1517*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_LTSSM_STATUS_WRITE_ENABLE)); 1518*0Sstevel@tonic-gate 1519*0Sstevel@tonic-gate /* 1520*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_CONFIG1 Expect OBP 0x88407 1521*0Sstevel@tonic-gate */ 1522*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG1: 0x%llx\n", 1523*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG1)); 1524*0Sstevel@tonic-gate 1525*0Sstevel@tonic-gate /* 1526*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_CONFIG2 Expect OBP 0x35 1527*0Sstevel@tonic-gate */ 1528*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG2: 0x%llx\n", 1529*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG2)); 1530*0Sstevel@tonic-gate 1531*0Sstevel@tonic-gate /* 1532*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_CONFIG3 Expect OBP 0x4400FA 1533*0Sstevel@tonic-gate */ 1534*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG3: 0x%llx\n", 1535*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG3)); 1536*0Sstevel@tonic-gate 1537*0Sstevel@tonic-gate /* 1538*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_CONFIG4 Expect OBP 0x1E848 1539*0Sstevel@tonic-gate */ 1540*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG4: 0x%llx\n", 1541*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG4)); 1542*0Sstevel@tonic-gate 1543*0Sstevel@tonic-gate /* 1544*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_STATUS Expect OBP 0x0 1545*0Sstevel@tonic-gate */ 1546*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_STATUS: 0x%llx\n", 1547*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_STATUS)); 1548*0Sstevel@tonic-gate 1549*0Sstevel@tonic-gate /* 1550*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS Expect OBP 0x0 1551*0Sstevel@tonic-gate */ 1552*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1553*0Sstevel@tonic-gate "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS: 0x%llx\n", 1554*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS)); 1555*0Sstevel@tonic-gate 1556*0Sstevel@tonic-gate /* 1557*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST Expect OBP 0x0 1558*0Sstevel@tonic-gate */ 1559*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1560*0Sstevel@tonic-gate "lpu_init - " 1561*0Sstevel@tonic-gate "LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST: 0x%llx\n", 1562*0Sstevel@tonic-gate CSR_XR(csr_base, 1563*0Sstevel@tonic-gate LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_TEST)); 1564*0Sstevel@tonic-gate 1565*0Sstevel@tonic-gate /* 1566*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_INTERRUPT_MASK Expect OBP 0x0 1567*0Sstevel@tonic-gate */ 1568*0Sstevel@tonic-gate 1569*0Sstevel@tonic-gate /* 1570*0Sstevel@tonic-gate * Reset value masks all interrupts. This will be changed 1571*0Sstevel@tonic-gate * to enable all interrupts. 1572*0Sstevel@tonic-gate */ 1573*0Sstevel@tonic-gate val = 0x0ull; 1574*0Sstevel@tonic-gate CSR_XS(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_MASK, val); 1575*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1576*0Sstevel@tonic-gate "lpu_init - LPU_GIGABLAZE_GLUE_INTERRUPT_MASK: 0x%llx\n", 1577*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_INTERRUPT_MASK)); 1578*0Sstevel@tonic-gate 1579*0Sstevel@tonic-gate /* 1580*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN1 Expect HW 0x0 1581*0Sstevel@tonic-gate */ 1582*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1583*0Sstevel@tonic-gate "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN1: 0x%llx\n", 1584*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN1)); 1585*0Sstevel@tonic-gate 1586*0Sstevel@tonic-gate /* 1587*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_POWER_DOWN2 Expect HW 0x0 1588*0Sstevel@tonic-gate */ 1589*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, 1590*0Sstevel@tonic-gate "lpu_init - LPU_GIGABLAZE_GLUE_POWER_DOWN2: 0x%llx\n", 1591*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_POWER_DOWN2)); 1592*0Sstevel@tonic-gate 1593*0Sstevel@tonic-gate /* 1594*0Sstevel@tonic-gate * CSR_V LPU_GIGABLAZE_GLUE_CONFIG5 Expect OBP 0x0 1595*0Sstevel@tonic-gate */ 1596*0Sstevel@tonic-gate DBG(DBG_LPU, NULL, "lpu_init - LPU_GIGABLAZE_GLUE_CONFIG5: 0x%llx\n", 1597*0Sstevel@tonic-gate CSR_XR(csr_base, LPU_GIGABLAZE_GLUE_CONFIG5)); 1598*0Sstevel@tonic-gate } 1599*0Sstevel@tonic-gate 1600*0Sstevel@tonic-gate /* ARGSUSED */ 1601*0Sstevel@tonic-gate static void 1602*0Sstevel@tonic-gate dmc_init(caddr_t csr_base, pxu_t *pxu_p) 1603*0Sstevel@tonic-gate { 1604*0Sstevel@tonic-gate uint64_t val; 1605*0Sstevel@tonic-gate 1606*0Sstevel@tonic-gate /* 1607*0Sstevel@tonic-gate * CSR_V DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect OBP 0x8000000000000003 1608*0Sstevel@tonic-gate */ 1609*0Sstevel@tonic-gate 1610*0Sstevel@tonic-gate val = -1ull; 1611*0Sstevel@tonic-gate CSR_XS(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1612*0Sstevel@tonic-gate DBG(DBG_DMC, NULL, 1613*0Sstevel@tonic-gate "dmc_init - DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1614*0Sstevel@tonic-gate CSR_XR(csr_base, DMC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1615*0Sstevel@tonic-gate 1616*0Sstevel@tonic-gate /* 1617*0Sstevel@tonic-gate * CSR_V DMC_CORE_AND_BLOCK_ERROR_STATUS Expect HW 0x0 1618*0Sstevel@tonic-gate */ 1619*0Sstevel@tonic-gate DBG(DBG_DMC, NULL, 1620*0Sstevel@tonic-gate "dmc_init - DMC_CORE_AND_BLOCK_ERROR_STATUS: 0x%llx\n", 1621*0Sstevel@tonic-gate CSR_XR(csr_base, DMC_CORE_AND_BLOCK_ERROR_STATUS)); 1622*0Sstevel@tonic-gate 1623*0Sstevel@tonic-gate /* 1624*0Sstevel@tonic-gate * CSR_V DMC_DEBUG_SELECT_FOR_PORT_A Expect HW 0x0 1625*0Sstevel@tonic-gate */ 1626*0Sstevel@tonic-gate val = 0x0ull; 1627*0Sstevel@tonic-gate CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A, val); 1628*0Sstevel@tonic-gate DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_A: 0x%llx\n", 1629*0Sstevel@tonic-gate CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_A)); 1630*0Sstevel@tonic-gate 1631*0Sstevel@tonic-gate /* 1632*0Sstevel@tonic-gate * CSR_V DMC_DEBUG_SELECT_FOR_PORT_B Expect HW 0x0 1633*0Sstevel@tonic-gate */ 1634*0Sstevel@tonic-gate val = 0x0ull; 1635*0Sstevel@tonic-gate CSR_XS(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B, val); 1636*0Sstevel@tonic-gate DBG(DBG_DMC, NULL, "dmc_init - DMC_DEBUG_SELECT_FOR_PORT_B: 0x%llx\n", 1637*0Sstevel@tonic-gate CSR_XR(csr_base, DMC_DEBUG_SELECT_FOR_PORT_B)); 1638*0Sstevel@tonic-gate } 1639*0Sstevel@tonic-gate 1640*0Sstevel@tonic-gate void 1641*0Sstevel@tonic-gate hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p) 1642*0Sstevel@tonic-gate { 1643*0Sstevel@tonic-gate uint64_t val; 1644*0Sstevel@tonic-gate 1645*0Sstevel@tonic-gate ilu_init(csr_base, pxu_p); 1646*0Sstevel@tonic-gate tlu_init(csr_base, pxu_p); 1647*0Sstevel@tonic-gate lpu_init(csr_base, pxu_p); 1648*0Sstevel@tonic-gate dmc_init(csr_base, pxu_p); 1649*0Sstevel@tonic-gate 1650*0Sstevel@tonic-gate /* 1651*0Sstevel@tonic-gate * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE Expect Kernel 0x800000000000000F 1652*0Sstevel@tonic-gate */ 1653*0Sstevel@tonic-gate 1654*0Sstevel@tonic-gate val = -1ull; 1655*0Sstevel@tonic-gate CSR_XS(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE, val); 1656*0Sstevel@tonic-gate DBG(DBG_PEC, NULL, 1657*0Sstevel@tonic-gate "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE: 0x%llx\n", 1658*0Sstevel@tonic-gate CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_ENABLE)); 1659*0Sstevel@tonic-gate 1660*0Sstevel@tonic-gate /* 1661*0Sstevel@tonic-gate * CSR_V PEC_CORE_AND_BLOCK_INTERRUPT_STATUS Expect HW 0x0 1662*0Sstevel@tonic-gate */ 1663*0Sstevel@tonic-gate DBG(DBG_PEC, NULL, 1664*0Sstevel@tonic-gate "hvio_pec_init - PEC_CORE_AND_BLOCK_INTERRUPT_STATUS: 0x%llx\n", 1665*0Sstevel@tonic-gate CSR_XR(csr_base, PEC_CORE_AND_BLOCK_INTERRUPT_STATUS)); 1666*0Sstevel@tonic-gate } 1667*0Sstevel@tonic-gate 1668*0Sstevel@tonic-gate void 1669*0Sstevel@tonic-gate hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p) 1670*0Sstevel@tonic-gate { 1671*0Sstevel@tonic-gate uint64_t val, i, tsb_ctrl, obp_tsb_pa, *base_tte_addr; 1672*0Sstevel@tonic-gate uint_t obp_tsb_entries, obp_tsb_size; 1673*0Sstevel@tonic-gate 1674*0Sstevel@tonic-gate bzero(pxu_p->tsb_vaddr, pxu_p->tsb_size); 1675*0Sstevel@tonic-gate 1676*0Sstevel@tonic-gate /* 1677*0Sstevel@tonic-gate * Preserve OBP's TSB 1678*0Sstevel@tonic-gate */ 1679*0Sstevel@tonic-gate val = CSR_XR(csr_base, MMU_TSB_CONTROL); 1680*0Sstevel@tonic-gate 1681*0Sstevel@tonic-gate tsb_ctrl = CSR_XR(csr_base, MMU_TSB_CONTROL); 1682*0Sstevel@tonic-gate 1683*0Sstevel@tonic-gate obp_tsb_pa = tsb_ctrl & 0x7FFFFFFE000; 1684*0Sstevel@tonic-gate obp_tsb_size = tsb_ctrl & 0xF; 1685*0Sstevel@tonic-gate 1686*0Sstevel@tonic-gate obp_tsb_entries = MMU_TSBSIZE_TO_TSBENTRIES(obp_tsb_size); 1687*0Sstevel@tonic-gate 1688*0Sstevel@tonic-gate base_tte_addr = pxu_p->tsb_vaddr + 1689*0Sstevel@tonic-gate ((pxu_p->tsb_size >> 3) - obp_tsb_entries); 1690*0Sstevel@tonic-gate 1691*0Sstevel@tonic-gate for (i = 0; i < obp_tsb_entries; i++) { 1692*0Sstevel@tonic-gate uint64_t tte = lddphys(obp_tsb_pa + i * 8); 1693*0Sstevel@tonic-gate 1694*0Sstevel@tonic-gate if (!MMU_TTE_VALID(tte)) 1695*0Sstevel@tonic-gate continue; 1696*0Sstevel@tonic-gate 1697*0Sstevel@tonic-gate base_tte_addr[i] = tte; 1698*0Sstevel@tonic-gate } 1699*0Sstevel@tonic-gate 1700*0Sstevel@tonic-gate /* 1701*0Sstevel@tonic-gate * Invalidate the TLB through the diagnostic register. 1702*0Sstevel@tonic-gate */ 1703*0Sstevel@tonic-gate 1704*0Sstevel@tonic-gate CSR_XS(csr_base, MMU_TTE_CACHE_INVALIDATE, -1ull); 1705*0Sstevel@tonic-gate 1706*0Sstevel@tonic-gate /* 1707*0Sstevel@tonic-gate * Configure the Fire MMU TSB Control Register. Determine 1708*0Sstevel@tonic-gate * the encoding for either 8KB pages (0) or 64KB pages (1). 1709*0Sstevel@tonic-gate * 1710*0Sstevel@tonic-gate * Write the most significant 30 bits of the TSB physical address 1711*0Sstevel@tonic-gate * and the encoded TSB table size. 1712*0Sstevel@tonic-gate */ 1713*0Sstevel@tonic-gate for (i = 8; i && (pxu_p->tsb_size < (0x2000 << i)); i--); 1714*0Sstevel@tonic-gate 1715*0Sstevel@tonic-gate val = (((((va_to_pa(pxu_p->tsb_vaddr)) >> 13) << 13) | 1716*0Sstevel@tonic-gate ((MMU_PAGE_SHIFT == 13) ? 0 : 1) << 8) | i); 1717*0Sstevel@tonic-gate 1718*0Sstevel@tonic-gate CSR_XS(csr_base, MMU_TSB_CONTROL, val); 1719*0Sstevel@tonic-gate 1720*0Sstevel@tonic-gate /* 1721*0Sstevel@tonic-gate * Enable the MMU, set the "TSB Cache Snoop Enable", 1722*0Sstevel@tonic-gate * the "Cache Mode", the "Bypass Enable" and 1723*0Sstevel@tonic-gate * the "Translation Enable" bits. 1724*0Sstevel@tonic-gate */ 1725*0Sstevel@tonic-gate val = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1726*0Sstevel@tonic-gate val |= ((1ull << MMU_CONTROL_AND_STATUS_SE) 1727*0Sstevel@tonic-gate | (MMU_CONTROL_AND_STATUS_CM_MASK << MMU_CONTROL_AND_STATUS_CM) 1728*0Sstevel@tonic-gate | (1ull << MMU_CONTROL_AND_STATUS_BE) 1729*0Sstevel@tonic-gate | (1ull << MMU_CONTROL_AND_STATUS_TE)); 1730*0Sstevel@tonic-gate 1731*0Sstevel@tonic-gate CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, val); 1732*0Sstevel@tonic-gate 1733*0Sstevel@tonic-gate /* 1734*0Sstevel@tonic-gate * Read the register here to ensure that the previous writes to 1735*0Sstevel@tonic-gate * the Fire MMU registers have been flushed. (Technically, this 1736*0Sstevel@tonic-gate * is not entirely necessary here as we will likely do later reads 1737*0Sstevel@tonic-gate * during Fire initialization, but it is a small price to pay for 1738*0Sstevel@tonic-gate * more modular code.) 1739*0Sstevel@tonic-gate */ 1740*0Sstevel@tonic-gate (void) CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1741*0Sstevel@tonic-gate 1742*0Sstevel@tonic-gate /* 1743*0Sstevel@tonic-gate * Enable all primary and secondary interrupts. 1744*0Sstevel@tonic-gate */ 1745*0Sstevel@tonic-gate val = -1ull; 1746*0Sstevel@tonic-gate CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, val); 1747*0Sstevel@tonic-gate } 1748*0Sstevel@tonic-gate 1749*0Sstevel@tonic-gate /* 1750*0Sstevel@tonic-gate * Generic IOMMU Servies 1751*0Sstevel@tonic-gate */ 1752*0Sstevel@tonic-gate 1753*0Sstevel@tonic-gate /* ARGSUSED */ 1754*0Sstevel@tonic-gate uint64_t 1755*0Sstevel@tonic-gate hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1756*0Sstevel@tonic-gate pages_t pages, io_attributes_t io_attributes, 1757*0Sstevel@tonic-gate void *addr, size_t pfn_index, int flag) 1758*0Sstevel@tonic-gate { 1759*0Sstevel@tonic-gate tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1760*0Sstevel@tonic-gate uint64_t attr = MMU_TTE_V; 1761*0Sstevel@tonic-gate int i; 1762*0Sstevel@tonic-gate 1763*0Sstevel@tonic-gate if (io_attributes & PCI_MAP_ATTR_WRITE) 1764*0Sstevel@tonic-gate attr |= MMU_TTE_W; 1765*0Sstevel@tonic-gate 1766*0Sstevel@tonic-gate if (flag == MMU_MAP_MP) { 1767*0Sstevel@tonic-gate ddi_dma_impl_t *mp = (ddi_dma_impl_t *)addr; 1768*0Sstevel@tonic-gate 1769*0Sstevel@tonic-gate for (i = 0; i < pages; i++, pfn_index++, tsb_index++) { 1770*0Sstevel@tonic-gate px_iopfn_t pfn = PX_GET_MP_PFN(mp, pfn_index); 1771*0Sstevel@tonic-gate 1772*0Sstevel@tonic-gate pxu_p->tsb_vaddr[tsb_index] = 1773*0Sstevel@tonic-gate MMU_PTOB(pfn) | attr; 1774*0Sstevel@tonic-gate } 1775*0Sstevel@tonic-gate } else { 1776*0Sstevel@tonic-gate caddr_t a = (caddr_t)addr; 1777*0Sstevel@tonic-gate 1778*0Sstevel@tonic-gate for (i = 0; i < pages; i++, a += MMU_PAGE_SIZE, tsb_index++) { 1779*0Sstevel@tonic-gate px_iopfn_t pfn = hat_getpfnum(kas.a_hat, a); 1780*0Sstevel@tonic-gate 1781*0Sstevel@tonic-gate pxu_p->tsb_vaddr[tsb_index] = 1782*0Sstevel@tonic-gate MMU_PTOB(pfn) | attr; 1783*0Sstevel@tonic-gate } 1784*0Sstevel@tonic-gate } 1785*0Sstevel@tonic-gate 1786*0Sstevel@tonic-gate return (H_EOK); 1787*0Sstevel@tonic-gate } 1788*0Sstevel@tonic-gate 1789*0Sstevel@tonic-gate /* ARGSUSED */ 1790*0Sstevel@tonic-gate uint64_t 1791*0Sstevel@tonic-gate hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1792*0Sstevel@tonic-gate pages_t pages) 1793*0Sstevel@tonic-gate { 1794*0Sstevel@tonic-gate tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1795*0Sstevel@tonic-gate int i; 1796*0Sstevel@tonic-gate 1797*0Sstevel@tonic-gate for (i = 0; i < pages; i++, tsb_index++) { 1798*0Sstevel@tonic-gate pxu_p->tsb_vaddr[tsb_index] = MMU_INVALID_TTE; 1799*0Sstevel@tonic-gate } 1800*0Sstevel@tonic-gate 1801*0Sstevel@tonic-gate return (H_EOK); 1802*0Sstevel@tonic-gate } 1803*0Sstevel@tonic-gate 1804*0Sstevel@tonic-gate /* ARGSUSED */ 1805*0Sstevel@tonic-gate uint64_t 1806*0Sstevel@tonic-gate hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 1807*0Sstevel@tonic-gate io_attributes_t *attributes_p, r_addr_t *r_addr_p) 1808*0Sstevel@tonic-gate { 1809*0Sstevel@tonic-gate tsbindex_t tsb_index = PCI_TSBID_TO_TSBINDEX(tsbid); 1810*0Sstevel@tonic-gate uint64_t *tte_addr; 1811*0Sstevel@tonic-gate uint64_t ret = H_EOK; 1812*0Sstevel@tonic-gate 1813*0Sstevel@tonic-gate tte_addr = (uint64_t *)(pxu_p->tsb_vaddr) + tsb_index; 1814*0Sstevel@tonic-gate 1815*0Sstevel@tonic-gate if (*tte_addr & MMU_TTE_V) { 1816*0Sstevel@tonic-gate *r_addr_p = MMU_TTETOPA(*tte_addr); 1817*0Sstevel@tonic-gate *attributes_p = (*tte_addr & MMU_TTE_W) ? 1818*0Sstevel@tonic-gate PCI_MAP_ATTR_WRITE:PCI_MAP_ATTR_READ; 1819*0Sstevel@tonic-gate } else { 1820*0Sstevel@tonic-gate *r_addr_p = 0; 1821*0Sstevel@tonic-gate *attributes_p = 0; 1822*0Sstevel@tonic-gate ret = H_ENOMAP; 1823*0Sstevel@tonic-gate } 1824*0Sstevel@tonic-gate 1825*0Sstevel@tonic-gate return (ret); 1826*0Sstevel@tonic-gate } 1827*0Sstevel@tonic-gate 1828*0Sstevel@tonic-gate /* ARGSUSED */ 1829*0Sstevel@tonic-gate uint64_t 1830*0Sstevel@tonic-gate hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 1831*0Sstevel@tonic-gate io_attributes_t io_attributes, io_addr_t *io_addr_p) 1832*0Sstevel@tonic-gate { 1833*0Sstevel@tonic-gate uint64_t pfn = MMU_BTOP(ra); 1834*0Sstevel@tonic-gate 1835*0Sstevel@tonic-gate *io_addr_p = MMU_BYPASS_BASE | ra | 1836*0Sstevel@tonic-gate (pf_is_memory(pfn) ? 0 : MMU_BYPASS_NONCACHE); 1837*0Sstevel@tonic-gate 1838*0Sstevel@tonic-gate return (H_EOK); 1839*0Sstevel@tonic-gate } 1840*0Sstevel@tonic-gate 1841*0Sstevel@tonic-gate /* 1842*0Sstevel@tonic-gate * Generic IO Interrupt Servies 1843*0Sstevel@tonic-gate */ 1844*0Sstevel@tonic-gate 1845*0Sstevel@tonic-gate /* 1846*0Sstevel@tonic-gate * Converts a device specific interrupt number given by the 1847*0Sstevel@tonic-gate * arguments devhandle and devino into a system specific ino. 1848*0Sstevel@tonic-gate */ 1849*0Sstevel@tonic-gate /* ARGSUSED */ 1850*0Sstevel@tonic-gate uint64_t 1851*0Sstevel@tonic-gate hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, devino_t devino, 1852*0Sstevel@tonic-gate sysino_t *sysino) 1853*0Sstevel@tonic-gate { 1854*0Sstevel@tonic-gate if (devino > INTERRUPT_MAPPING_ENTRIES) { 1855*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "ino %x is invalid\n", devino); 1856*0Sstevel@tonic-gate return (H_ENOINTR); 1857*0Sstevel@tonic-gate } 1858*0Sstevel@tonic-gate 1859*0Sstevel@tonic-gate *sysino = DEVINO_TO_SYSINO(pxu_p->portid, devino); 1860*0Sstevel@tonic-gate 1861*0Sstevel@tonic-gate return (H_EOK); 1862*0Sstevel@tonic-gate } 1863*0Sstevel@tonic-gate 1864*0Sstevel@tonic-gate /* 1865*0Sstevel@tonic-gate * Returns state in intr_valid_state if the interrupt defined by sysino 1866*0Sstevel@tonic-gate * is valid (enabled) or not-valid (disabled). 1867*0Sstevel@tonic-gate */ 1868*0Sstevel@tonic-gate uint64_t 1869*0Sstevel@tonic-gate hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 1870*0Sstevel@tonic-gate intr_valid_state_t *intr_valid_state) 1871*0Sstevel@tonic-gate { 1872*0Sstevel@tonic-gate if (CSRA_BR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 1873*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_V)) { 1874*0Sstevel@tonic-gate *intr_valid_state = INTR_VALID; 1875*0Sstevel@tonic-gate } else { 1876*0Sstevel@tonic-gate *intr_valid_state = INTR_NOTVALID; 1877*0Sstevel@tonic-gate } 1878*0Sstevel@tonic-gate 1879*0Sstevel@tonic-gate return (H_EOK); 1880*0Sstevel@tonic-gate } 1881*0Sstevel@tonic-gate 1882*0Sstevel@tonic-gate /* 1883*0Sstevel@tonic-gate * Sets the 'valid' state of the interrupt defined by 1884*0Sstevel@tonic-gate * the argument sysino to the state defined by the 1885*0Sstevel@tonic-gate * argument intr_valid_state. 1886*0Sstevel@tonic-gate */ 1887*0Sstevel@tonic-gate uint64_t 1888*0Sstevel@tonic-gate hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 1889*0Sstevel@tonic-gate intr_valid_state_t intr_valid_state) 1890*0Sstevel@tonic-gate { 1891*0Sstevel@tonic-gate switch (intr_valid_state) { 1892*0Sstevel@tonic-gate case INTR_VALID: 1893*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, INTERRUPT_MAPPING, 1894*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_V); 1895*0Sstevel@tonic-gate break; 1896*0Sstevel@tonic-gate case INTR_NOTVALID: 1897*0Sstevel@tonic-gate CSRA_BC((caddr_t)dev_hdl, INTERRUPT_MAPPING, 1898*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_V); 1899*0Sstevel@tonic-gate break; 1900*0Sstevel@tonic-gate default: 1901*0Sstevel@tonic-gate return (EINVAL); 1902*0Sstevel@tonic-gate } 1903*0Sstevel@tonic-gate 1904*0Sstevel@tonic-gate return (H_EOK); 1905*0Sstevel@tonic-gate } 1906*0Sstevel@tonic-gate 1907*0Sstevel@tonic-gate /* 1908*0Sstevel@tonic-gate * Returns the current state of the interrupt given by the sysino 1909*0Sstevel@tonic-gate * argument. 1910*0Sstevel@tonic-gate */ 1911*0Sstevel@tonic-gate uint64_t 1912*0Sstevel@tonic-gate hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 1913*0Sstevel@tonic-gate intr_state_t *intr_state) 1914*0Sstevel@tonic-gate { 1915*0Sstevel@tonic-gate intr_state_t state; 1916*0Sstevel@tonic-gate 1917*0Sstevel@tonic-gate state = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_CLEAR, 1918*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE); 1919*0Sstevel@tonic-gate 1920*0Sstevel@tonic-gate switch (state) { 1921*0Sstevel@tonic-gate case INTERRUPT_IDLE_STATE: 1922*0Sstevel@tonic-gate *intr_state = INTR_IDLE_STATE; 1923*0Sstevel@tonic-gate break; 1924*0Sstevel@tonic-gate case INTERRUPT_RECEIVED_STATE: 1925*0Sstevel@tonic-gate *intr_state = INTR_RECEIVED_STATE; 1926*0Sstevel@tonic-gate break; 1927*0Sstevel@tonic-gate case INTERRUPT_PENDING_STATE: 1928*0Sstevel@tonic-gate *intr_state = INTR_DELIVERED_STATE; 1929*0Sstevel@tonic-gate break; 1930*0Sstevel@tonic-gate default: 1931*0Sstevel@tonic-gate return (EINVAL); 1932*0Sstevel@tonic-gate } 1933*0Sstevel@tonic-gate 1934*0Sstevel@tonic-gate return (H_EOK); 1935*0Sstevel@tonic-gate 1936*0Sstevel@tonic-gate } 1937*0Sstevel@tonic-gate 1938*0Sstevel@tonic-gate /* 1939*0Sstevel@tonic-gate * Sets the current state of the interrupt given by the sysino 1940*0Sstevel@tonic-gate * argument to the value given in the argument intr_state. 1941*0Sstevel@tonic-gate * 1942*0Sstevel@tonic-gate * Note: Setting the state to INTR_IDLE clears any pending 1943*0Sstevel@tonic-gate * interrupt for sysino. 1944*0Sstevel@tonic-gate */ 1945*0Sstevel@tonic-gate uint64_t 1946*0Sstevel@tonic-gate hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 1947*0Sstevel@tonic-gate intr_state_t intr_state) 1948*0Sstevel@tonic-gate { 1949*0Sstevel@tonic-gate intr_state_t state; 1950*0Sstevel@tonic-gate 1951*0Sstevel@tonic-gate switch (intr_state) { 1952*0Sstevel@tonic-gate case INTR_IDLE_STATE: 1953*0Sstevel@tonic-gate state = INTERRUPT_IDLE_STATE; 1954*0Sstevel@tonic-gate break; 1955*0Sstevel@tonic-gate case INTR_DELIVERED_STATE: 1956*0Sstevel@tonic-gate state = INTERRUPT_PENDING_STATE; 1957*0Sstevel@tonic-gate break; 1958*0Sstevel@tonic-gate default: 1959*0Sstevel@tonic-gate return (EINVAL); 1960*0Sstevel@tonic-gate } 1961*0Sstevel@tonic-gate 1962*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, 1963*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_INT_STATE, state); 1964*0Sstevel@tonic-gate 1965*0Sstevel@tonic-gate return (H_EOK); 1966*0Sstevel@tonic-gate } 1967*0Sstevel@tonic-gate 1968*0Sstevel@tonic-gate /* 1969*0Sstevel@tonic-gate * Returns the cpuid that is the current target of the 1970*0Sstevel@tonic-gate * interrupt given by the sysino argument. 1971*0Sstevel@tonic-gate * 1972*0Sstevel@tonic-gate * The cpuid value returned is undefined if the target 1973*0Sstevel@tonic-gate * has not been set via intr_settarget. 1974*0Sstevel@tonic-gate */ 1975*0Sstevel@tonic-gate uint64_t 1976*0Sstevel@tonic-gate hvio_intr_gettarget(devhandle_t dev_hdl, sysino_t sysino, cpuid_t *cpuid) 1977*0Sstevel@tonic-gate { 1978*0Sstevel@tonic-gate *cpuid = CSRA_FR((caddr_t)dev_hdl, INTERRUPT_MAPPING, 1979*0Sstevel@tonic-gate SYSINO_TO_DEVINO(sysino), ENTRIES_T_JPID); 1980*0Sstevel@tonic-gate 1981*0Sstevel@tonic-gate return (H_EOK); 1982*0Sstevel@tonic-gate } 1983*0Sstevel@tonic-gate 1984*0Sstevel@tonic-gate /* 1985*0Sstevel@tonic-gate * Set the target cpu for the interrupt defined by the argument 1986*0Sstevel@tonic-gate * sysino to the target cpu value defined by the argument cpuid. 1987*0Sstevel@tonic-gate */ 1988*0Sstevel@tonic-gate uint64_t 1989*0Sstevel@tonic-gate hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, cpuid_t cpuid) 1990*0Sstevel@tonic-gate { 1991*0Sstevel@tonic-gate 1992*0Sstevel@tonic-gate uint64_t val, intr_controller; 1993*0Sstevel@tonic-gate uint32_t ino = SYSINO_TO_DEVINO(sysino); 1994*0Sstevel@tonic-gate 1995*0Sstevel@tonic-gate /* 1996*0Sstevel@tonic-gate * For now, we assign interrupt controller in a round 1997*0Sstevel@tonic-gate * robin fashion. Later, we may need to come up with 1998*0Sstevel@tonic-gate * a more efficient assignment algorithm. 1999*0Sstevel@tonic-gate */ 2000*0Sstevel@tonic-gate intr_controller = 0x1ull << (cpuid % 4); 2001*0Sstevel@tonic-gate 2002*0Sstevel@tonic-gate val = (((cpuid & INTERRUPT_MAPPING_ENTRIES_T_JPID_MASK) << 2003*0Sstevel@tonic-gate INTERRUPT_MAPPING_ENTRIES_T_JPID) | 2004*0Sstevel@tonic-gate ((intr_controller & INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM_MASK) 2005*0Sstevel@tonic-gate << INTERRUPT_MAPPING_ENTRIES_INT_CNTRL_NUM)); 2006*0Sstevel@tonic-gate 2007*0Sstevel@tonic-gate /* For EQ interrupts, set DATA MONDO bit */ 2008*0Sstevel@tonic-gate if ((ino >= PX_DEFAULT_MSIQ_1ST_DEVINO) && 2009*0Sstevel@tonic-gate (ino < (PX_DEFAULT_MSIQ_1ST_DEVINO + PX_DEFAULT_MSIQ_CNT))) 2010*0Sstevel@tonic-gate val |= (0x1ull << INTERRUPT_MAPPING_ENTRIES_MDO_MODE); 2011*0Sstevel@tonic-gate 2012*0Sstevel@tonic-gate CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, ino, val); 2013*0Sstevel@tonic-gate 2014*0Sstevel@tonic-gate return (H_EOK); 2015*0Sstevel@tonic-gate } 2016*0Sstevel@tonic-gate 2017*0Sstevel@tonic-gate /* 2018*0Sstevel@tonic-gate * MSIQ Functions: 2019*0Sstevel@tonic-gate */ 2020*0Sstevel@tonic-gate uint64_t 2021*0Sstevel@tonic-gate hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p) 2022*0Sstevel@tonic-gate { 2023*0Sstevel@tonic-gate CSRA_XS((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS, 0, 2024*0Sstevel@tonic-gate (uint64_t)pxu_p->msiq_mapped_p); 2025*0Sstevel@tonic-gate DBG(DBG_IB, NULL, 2026*0Sstevel@tonic-gate "hvio_msiq_init: EVENT_QUEUE_BASE_ADDRESS 0x%llx\n", 2027*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, EVENT_QUEUE_BASE_ADDRESS)); 2028*0Sstevel@tonic-gate 2029*0Sstevel@tonic-gate CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0, 0, 2030*0Sstevel@tonic-gate (uint64_t)ID_TO_IGN(pxu_p->portid) << INO_BITS); 2031*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_msiq_init: " 2032*0Sstevel@tonic-gate "INTERRUPT_MONDO_DATA_0: 0x%llx\n", 2033*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, INTERRUPT_MONDO_DATA_0)); 2034*0Sstevel@tonic-gate 2035*0Sstevel@tonic-gate return (H_EOK); 2036*0Sstevel@tonic-gate } 2037*0Sstevel@tonic-gate 2038*0Sstevel@tonic-gate uint64_t 2039*0Sstevel@tonic-gate hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2040*0Sstevel@tonic-gate pci_msiq_valid_state_t *msiq_valid_state) 2041*0Sstevel@tonic-gate { 2042*0Sstevel@tonic-gate uint32_t eq_state; 2043*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2044*0Sstevel@tonic-gate 2045*0Sstevel@tonic-gate eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2046*0Sstevel@tonic-gate msiq_id, ENTRIES_STATE); 2047*0Sstevel@tonic-gate 2048*0Sstevel@tonic-gate switch (eq_state) { 2049*0Sstevel@tonic-gate case EQ_IDLE_STATE: 2050*0Sstevel@tonic-gate *msiq_valid_state = PCI_MSIQ_INVALID; 2051*0Sstevel@tonic-gate break; 2052*0Sstevel@tonic-gate case EQ_ACTIVE_STATE: 2053*0Sstevel@tonic-gate case EQ_ERROR_STATE: 2054*0Sstevel@tonic-gate *msiq_valid_state = PCI_MSIQ_VALID; 2055*0Sstevel@tonic-gate break; 2056*0Sstevel@tonic-gate default: 2057*0Sstevel@tonic-gate ret = H_EIO; 2058*0Sstevel@tonic-gate break; 2059*0Sstevel@tonic-gate } 2060*0Sstevel@tonic-gate 2061*0Sstevel@tonic-gate return (ret); 2062*0Sstevel@tonic-gate } 2063*0Sstevel@tonic-gate 2064*0Sstevel@tonic-gate uint64_t 2065*0Sstevel@tonic-gate hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 2066*0Sstevel@tonic-gate pci_msiq_valid_state_t msiq_valid_state) 2067*0Sstevel@tonic-gate { 2068*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2069*0Sstevel@tonic-gate 2070*0Sstevel@tonic-gate switch (msiq_valid_state) { 2071*0Sstevel@tonic-gate case PCI_MSIQ_INVALID: 2072*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2073*0Sstevel@tonic-gate msiq_id, ENTRIES_DIS); 2074*0Sstevel@tonic-gate break; 2075*0Sstevel@tonic-gate case PCI_MSIQ_VALID: 2076*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2077*0Sstevel@tonic-gate msiq_id, ENTRIES_EN); 2078*0Sstevel@tonic-gate break; 2079*0Sstevel@tonic-gate default: 2080*0Sstevel@tonic-gate ret = H_EINVAL; 2081*0Sstevel@tonic-gate break; 2082*0Sstevel@tonic-gate } 2083*0Sstevel@tonic-gate 2084*0Sstevel@tonic-gate return (ret); 2085*0Sstevel@tonic-gate } 2086*0Sstevel@tonic-gate 2087*0Sstevel@tonic-gate uint64_t 2088*0Sstevel@tonic-gate hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2089*0Sstevel@tonic-gate pci_msiq_state_t *msiq_state) 2090*0Sstevel@tonic-gate { 2091*0Sstevel@tonic-gate uint32_t eq_state; 2092*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2093*0Sstevel@tonic-gate 2094*0Sstevel@tonic-gate eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2095*0Sstevel@tonic-gate msiq_id, ENTRIES_STATE); 2096*0Sstevel@tonic-gate 2097*0Sstevel@tonic-gate switch (eq_state) { 2098*0Sstevel@tonic-gate case EQ_IDLE_STATE: 2099*0Sstevel@tonic-gate case EQ_ACTIVE_STATE: 2100*0Sstevel@tonic-gate *msiq_state = PCI_MSIQ_STATE_IDLE; 2101*0Sstevel@tonic-gate break; 2102*0Sstevel@tonic-gate case EQ_ERROR_STATE: 2103*0Sstevel@tonic-gate *msiq_state = PCI_MSIQ_STATE_ERROR; 2104*0Sstevel@tonic-gate break; 2105*0Sstevel@tonic-gate default: 2106*0Sstevel@tonic-gate ret = H_EIO; 2107*0Sstevel@tonic-gate } 2108*0Sstevel@tonic-gate 2109*0Sstevel@tonic-gate return (ret); 2110*0Sstevel@tonic-gate } 2111*0Sstevel@tonic-gate 2112*0Sstevel@tonic-gate uint64_t 2113*0Sstevel@tonic-gate hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 2114*0Sstevel@tonic-gate pci_msiq_state_t msiq_state) 2115*0Sstevel@tonic-gate { 2116*0Sstevel@tonic-gate uint32_t eq_state; 2117*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2118*0Sstevel@tonic-gate 2119*0Sstevel@tonic-gate eq_state = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, 2120*0Sstevel@tonic-gate msiq_id, ENTRIES_STATE); 2121*0Sstevel@tonic-gate 2122*0Sstevel@tonic-gate switch (eq_state) { 2123*0Sstevel@tonic-gate case EQ_IDLE_STATE: 2124*0Sstevel@tonic-gate if (msiq_state == PCI_MSIQ_STATE_ERROR) 2125*0Sstevel@tonic-gate ret = H_EIO; 2126*0Sstevel@tonic-gate break; 2127*0Sstevel@tonic-gate case EQ_ACTIVE_STATE: 2128*0Sstevel@tonic-gate if (msiq_state == PCI_MSIQ_STATE_ERROR) 2129*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2130*0Sstevel@tonic-gate msiq_id, ENTRIES_ENOVERR); 2131*0Sstevel@tonic-gate else 2132*0Sstevel@tonic-gate ret = H_EIO; 2133*0Sstevel@tonic-gate break; 2134*0Sstevel@tonic-gate case EQ_ERROR_STATE: 2135*0Sstevel@tonic-gate if (msiq_state == PCI_MSIQ_STATE_IDLE) 2136*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_CLEAR, 2137*0Sstevel@tonic-gate msiq_id, ENTRIES_E2I); 2138*0Sstevel@tonic-gate else 2139*0Sstevel@tonic-gate ret = H_EIO; 2140*0Sstevel@tonic-gate break; 2141*0Sstevel@tonic-gate default: 2142*0Sstevel@tonic-gate ret = H_EIO; 2143*0Sstevel@tonic-gate } 2144*0Sstevel@tonic-gate 2145*0Sstevel@tonic-gate return (ret); 2146*0Sstevel@tonic-gate } 2147*0Sstevel@tonic-gate 2148*0Sstevel@tonic-gate uint64_t 2149*0Sstevel@tonic-gate hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2150*0Sstevel@tonic-gate msiqhead_t *msiq_head) 2151*0Sstevel@tonic-gate { 2152*0Sstevel@tonic-gate *msiq_head = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, 2153*0Sstevel@tonic-gate msiq_id, ENTRIES_HEAD); 2154*0Sstevel@tonic-gate 2155*0Sstevel@tonic-gate return (H_EOK); 2156*0Sstevel@tonic-gate } 2157*0Sstevel@tonic-gate 2158*0Sstevel@tonic-gate uint64_t 2159*0Sstevel@tonic-gate hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 2160*0Sstevel@tonic-gate msiqhead_t msiq_head) 2161*0Sstevel@tonic-gate { 2162*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, EVENT_QUEUE_HEAD, msiq_id, 2163*0Sstevel@tonic-gate ENTRIES_HEAD, msiq_head); 2164*0Sstevel@tonic-gate 2165*0Sstevel@tonic-gate return (H_EOK); 2166*0Sstevel@tonic-gate } 2167*0Sstevel@tonic-gate 2168*0Sstevel@tonic-gate uint64_t 2169*0Sstevel@tonic-gate hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 2170*0Sstevel@tonic-gate msiqtail_t *msiq_tail) 2171*0Sstevel@tonic-gate { 2172*0Sstevel@tonic-gate *msiq_tail = CSRA_FR((caddr_t)dev_hdl, EVENT_QUEUE_TAIL, 2173*0Sstevel@tonic-gate msiq_id, ENTRIES_TAIL); 2174*0Sstevel@tonic-gate 2175*0Sstevel@tonic-gate return (H_EOK); 2176*0Sstevel@tonic-gate } 2177*0Sstevel@tonic-gate 2178*0Sstevel@tonic-gate /* 2179*0Sstevel@tonic-gate * MSI Functions: 2180*0Sstevel@tonic-gate */ 2181*0Sstevel@tonic-gate uint64_t 2182*0Sstevel@tonic-gate hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, uint64_t addr64) 2183*0Sstevel@tonic-gate { 2184*0Sstevel@tonic-gate /* PCI MEM 32 resources to perform 32 bit MSI transactions */ 2185*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS, 0, 2186*0Sstevel@tonic-gate ADDR, (uint64_t)addr32 >> MSI_32_BIT_ADDRESS_ADDR); 2187*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_msiq_init: MSI_32_BIT_ADDRESS: 0x%llx\n", 2188*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, MSI_32_BIT_ADDRESS)); 2189*0Sstevel@tonic-gate 2190*0Sstevel@tonic-gate /* Reserve PCI MEM 64 resources to perform 64 bit MSI transactions */ 2191*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS, 0, 2192*0Sstevel@tonic-gate ADDR, (uint64_t)addr64 >> MSI_64_BIT_ADDRESS_ADDR); 2193*0Sstevel@tonic-gate DBG(DBG_IB, NULL, "hvio_msiq_init: MSI_64_BIT_ADDRESS: 0x%llx\n", 2194*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, MSI_64_BIT_ADDRESS)); 2195*0Sstevel@tonic-gate 2196*0Sstevel@tonic-gate return (H_EOK); 2197*0Sstevel@tonic-gate } 2198*0Sstevel@tonic-gate 2199*0Sstevel@tonic-gate uint64_t 2200*0Sstevel@tonic-gate hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2201*0Sstevel@tonic-gate msiqid_t *msiq_id) 2202*0Sstevel@tonic-gate { 2203*0Sstevel@tonic-gate *msiq_id = CSRA_FR((caddr_t)dev_hdl, MSI_MAPPING, 2204*0Sstevel@tonic-gate msi_num, ENTRIES_EQNUM); 2205*0Sstevel@tonic-gate 2206*0Sstevel@tonic-gate return (H_EOK); 2207*0Sstevel@tonic-gate } 2208*0Sstevel@tonic-gate 2209*0Sstevel@tonic-gate uint64_t 2210*0Sstevel@tonic-gate hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 2211*0Sstevel@tonic-gate msiqid_t msiq_id) 2212*0Sstevel@tonic-gate { 2213*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2214*0Sstevel@tonic-gate ENTRIES_EQNUM, msiq_id); 2215*0Sstevel@tonic-gate 2216*0Sstevel@tonic-gate return (H_EOK); 2217*0Sstevel@tonic-gate } 2218*0Sstevel@tonic-gate 2219*0Sstevel@tonic-gate uint64_t 2220*0Sstevel@tonic-gate hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 2221*0Sstevel@tonic-gate pci_msi_valid_state_t *msi_valid_state) 2222*0Sstevel@tonic-gate { 2223*0Sstevel@tonic-gate *msi_valid_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2224*0Sstevel@tonic-gate msi_num, ENTRIES_V); 2225*0Sstevel@tonic-gate 2226*0Sstevel@tonic-gate return (H_EOK); 2227*0Sstevel@tonic-gate } 2228*0Sstevel@tonic-gate 2229*0Sstevel@tonic-gate uint64_t 2230*0Sstevel@tonic-gate hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 2231*0Sstevel@tonic-gate pci_msi_valid_state_t msi_valid_state) 2232*0Sstevel@tonic-gate { 2233*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2234*0Sstevel@tonic-gate 2235*0Sstevel@tonic-gate switch (msi_valid_state) { 2236*0Sstevel@tonic-gate case PCI_MSI_VALID: 2237*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2238*0Sstevel@tonic-gate ENTRIES_V); 2239*0Sstevel@tonic-gate break; 2240*0Sstevel@tonic-gate case PCI_MSI_INVALID: 2241*0Sstevel@tonic-gate CSRA_BC((caddr_t)dev_hdl, MSI_MAPPING, msi_num, 2242*0Sstevel@tonic-gate ENTRIES_V); 2243*0Sstevel@tonic-gate break; 2244*0Sstevel@tonic-gate default: 2245*0Sstevel@tonic-gate ret = H_EINVAL; 2246*0Sstevel@tonic-gate } 2247*0Sstevel@tonic-gate 2248*0Sstevel@tonic-gate return (ret); 2249*0Sstevel@tonic-gate } 2250*0Sstevel@tonic-gate 2251*0Sstevel@tonic-gate uint64_t 2252*0Sstevel@tonic-gate hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 2253*0Sstevel@tonic-gate pci_msi_state_t *msi_state) 2254*0Sstevel@tonic-gate { 2255*0Sstevel@tonic-gate *msi_state = CSRA_BR((caddr_t)dev_hdl, MSI_MAPPING, 2256*0Sstevel@tonic-gate msi_num, ENTRIES_EQWR_N); 2257*0Sstevel@tonic-gate 2258*0Sstevel@tonic-gate return (H_EOK); 2259*0Sstevel@tonic-gate } 2260*0Sstevel@tonic-gate 2261*0Sstevel@tonic-gate uint64_t 2262*0Sstevel@tonic-gate hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 2263*0Sstevel@tonic-gate pci_msi_state_t msi_state) 2264*0Sstevel@tonic-gate { 2265*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2266*0Sstevel@tonic-gate 2267*0Sstevel@tonic-gate switch (msi_state) { 2268*0Sstevel@tonic-gate case PCI_MSI_STATE_IDLE: 2269*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, MSI_CLEAR, msi_num, 2270*0Sstevel@tonic-gate ENTRIES_EQWR_N); 2271*0Sstevel@tonic-gate break; 2272*0Sstevel@tonic-gate case PCI_MSI_STATE_DELIVERED: 2273*0Sstevel@tonic-gate default: 2274*0Sstevel@tonic-gate ret = H_EINVAL; 2275*0Sstevel@tonic-gate break; 2276*0Sstevel@tonic-gate } 2277*0Sstevel@tonic-gate 2278*0Sstevel@tonic-gate return (ret); 2279*0Sstevel@tonic-gate } 2280*0Sstevel@tonic-gate 2281*0Sstevel@tonic-gate /* 2282*0Sstevel@tonic-gate * MSG Functions: 2283*0Sstevel@tonic-gate */ 2284*0Sstevel@tonic-gate uint64_t 2285*0Sstevel@tonic-gate hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2286*0Sstevel@tonic-gate msiqid_t *msiq_id) 2287*0Sstevel@tonic-gate { 2288*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2289*0Sstevel@tonic-gate 2290*0Sstevel@tonic-gate switch (msg_type) { 2291*0Sstevel@tonic-gate case PCIE_PME_MSG: 2292*0Sstevel@tonic-gate *msiq_id = CSR_FR((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM); 2293*0Sstevel@tonic-gate break; 2294*0Sstevel@tonic-gate case PCIE_PME_ACK_MSG: 2295*0Sstevel@tonic-gate *msiq_id = CSR_FR((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, 2296*0Sstevel@tonic-gate EQNUM); 2297*0Sstevel@tonic-gate break; 2298*0Sstevel@tonic-gate case PCIE_CORR_MSG: 2299*0Sstevel@tonic-gate *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM); 2300*0Sstevel@tonic-gate break; 2301*0Sstevel@tonic-gate case PCIE_NONFATAL_MSG: 2302*0Sstevel@tonic-gate *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, 2303*0Sstevel@tonic-gate EQNUM); 2304*0Sstevel@tonic-gate break; 2305*0Sstevel@tonic-gate case PCIE_FATAL_MSG: 2306*0Sstevel@tonic-gate *msiq_id = CSR_FR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM); 2307*0Sstevel@tonic-gate break; 2308*0Sstevel@tonic-gate default: 2309*0Sstevel@tonic-gate ret = H_EINVAL; 2310*0Sstevel@tonic-gate break; 2311*0Sstevel@tonic-gate } 2312*0Sstevel@tonic-gate 2313*0Sstevel@tonic-gate return (ret); 2314*0Sstevel@tonic-gate } 2315*0Sstevel@tonic-gate 2316*0Sstevel@tonic-gate uint64_t 2317*0Sstevel@tonic-gate hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2318*0Sstevel@tonic-gate msiqid_t msiq_id) 2319*0Sstevel@tonic-gate { 2320*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2321*0Sstevel@tonic-gate 2322*0Sstevel@tonic-gate switch (msg_type) { 2323*0Sstevel@tonic-gate case PCIE_PME_MSG: 2324*0Sstevel@tonic-gate CSR_FS((caddr_t)dev_hdl, PM_PME_MAPPING, EQNUM, msiq_id); 2325*0Sstevel@tonic-gate break; 2326*0Sstevel@tonic-gate case PCIE_PME_ACK_MSG: 2327*0Sstevel@tonic-gate CSR_FS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, EQNUM, msiq_id); 2328*0Sstevel@tonic-gate break; 2329*0Sstevel@tonic-gate case PCIE_CORR_MSG: 2330*0Sstevel@tonic-gate CSR_FS((caddr_t)dev_hdl, ERR_COR_MAPPING, EQNUM, msiq_id); 2331*0Sstevel@tonic-gate break; 2332*0Sstevel@tonic-gate case PCIE_NONFATAL_MSG: 2333*0Sstevel@tonic-gate CSR_FS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, EQNUM, msiq_id); 2334*0Sstevel@tonic-gate break; 2335*0Sstevel@tonic-gate case PCIE_FATAL_MSG: 2336*0Sstevel@tonic-gate CSR_FS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, EQNUM, msiq_id); 2337*0Sstevel@tonic-gate break; 2338*0Sstevel@tonic-gate default: 2339*0Sstevel@tonic-gate ret = H_EINVAL; 2340*0Sstevel@tonic-gate break; 2341*0Sstevel@tonic-gate } 2342*0Sstevel@tonic-gate 2343*0Sstevel@tonic-gate return (ret); 2344*0Sstevel@tonic-gate } 2345*0Sstevel@tonic-gate 2346*0Sstevel@tonic-gate uint64_t 2347*0Sstevel@tonic-gate hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2348*0Sstevel@tonic-gate pcie_msg_valid_state_t *msg_valid_state) 2349*0Sstevel@tonic-gate { 2350*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2351*0Sstevel@tonic-gate 2352*0Sstevel@tonic-gate switch (msg_type) { 2353*0Sstevel@tonic-gate case PCIE_PME_MSG: 2354*0Sstevel@tonic-gate *msg_valid_state = CSR_BR((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2355*0Sstevel@tonic-gate break; 2356*0Sstevel@tonic-gate case PCIE_PME_ACK_MSG: 2357*0Sstevel@tonic-gate *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2358*0Sstevel@tonic-gate PME_TO_ACK_MAPPING, V); 2359*0Sstevel@tonic-gate break; 2360*0Sstevel@tonic-gate case PCIE_CORR_MSG: 2361*0Sstevel@tonic-gate *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2362*0Sstevel@tonic-gate break; 2363*0Sstevel@tonic-gate case PCIE_NONFATAL_MSG: 2364*0Sstevel@tonic-gate *msg_valid_state = CSR_BR((caddr_t)dev_hdl, 2365*0Sstevel@tonic-gate ERR_NONFATAL_MAPPING, V); 2366*0Sstevel@tonic-gate break; 2367*0Sstevel@tonic-gate case PCIE_FATAL_MSG: 2368*0Sstevel@tonic-gate *msg_valid_state = CSR_BR((caddr_t)dev_hdl, ERR_FATAL_MAPPING, 2369*0Sstevel@tonic-gate V); 2370*0Sstevel@tonic-gate break; 2371*0Sstevel@tonic-gate default: 2372*0Sstevel@tonic-gate ret = H_EINVAL; 2373*0Sstevel@tonic-gate break; 2374*0Sstevel@tonic-gate } 2375*0Sstevel@tonic-gate 2376*0Sstevel@tonic-gate return (ret); 2377*0Sstevel@tonic-gate } 2378*0Sstevel@tonic-gate 2379*0Sstevel@tonic-gate uint64_t 2380*0Sstevel@tonic-gate hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 2381*0Sstevel@tonic-gate pcie_msg_valid_state_t msg_valid_state) 2382*0Sstevel@tonic-gate { 2383*0Sstevel@tonic-gate uint64_t ret = H_EOK; 2384*0Sstevel@tonic-gate 2385*0Sstevel@tonic-gate switch (msg_valid_state) { 2386*0Sstevel@tonic-gate case PCIE_MSG_VALID: 2387*0Sstevel@tonic-gate switch (msg_type) { 2388*0Sstevel@tonic-gate case PCIE_PME_MSG: 2389*0Sstevel@tonic-gate CSR_BS((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2390*0Sstevel@tonic-gate break; 2391*0Sstevel@tonic-gate case PCIE_PME_ACK_MSG: 2392*0Sstevel@tonic-gate CSR_BS((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2393*0Sstevel@tonic-gate break; 2394*0Sstevel@tonic-gate case PCIE_CORR_MSG: 2395*0Sstevel@tonic-gate CSR_BS((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2396*0Sstevel@tonic-gate break; 2397*0Sstevel@tonic-gate case PCIE_NONFATAL_MSG: 2398*0Sstevel@tonic-gate CSR_BS((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2399*0Sstevel@tonic-gate break; 2400*0Sstevel@tonic-gate case PCIE_FATAL_MSG: 2401*0Sstevel@tonic-gate CSR_BS((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2402*0Sstevel@tonic-gate break; 2403*0Sstevel@tonic-gate default: 2404*0Sstevel@tonic-gate ret = H_EINVAL; 2405*0Sstevel@tonic-gate break; 2406*0Sstevel@tonic-gate } 2407*0Sstevel@tonic-gate 2408*0Sstevel@tonic-gate break; 2409*0Sstevel@tonic-gate case PCIE_MSG_INVALID: 2410*0Sstevel@tonic-gate switch (msg_type) { 2411*0Sstevel@tonic-gate case PCIE_PME_MSG: 2412*0Sstevel@tonic-gate CSR_BC((caddr_t)dev_hdl, PM_PME_MAPPING, V); 2413*0Sstevel@tonic-gate break; 2414*0Sstevel@tonic-gate case PCIE_PME_ACK_MSG: 2415*0Sstevel@tonic-gate CSR_BC((caddr_t)dev_hdl, PME_TO_ACK_MAPPING, V); 2416*0Sstevel@tonic-gate break; 2417*0Sstevel@tonic-gate case PCIE_CORR_MSG: 2418*0Sstevel@tonic-gate CSR_BC((caddr_t)dev_hdl, ERR_COR_MAPPING, V); 2419*0Sstevel@tonic-gate break; 2420*0Sstevel@tonic-gate case PCIE_NONFATAL_MSG: 2421*0Sstevel@tonic-gate CSR_BC((caddr_t)dev_hdl, ERR_NONFATAL_MAPPING, V); 2422*0Sstevel@tonic-gate break; 2423*0Sstevel@tonic-gate case PCIE_FATAL_MSG: 2424*0Sstevel@tonic-gate CSR_BC((caddr_t)dev_hdl, ERR_FATAL_MAPPING, V); 2425*0Sstevel@tonic-gate break; 2426*0Sstevel@tonic-gate default: 2427*0Sstevel@tonic-gate ret = H_EINVAL; 2428*0Sstevel@tonic-gate break; 2429*0Sstevel@tonic-gate } 2430*0Sstevel@tonic-gate break; 2431*0Sstevel@tonic-gate default: 2432*0Sstevel@tonic-gate ret = H_EINVAL; 2433*0Sstevel@tonic-gate } 2434*0Sstevel@tonic-gate 2435*0Sstevel@tonic-gate return (ret); 2436*0Sstevel@tonic-gate } 2437*0Sstevel@tonic-gate 2438*0Sstevel@tonic-gate /* 2439*0Sstevel@tonic-gate * Suspend/Resume Functions: 2440*0Sstevel@tonic-gate * (pec, mmu, ib) 2441*0Sstevel@tonic-gate * cb 2442*0Sstevel@tonic-gate * Registers saved have all been touched in the XXX_init functions. 2443*0Sstevel@tonic-gate */ 2444*0Sstevel@tonic-gate uint64_t 2445*0Sstevel@tonic-gate hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2446*0Sstevel@tonic-gate { 2447*0Sstevel@tonic-gate uint64_t *config_state; 2448*0Sstevel@tonic-gate int total_size; 2449*0Sstevel@tonic-gate int i; 2450*0Sstevel@tonic-gate 2451*0Sstevel@tonic-gate if (msiq_suspend(dev_hdl, pxu_p) != H_EOK) 2452*0Sstevel@tonic-gate return (H_EIO); 2453*0Sstevel@tonic-gate 2454*0Sstevel@tonic-gate total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2455*0Sstevel@tonic-gate config_state = kmem_zalloc(total_size, KM_NOSLEEP); 2456*0Sstevel@tonic-gate 2457*0Sstevel@tonic-gate if (config_state == NULL) { 2458*0Sstevel@tonic-gate return (H_EIO); 2459*0Sstevel@tonic-gate } 2460*0Sstevel@tonic-gate 2461*0Sstevel@tonic-gate /* 2462*0Sstevel@tonic-gate * Soft state for suspend/resume from pxu_t 2463*0Sstevel@tonic-gate * uint64_t *pec_config_state; 2464*0Sstevel@tonic-gate * uint64_t *mmu_config_state; 2465*0Sstevel@tonic-gate * uint64_t *ib_intr_map; 2466*0Sstevel@tonic-gate * uint64_t *ib_config_state; 2467*0Sstevel@tonic-gate * uint64_t *xcb_config_state; 2468*0Sstevel@tonic-gate */ 2469*0Sstevel@tonic-gate 2470*0Sstevel@tonic-gate /* Save the PEC configuration states */ 2471*0Sstevel@tonic-gate pxu_p->pec_config_state = config_state; 2472*0Sstevel@tonic-gate for (i = 0; i < PEC_KEYS; i++) { 2473*0Sstevel@tonic-gate pxu_p->pec_config_state[i] = 2474*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, pec_config_state_regs[i]); 2475*0Sstevel@tonic-gate } 2476*0Sstevel@tonic-gate 2477*0Sstevel@tonic-gate /* Save the MMU configuration states */ 2478*0Sstevel@tonic-gate pxu_p->mmu_config_state = pxu_p->pec_config_state + PEC_KEYS; 2479*0Sstevel@tonic-gate for (i = 0; i < MMU_KEYS; i++) { 2480*0Sstevel@tonic-gate pxu_p->mmu_config_state[i] = 2481*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, mmu_config_state_regs[i]); 2482*0Sstevel@tonic-gate } 2483*0Sstevel@tonic-gate 2484*0Sstevel@tonic-gate /* Save the interrupt mapping registers */ 2485*0Sstevel@tonic-gate pxu_p->ib_intr_map = pxu_p->mmu_config_state + MMU_KEYS; 2486*0Sstevel@tonic-gate for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2487*0Sstevel@tonic-gate pxu_p->ib_intr_map[i] = 2488*0Sstevel@tonic-gate CSRA_XR((caddr_t)dev_hdl, INTERRUPT_MAPPING, i); 2489*0Sstevel@tonic-gate } 2490*0Sstevel@tonic-gate 2491*0Sstevel@tonic-gate /* Save the IB configuration states */ 2492*0Sstevel@tonic-gate pxu_p->ib_config_state = pxu_p->ib_intr_map + INTERRUPT_MAPPING_ENTRIES; 2493*0Sstevel@tonic-gate for (i = 0; i < IB_KEYS; i++) { 2494*0Sstevel@tonic-gate pxu_p->ib_config_state[i] = 2495*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, ib_config_state_regs[i]); 2496*0Sstevel@tonic-gate } 2497*0Sstevel@tonic-gate 2498*0Sstevel@tonic-gate return (H_EOK); 2499*0Sstevel@tonic-gate } 2500*0Sstevel@tonic-gate 2501*0Sstevel@tonic-gate void 2502*0Sstevel@tonic-gate hvio_resume(devhandle_t dev_hdl, devino_t devino, pxu_t *pxu_p) 2503*0Sstevel@tonic-gate { 2504*0Sstevel@tonic-gate int total_size; 2505*0Sstevel@tonic-gate sysino_t sysino; 2506*0Sstevel@tonic-gate int i; 2507*0Sstevel@tonic-gate 2508*0Sstevel@tonic-gate /* Make sure that suspend actually did occur */ 2509*0Sstevel@tonic-gate if (!pxu_p->pec_config_state) { 2510*0Sstevel@tonic-gate return; 2511*0Sstevel@tonic-gate } 2512*0Sstevel@tonic-gate 2513*0Sstevel@tonic-gate /* Restore IB configuration states */ 2514*0Sstevel@tonic-gate for (i = 0; i < IB_KEYS; i++) { 2515*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, ib_config_state_regs[i], 2516*0Sstevel@tonic-gate pxu_p->ib_config_state[i]); 2517*0Sstevel@tonic-gate } 2518*0Sstevel@tonic-gate 2519*0Sstevel@tonic-gate /* 2520*0Sstevel@tonic-gate * Restore the interrupt mapping registers 2521*0Sstevel@tonic-gate * And make sure the intrs are idle. 2522*0Sstevel@tonic-gate */ 2523*0Sstevel@tonic-gate for (i = 0; i < INTERRUPT_MAPPING_ENTRIES; i++) { 2524*0Sstevel@tonic-gate CSRA_FS((caddr_t)dev_hdl, INTERRUPT_CLEAR, i, 2525*0Sstevel@tonic-gate ENTRIES_INT_STATE, INTERRUPT_IDLE_STATE); 2526*0Sstevel@tonic-gate CSRA_XS((caddr_t)dev_hdl, INTERRUPT_MAPPING, i, 2527*0Sstevel@tonic-gate pxu_p->ib_intr_map[i]); 2528*0Sstevel@tonic-gate } 2529*0Sstevel@tonic-gate 2530*0Sstevel@tonic-gate /* Restore MMU configuration states */ 2531*0Sstevel@tonic-gate /* Clear the cache. */ 2532*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, MMU_TTE_CACHE_INVALIDATE, -1ull); 2533*0Sstevel@tonic-gate 2534*0Sstevel@tonic-gate for (i = 0; i < MMU_KEYS; i++) { 2535*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, mmu_config_state_regs[i], 2536*0Sstevel@tonic-gate pxu_p->mmu_config_state[i]); 2537*0Sstevel@tonic-gate } 2538*0Sstevel@tonic-gate 2539*0Sstevel@tonic-gate /* Restore PEC configuration states */ 2540*0Sstevel@tonic-gate /* Make sure all reset bits are low until error is detected */ 2541*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, LPU_RESET, 0ull); 2542*0Sstevel@tonic-gate 2543*0Sstevel@tonic-gate for (i = 0; i < PEC_KEYS; i++) { 2544*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, pec_config_state_regs[i], 2545*0Sstevel@tonic-gate pxu_p->pec_config_state[i]); 2546*0Sstevel@tonic-gate } 2547*0Sstevel@tonic-gate 2548*0Sstevel@tonic-gate /* Enable PCI-E interrupt */ 2549*0Sstevel@tonic-gate (void) hvio_intr_devino_to_sysino(dev_hdl, pxu_p, devino, &sysino); 2550*0Sstevel@tonic-gate 2551*0Sstevel@tonic-gate (void) hvio_intr_setstate(dev_hdl, sysino, INTR_IDLE_STATE); 2552*0Sstevel@tonic-gate 2553*0Sstevel@tonic-gate total_size = PEC_SIZE + MMU_SIZE + IB_SIZE + IB_MAP_SIZE; 2554*0Sstevel@tonic-gate kmem_free(pxu_p->pec_config_state, total_size); 2555*0Sstevel@tonic-gate 2556*0Sstevel@tonic-gate pxu_p->pec_config_state = NULL; 2557*0Sstevel@tonic-gate pxu_p->mmu_config_state = NULL; 2558*0Sstevel@tonic-gate pxu_p->ib_config_state = NULL; 2559*0Sstevel@tonic-gate pxu_p->ib_intr_map = NULL; 2560*0Sstevel@tonic-gate 2561*0Sstevel@tonic-gate msiq_resume(dev_hdl, pxu_p); 2562*0Sstevel@tonic-gate } 2563*0Sstevel@tonic-gate 2564*0Sstevel@tonic-gate uint64_t 2565*0Sstevel@tonic-gate hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2566*0Sstevel@tonic-gate { 2567*0Sstevel@tonic-gate uint64_t *config_state; 2568*0Sstevel@tonic-gate int i; 2569*0Sstevel@tonic-gate 2570*0Sstevel@tonic-gate config_state = kmem_zalloc(CB_SIZE, KM_NOSLEEP); 2571*0Sstevel@tonic-gate 2572*0Sstevel@tonic-gate if (config_state == NULL) { 2573*0Sstevel@tonic-gate return (H_EIO); 2574*0Sstevel@tonic-gate } 2575*0Sstevel@tonic-gate 2576*0Sstevel@tonic-gate /* Save the configuration states */ 2577*0Sstevel@tonic-gate pxu_p->xcb_config_state = config_state; 2578*0Sstevel@tonic-gate for (i = 0; i < CB_KEYS; i++) { 2579*0Sstevel@tonic-gate pxu_p->xcb_config_state[i] = 2580*0Sstevel@tonic-gate CSR_XR((caddr_t)dev_hdl, cb_config_state_regs[i]); 2581*0Sstevel@tonic-gate } 2582*0Sstevel@tonic-gate 2583*0Sstevel@tonic-gate return (H_EOK); 2584*0Sstevel@tonic-gate } 2585*0Sstevel@tonic-gate 2586*0Sstevel@tonic-gate void 2587*0Sstevel@tonic-gate hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 2588*0Sstevel@tonic-gate devino_t devino, pxu_t *pxu_p) 2589*0Sstevel@tonic-gate { 2590*0Sstevel@tonic-gate sysino_t sysino; 2591*0Sstevel@tonic-gate int i; 2592*0Sstevel@tonic-gate 2593*0Sstevel@tonic-gate /* 2594*0Sstevel@tonic-gate * No reason to have any reset bits high until an error is 2595*0Sstevel@tonic-gate * detected on the link. 2596*0Sstevel@tonic-gate */ 2597*0Sstevel@tonic-gate CSR_XS((caddr_t)xbus_dev_hdl, JBC_ERROR_STATUS_CLEAR, -1ull); 2598*0Sstevel@tonic-gate 2599*0Sstevel@tonic-gate ASSERT(pxu_p->xcb_config_state); 2600*0Sstevel@tonic-gate 2601*0Sstevel@tonic-gate /* Restore the configuration states */ 2602*0Sstevel@tonic-gate for (i = 0; i < CB_KEYS; i++) { 2603*0Sstevel@tonic-gate CSR_XS((caddr_t)xbus_dev_hdl, cb_config_state_regs[i], 2604*0Sstevel@tonic-gate pxu_p->xcb_config_state[i]); 2605*0Sstevel@tonic-gate } 2606*0Sstevel@tonic-gate 2607*0Sstevel@tonic-gate /* Enable XBC interrupt */ 2608*0Sstevel@tonic-gate (void) hvio_intr_devino_to_sysino(pci_dev_hdl, pxu_p, devino, &sysino); 2609*0Sstevel@tonic-gate 2610*0Sstevel@tonic-gate (void) hvio_intr_setstate(pci_dev_hdl, sysino, INTR_IDLE_STATE); 2611*0Sstevel@tonic-gate 2612*0Sstevel@tonic-gate kmem_free(pxu_p->xcb_config_state, CB_SIZE); 2613*0Sstevel@tonic-gate 2614*0Sstevel@tonic-gate pxu_p->xcb_config_state = NULL; 2615*0Sstevel@tonic-gate } 2616*0Sstevel@tonic-gate 2617*0Sstevel@tonic-gate static uint64_t 2618*0Sstevel@tonic-gate msiq_suspend(devhandle_t dev_hdl, pxu_t *pxu_p) 2619*0Sstevel@tonic-gate { 2620*0Sstevel@tonic-gate size_t bufsz; 2621*0Sstevel@tonic-gate volatile uint64_t *cur_p; 2622*0Sstevel@tonic-gate int i; 2623*0Sstevel@tonic-gate 2624*0Sstevel@tonic-gate bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2625*0Sstevel@tonic-gate if ((pxu_p->msiq_config_state = kmem_zalloc(bufsz, KM_NOSLEEP)) == 2626*0Sstevel@tonic-gate NULL) 2627*0Sstevel@tonic-gate return (H_EIO); 2628*0Sstevel@tonic-gate 2629*0Sstevel@tonic-gate cur_p = pxu_p->msiq_config_state; 2630*0Sstevel@tonic-gate 2631*0Sstevel@tonic-gate /* Save each EQ state */ 2632*0Sstevel@tonic-gate for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) 2633*0Sstevel@tonic-gate *cur_p = CSRA_XR((caddr_t)dev_hdl, EVENT_QUEUE_STATE, i); 2634*0Sstevel@tonic-gate 2635*0Sstevel@tonic-gate /* Save MSI mapping registers */ 2636*0Sstevel@tonic-gate for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2637*0Sstevel@tonic-gate *cur_p = CSRA_XR((caddr_t)dev_hdl, MSI_MAPPING, i); 2638*0Sstevel@tonic-gate 2639*0Sstevel@tonic-gate /* Save all other MSIQ registers */ 2640*0Sstevel@tonic-gate for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2641*0Sstevel@tonic-gate *cur_p = CSR_XR((caddr_t)dev_hdl, msiq_config_other_regs[i]); 2642*0Sstevel@tonic-gate return (H_EOK); 2643*0Sstevel@tonic-gate } 2644*0Sstevel@tonic-gate 2645*0Sstevel@tonic-gate static void 2646*0Sstevel@tonic-gate msiq_resume(devhandle_t dev_hdl, pxu_t *pxu_p) 2647*0Sstevel@tonic-gate { 2648*0Sstevel@tonic-gate size_t bufsz; 2649*0Sstevel@tonic-gate uint64_t *cur_p; 2650*0Sstevel@tonic-gate int i; 2651*0Sstevel@tonic-gate 2652*0Sstevel@tonic-gate bufsz = MSIQ_STATE_SIZE + MSIQ_MAPPING_SIZE + MSIQ_OTHER_SIZE; 2653*0Sstevel@tonic-gate cur_p = pxu_p->msiq_config_state; 2654*0Sstevel@tonic-gate /* 2655*0Sstevel@tonic-gate * Initialize EQ base address register and 2656*0Sstevel@tonic-gate * Interrupt Mondo Data 0 register. 2657*0Sstevel@tonic-gate */ 2658*0Sstevel@tonic-gate (void) hvio_msiq_init(dev_hdl, pxu_p); 2659*0Sstevel@tonic-gate 2660*0Sstevel@tonic-gate /* Restore EQ states */ 2661*0Sstevel@tonic-gate for (i = 0; i < EVENT_QUEUE_STATE_ENTRIES; i++, cur_p++) { 2662*0Sstevel@tonic-gate if (((*cur_p) & EVENT_QUEUE_STATE_ENTRIES_STATE_MASK) == 2663*0Sstevel@tonic-gate EQ_ACTIVE_STATE) { 2664*0Sstevel@tonic-gate CSRA_BS((caddr_t)dev_hdl, EVENT_QUEUE_CONTROL_SET, 2665*0Sstevel@tonic-gate i, ENTRIES_EN); 2666*0Sstevel@tonic-gate } 2667*0Sstevel@tonic-gate } 2668*0Sstevel@tonic-gate 2669*0Sstevel@tonic-gate /* Restore MSI mapping */ 2670*0Sstevel@tonic-gate for (i = 0; i < MSI_MAPPING_ENTRIES; i++, cur_p++) 2671*0Sstevel@tonic-gate CSRA_XS((caddr_t)dev_hdl, MSI_MAPPING, i, *cur_p); 2672*0Sstevel@tonic-gate 2673*0Sstevel@tonic-gate /* 2674*0Sstevel@tonic-gate * Restore all other registers. MSI 32 bit address and 2675*0Sstevel@tonic-gate * MSI 64 bit address are restored as part of this. 2676*0Sstevel@tonic-gate */ 2677*0Sstevel@tonic-gate for (i = 0; i < MSIQ_OTHER_KEYS; i++, cur_p++) 2678*0Sstevel@tonic-gate CSR_XS((caddr_t)dev_hdl, msiq_config_other_regs[i], *cur_p); 2679*0Sstevel@tonic-gate 2680*0Sstevel@tonic-gate kmem_free(pxu_p->msiq_config_state, bufsz); 2681*0Sstevel@tonic-gate pxu_p->msiq_config_state = NULL; 2682*0Sstevel@tonic-gate } 2683*0Sstevel@tonic-gate 2684*0Sstevel@tonic-gate /* 2685*0Sstevel@tonic-gate * sends PME_Turn_Off message to put the link in L2/L3 ready state. 2686*0Sstevel@tonic-gate * called by px_goto_l23ready. 2687*0Sstevel@tonic-gate * returns DDI_SUCCESS or DDI_FAILURE 2688*0Sstevel@tonic-gate */ 2689*0Sstevel@tonic-gate int 2690*0Sstevel@tonic-gate px_send_pme_turnoff(caddr_t csr_base) 2691*0Sstevel@tonic-gate { 2692*0Sstevel@tonic-gate volatile uint64_t reg; 2693*0Sstevel@tonic-gate 2694*0Sstevel@tonic-gate /* TBD: Wait for link to be in L1 state (link status reg) */ 2695*0Sstevel@tonic-gate 2696*0Sstevel@tonic-gate reg = CSR_XR(csr_base, TLU_PME_TURN_OFF_GENERATE); 2697*0Sstevel@tonic-gate /* If already pending, return failure */ 2698*0Sstevel@tonic-gate if (reg & (1ull << TLU_PME_TURN_OFF_GENERATE_PTO)) { 2699*0Sstevel@tonic-gate return (DDI_FAILURE); 2700*0Sstevel@tonic-gate } 2701*0Sstevel@tonic-gate /* write to PME_Turn_off reg to boradcast */ 2702*0Sstevel@tonic-gate reg |= (1ull << TLU_PME_TURN_OFF_GENERATE_PTO); 2703*0Sstevel@tonic-gate CSR_XS(csr_base, TLU_PME_TURN_OFF_GENERATE, reg); 2704*0Sstevel@tonic-gate return (DDI_SUCCESS); 2705*0Sstevel@tonic-gate } 2706