1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * PCI nexus driver tunables 31*0Sstevel@tonic-gate */ 32*0Sstevel@tonic-gate 33*0Sstevel@tonic-gate #include <sys/types.h> 34*0Sstevel@tonic-gate #include <sys/cmn_err.h> 35*0Sstevel@tonic-gate #include <sys/time.h> 36*0Sstevel@tonic-gate #include <sys/thread.h> 37*0Sstevel@tonic-gate #include <sys/ksynch.h> 38*0Sstevel@tonic-gate #include <sys/pci.h> 39*0Sstevel@tonic-gate #include <sys/pci/pci_space.h> 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate /*LINTLIBRARY*/ 43*0Sstevel@tonic-gate 44*0Sstevel@tonic-gate /* 45*0Sstevel@tonic-gate * Used to disallow bypass requests for tomatillos ver <= 2.3 46*0Sstevel@tonic-gate * 0 allow bypass, 1 disallow it. errata #75 47*0Sstevel@tonic-gate */ 48*0Sstevel@tonic-gate uint_t tomatillo_disallow_bypass = 0; 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate /* 51*0Sstevel@tonic-gate * The three variables below enable a workround for 52*0Sstevel@tonic-gate * tomatillo's micro TLB bug. errata #82 53*0Sstevel@tonic-gate */ 54*0Sstevel@tonic-gate uint_t tm_mtlb_maxpgs = 20; 55*0Sstevel@tonic-gate uint_t tm_mtlb_gc = 0; /* for garbage collection */ 56*0Sstevel@tonic-gate uint_t tm_mtlb_gc_manual = 0; /* for manual tuning */ 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate /* 59*0Sstevel@tonic-gate * By initializing pci_interrupt_priorities_property to 1, the priority 60*0Sstevel@tonic-gate * level of the interrupt handler for a PCI device can be defined via an 61*0Sstevel@tonic-gate * "interrupt-priorities" property. This property is an array of integer 62*0Sstevel@tonic-gate * values that have a one to one mapping the the "interrupts" property. 63*0Sstevel@tonic-gate * For example, if a device's "interrupts" property was (1, 2) and its 64*0Sstevel@tonic-gate * "interrupt-priorities" value was (5, 12), the handler for the first 65*0Sstevel@tonic-gate * interrupt would run at cpu priority 5 and the second at priority 12. 66*0Sstevel@tonic-gate * This would override the drivers standard mechanism for assigning 67*0Sstevel@tonic-gate * priorities to interrupt handlers. 68*0Sstevel@tonic-gate */ 69*0Sstevel@tonic-gate uint_t pci_interrupt_priorities_property = 1; 70*0Sstevel@tonic-gate 71*0Sstevel@tonic-gate /* 72*0Sstevel@tonic-gate * By initializing pci_config_space_size_zero to 1, the driver will 73*0Sstevel@tonic-gate * tolerate mapping requests for configuration space "reg" entries whose 74*0Sstevel@tonic-gate * size is not zero. 75*0Sstevel@tonic-gate */ 76*0Sstevel@tonic-gate uint_t pci_config_space_size_zero = 1; 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate int pci_dvma_sync_before_unmap = 0; 79*0Sstevel@tonic-gate int pci_sync_lock = 0; 80*0Sstevel@tonic-gate 81*0Sstevel@tonic-gate int tomatillo_store_store_wrka = 0; 82*0Sstevel@tonic-gate uint32_t pci_spurintr_duration = 60000000; /* One minute */ 83*0Sstevel@tonic-gate uint64_t pci_spurintr_msgs = PCI_SPURINTR_MSG_DEFAULT; 84*0Sstevel@tonic-gate 85*0Sstevel@tonic-gate /* 86*0Sstevel@tonic-gate * The variable controls the default setting of the command register 87*0Sstevel@tonic-gate * for pci devices. See init_child() for details. 88*0Sstevel@tonic-gate * 89*0Sstevel@tonic-gate * This flags also controls the setting of bits in the bridge control 90*0Sstevel@tonic-gate * register pci to pci bridges. See init_child() for details. 91*0Sstevel@tonic-gate */ 92*0Sstevel@tonic-gate ushort_t pci_command_default = PCI_COMM_SERR_ENABLE | 93*0Sstevel@tonic-gate PCI_COMM_WAIT_CYC_ENAB | 94*0Sstevel@tonic-gate PCI_COMM_PARITY_DETECT | 95*0Sstevel@tonic-gate PCI_COMM_ME | 96*0Sstevel@tonic-gate PCI_COMM_MAE | 97*0Sstevel@tonic-gate PCI_COMM_IO; 98*0Sstevel@tonic-gate /* 99*0Sstevel@tonic-gate * The following variable enables a workaround for the following obp bug: 100*0Sstevel@tonic-gate * 101*0Sstevel@tonic-gate * 1234181 - obp should set latency timer registers in pci 102*0Sstevel@tonic-gate * configuration header 103*0Sstevel@tonic-gate * 104*0Sstevel@tonic-gate * Until this bug gets fixed in the obp, the following workaround should 105*0Sstevel@tonic-gate * be enabled. 106*0Sstevel@tonic-gate */ 107*0Sstevel@tonic-gate uint_t pci_set_latency_timer_register = 1; 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate /* 110*0Sstevel@tonic-gate * The following variable enables a workaround for an obp bug to be 111*0Sstevel@tonic-gate * submitted. A bug requesting a workaround fof this problem has 112*0Sstevel@tonic-gate * been filed: 113*0Sstevel@tonic-gate * 114*0Sstevel@tonic-gate * 1235094 - need workarounds on positron nexus drivers to set cache 115*0Sstevel@tonic-gate * line size registers 116*0Sstevel@tonic-gate * 117*0Sstevel@tonic-gate * Until this bug gets fixed in the obp, the following workaround should 118*0Sstevel@tonic-gate * be enabled. 119*0Sstevel@tonic-gate */ 120*0Sstevel@tonic-gate uint_t pci_set_cache_line_size_register = 1; 121*0Sstevel@tonic-gate 122*0Sstevel@tonic-gate /* 123*0Sstevel@tonic-gate * The following driver parameters are defined as variables to allow 124*0Sstevel@tonic-gate * patching for debugging and tuning. Flags that can be set on a per 125*0Sstevel@tonic-gate * PBM basis are bit fields where the PBM device instance number maps 126*0Sstevel@tonic-gate * to the bit position. 127*0Sstevel@tonic-gate */ 128*0Sstevel@tonic-gate #ifdef DEBUG 129*0Sstevel@tonic-gate uint64_t pci_debug_flags = 0; 130*0Sstevel@tonic-gate uint_t pci_warn_pp0 = 0; 131*0Sstevel@tonic-gate #endif 132*0Sstevel@tonic-gate uint_t pci_disable_pass1_workarounds = 0; 133*0Sstevel@tonic-gate uint_t pci_disable_pass2_workarounds = 0; 134*0Sstevel@tonic-gate uint_t pci_disable_pass3_workarounds = 0; 135*0Sstevel@tonic-gate uint_t pci_disable_plus_workarounds = 0; 136*0Sstevel@tonic-gate uint_t pci_disable_default_workarounds = 0; 137*0Sstevel@tonic-gate uint_t ecc_error_intr_enable = 1; 138*0Sstevel@tonic-gate uint_t pci_sbh_error_intr_enable = (uint_t)-1; 139*0Sstevel@tonic-gate uint_t pci_mmu_error_intr_enable = (uint_t)-1; 140*0Sstevel@tonic-gate uint_t pci_stream_buf_enable = (uint_t)-1; 141*0Sstevel@tonic-gate uint_t pci_stream_buf_exists = 1; 142*0Sstevel@tonic-gate uint_t pci_rerun_disable = 0; 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate uint_t pci_enable_retry_arb = (uint_t)-1; 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate uint_t pci_bus_parking_enable = (uint_t)-1; 147*0Sstevel@tonic-gate uint_t pci_error_intr_enable = (uint_t)-1; 148*0Sstevel@tonic-gate uint_t pci_retry_disable = 0; 149*0Sstevel@tonic-gate uint_t pci_retry_enable = 0; 150*0Sstevel@tonic-gate uint_t pci_dwsync_disable = 0; 151*0Sstevel@tonic-gate uint_t pci_intsync_disable = 0; 152*0Sstevel@tonic-gate uint_t pci_b_arb_enable = 0xf; 153*0Sstevel@tonic-gate uint_t pci_a_arb_enable = 0xf; 154*0Sstevel@tonic-gate uint_t pci_ecc_afsr_retries = 100; /* XXX - what's a good value? */ 155*0Sstevel@tonic-gate 156*0Sstevel@tonic-gate uint_t pci_intr_retry_intv = 5; /* for interrupt retry reg */ 157*0Sstevel@tonic-gate uint8_t pci_latency_timer = 0x40; /* for pci latency timer reg */ 158*0Sstevel@tonic-gate uint_t pci_panic_on_sbh_errors = 0; 159*0Sstevel@tonic-gate uint_t pci_panic_on_fatal_errors = 1; /* should be 1 at beta */ 160*0Sstevel@tonic-gate uint_t pci_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 161*0Sstevel@tonic-gate uint_t pci_buserr_interrupt = 1; /* safari buserr interrupt */ 162*0Sstevel@tonic-gate uint_t pci_set_dto_value = 0; /* overwrite the prom settings? */ 163*0Sstevel@tonic-gate uint_t pci_dto_value = 1; /* schizo consistent buf timeout PTO */ 164*0Sstevel@tonic-gate uint_t pci_lock_sbuf = 0; 165*0Sstevel@tonic-gate 166*0Sstevel@tonic-gate uint_t pci_use_contexts = 1; 167*0Sstevel@tonic-gate uint_t pci_sc_use_contexts = 1; 168*0Sstevel@tonic-gate uint_t pci_context_minpages = 2; 169*0Sstevel@tonic-gate uint_t pci_ctx_flush_warn = CE_IGNORE; 170*0Sstevel@tonic-gate uint_t pci_ctx_unsuccess_count = 0; /* unsuccessful ctx flush count */ 171*0Sstevel@tonic-gate uint_t pci_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 172*0Sstevel@tonic-gate uint_t pci_ctx_no_compat = 0; /* maintain compatibility */ 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate uint64_t pci_perr_enable = -1ull; 175*0Sstevel@tonic-gate uint64_t pci_serr_enable = -1ull; 176*0Sstevel@tonic-gate uint64_t pci_perr_fatal = -1ull; 177*0Sstevel@tonic-gate uint64_t pci_serr_fatal = -1ull; 178*0Sstevel@tonic-gate hrtime_t pci_intrpend_timeout = 5ll * NANOSEC; /* 5 seconds in nanoseconds */ 179*0Sstevel@tonic-gate hrtime_t pci_sync_buf_timeout = 1ll * NANOSEC; /* 1 second in nanoseconds */ 180*0Sstevel@tonic-gate hrtime_t pci_cdma_intr_timeout = 1ll * NANOSEC; /* consistent sync trigger */ 181*0Sstevel@tonic-gate uint32_t pci_cdma_intr_count = 15; /* num of pci_cdma_intr_timeout cycles */ 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate uint32_t pci_dto_fault_warn = CE_WARN; /* set to CE_IGNORE for no messages */ 184*0Sstevel@tonic-gate uint64_t pci_dto_intr_enable = 0; 185*0Sstevel@tonic-gate uint64_t pci_dto_count = 0; 186*0Sstevel@tonic-gate uint64_t pci_errtrig_pa = 0x0; 187*0Sstevel@tonic-gate 188*0Sstevel@tonic-gate /* 189*0Sstevel@tonic-gate * The following flag controls behavior of the ino handler routine 190*0Sstevel@tonic-gate * when multiple interrupts are attached to a single ino. Typically 191*0Sstevel@tonic-gate * this case would occur for the ino's assigned to the PCI bus slots 192*0Sstevel@tonic-gate * with multi-function devices or bus bridges. 193*0Sstevel@tonic-gate * 194*0Sstevel@tonic-gate * Setting the flag to zero causes the ino handler routine to return 195*0Sstevel@tonic-gate * after finding the first interrupt handler to claim the interrupt. 196*0Sstevel@tonic-gate * 197*0Sstevel@tonic-gate * Setting the flag to non-zero causes the ino handler routine to 198*0Sstevel@tonic-gate * return after making one complete pass through the interrupt 199*0Sstevel@tonic-gate * handlers. 200*0Sstevel@tonic-gate */ 201*0Sstevel@tonic-gate uint_t pci_check_all_handlers = 1; 202*0Sstevel@tonic-gate 203*0Sstevel@tonic-gate /* 204*0Sstevel@tonic-gate * The following value is the number of consecutive unclaimed interrupts that 205*0Sstevel@tonic-gate * will be tolerated for a particular ino_p before the interrupt is deemed to 206*0Sstevel@tonic-gate * be jabbering and is blocked. 207*0Sstevel@tonic-gate */ 208*0Sstevel@tonic-gate uint_t pci_unclaimed_intr_max = 20; 209*0Sstevel@tonic-gate 210*0Sstevel@tonic-gate ulong_t pci_iommu_dvma_end = 0xfffffffful; 211*0Sstevel@tonic-gate uint_t pci_lock_tlb = 0; 212*0Sstevel@tonic-gate uint64_t pci_dvma_debug_on = 0; 213*0Sstevel@tonic-gate uint64_t pci_dvma_debug_off = 0; 214*0Sstevel@tonic-gate uint32_t pci_dvma_debug_rec = 512; 215*0Sstevel@tonic-gate 216*0Sstevel@tonic-gate /* 217*0Sstevel@tonic-gate * dvma address space allocation cache variables 218*0Sstevel@tonic-gate */ 219*0Sstevel@tonic-gate uint_t pci_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 220*0Sstevel@tonic-gate uint_t pci_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 221*0Sstevel@tonic-gate #ifdef PCI_DMA_PROF 222*0Sstevel@tonic-gate uint_t pci_dvmaft_npages = 0; /* FT fail due npages */ 223*0Sstevel@tonic-gate uint_t pci_dvmaft_limit = 0; /* FT fail due limits */ 224*0Sstevel@tonic-gate uint_t pci_dvmaft_free = 0; /* FT free */ 225*0Sstevel@tonic-gate uint_t pci_dvmaft_success = 0; /* FT success */ 226*0Sstevel@tonic-gate uint_t pci_dvmaft_exhaust = 0; /* FT vmem fallback */ 227*0Sstevel@tonic-gate uint_t pci_dvma_vmem_alloc = 0; /* vmem alloc */ 228*0Sstevel@tonic-gate uint_t pci_dvma_vmem_xalloc = 0; /* vmem xalloc */ 229*0Sstevel@tonic-gate uint_t pci_dvma_vmem_xfree = 0; /* vmem xfree */ 230*0Sstevel@tonic-gate uint_t pci_dvma_vmem_free = 0; /* vmem free */ 231*0Sstevel@tonic-gate #endif 232*0Sstevel@tonic-gate uint_t pci_disable_fdvma = 0; 233*0Sstevel@tonic-gate 234*0Sstevel@tonic-gate uint_t pci_iommu_ctx_lock_failure = 0; 235*0Sstevel@tonic-gate 236*0Sstevel@tonic-gate /* 237*0Sstevel@tonic-gate * This flag preserves prom iommu settings by copying prom TSB entries 238*0Sstevel@tonic-gate * to corresponding kernel TSB entry locations. It should be removed 239*0Sstevel@tonic-gate * after the interface properties from obp have become default. 240*0Sstevel@tonic-gate */ 241*0Sstevel@tonic-gate uint_t pci_preserve_iommu_tsb = 1; 242*0Sstevel@tonic-gate 243*0Sstevel@tonic-gate /* 244*0Sstevel@tonic-gate * memory callback list id callback list for kmem_alloc failure clients 245*0Sstevel@tonic-gate */ 246*0Sstevel@tonic-gate uintptr_t pci_kmem_clid = 0; 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate /* 249*0Sstevel@tonic-gate * Perform a consistent-mode sync/flush during interrupt. 250*0Sstevel@tonic-gate */ 251*0Sstevel@tonic-gate uint_t pci_intr_dma_sync = 0; 252*0Sstevel@tonic-gate 253*0Sstevel@tonic-gate /* 254*0Sstevel@tonic-gate * This flag is used to enable max prefetch streaming cache mode 255*0Sstevel@tonic-gate * feature of XMITS. 256*0Sstevel@tonic-gate */ 257*0Sstevel@tonic-gate uint_t pci_xmits_sc_max_prf = 0; 258*0Sstevel@tonic-gate 259*0Sstevel@tonic-gate /* 260*0Sstevel@tonic-gate * This flag is used to enable pcix error reporting in XMITS. 261*0Sstevel@tonic-gate */ 262*0Sstevel@tonic-gate uint64_t xmits_error_intr_enable = -1ull; 263*0Sstevel@tonic-gate 264*0Sstevel@tonic-gate /* 265*0Sstevel@tonic-gate * Enable parity error recovery for xmits 266*0Sstevel@tonic-gate */ 267*0Sstevel@tonic-gate uint_t xmits_perr_recov_int_enable = 0; 268*0Sstevel@tonic-gate 269*0Sstevel@tonic-gate /* 270*0Sstevel@tonic-gate * This flag controls whether or not DVMA remap support is 271*0Sstevel@tonic-gate * enabled (currently, Schizo/XMITS only). 272*0Sstevel@tonic-gate */ 273*0Sstevel@tonic-gate int pci_dvma_remap_enabled = 0; 274*0Sstevel@tonic-gate 275*0Sstevel@tonic-gate /* 276*0Sstevel@tonic-gate * Serialize PCI relocations, since they are time critical. 277*0Sstevel@tonic-gate */ 278*0Sstevel@tonic-gate kthread_t *pci_reloc_thread = NULL; 279*0Sstevel@tonic-gate kmutex_t pci_reloc_mutex; 280*0Sstevel@tonic-gate kcondvar_t pci_reloc_cv; 281*0Sstevel@tonic-gate int pci_reloc_presuspend = 0; 282*0Sstevel@tonic-gate int pci_reloc_suspend = 0; 283*0Sstevel@tonic-gate id_t pci_dvma_cbid; 284*0Sstevel@tonic-gate id_t pci_fast_dvma_cbid; 285*0Sstevel@tonic-gate int pci_dma_panic_on_leak = 0; 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate /* 288*0Sstevel@tonic-gate * Set Outstanding Maximum Split Transactions. Legal settings are: 289*0Sstevel@tonic-gate * 0 = 1 Outstanding Transacation, 1 = 2, 2 = 3, 3 = 4, 4 = 8, 5 = 12, 290*0Sstevel@tonic-gate * 6 = 16, 7 = 32. 291*0Sstevel@tonic-gate */ 292*0Sstevel@tonic-gate uint_t xmits_max_transactions = 0; 293*0Sstevel@tonic-gate 294*0Sstevel@tonic-gate /* 295*0Sstevel@tonic-gate * Set Max Memory Read Byte Count. Legal settings are: 296*0Sstevel@tonic-gate * 0 = 512 Max Memory Read Bytes, 1 = 1024, 2 = 2048, 3 = 4096. 297*0Sstevel@tonic-gate */ 298*0Sstevel@tonic-gate uint_t xmits_max_read_bytes = 0; 299