1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * PCI PBM implementation: 31*0Sstevel@tonic-gate * initialization 32*0Sstevel@tonic-gate * Bus error interrupt handler 33*0Sstevel@tonic-gate */ 34*0Sstevel@tonic-gate 35*0Sstevel@tonic-gate #include <sys/types.h> 36*0Sstevel@tonic-gate #include <sys/kmem.h> 37*0Sstevel@tonic-gate #include <sys/spl.h> 38*0Sstevel@tonic-gate #include <sys/sysmacros.h> 39*0Sstevel@tonic-gate #include <sys/sunddi.h> 40*0Sstevel@tonic-gate #include <sys/fm/protocol.h> 41*0Sstevel@tonic-gate #include <sys/fm/util.h> 42*0Sstevel@tonic-gate #include <sys/machsystm.h> /* ldphysio() */ 43*0Sstevel@tonic-gate #include <sys/async.h> 44*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 45*0Sstevel@tonic-gate #include <sys/ontrap.h> 46*0Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 47*0Sstevel@tonic-gate #include <sys/membar.h> 48*0Sstevel@tonic-gate #include <sys/ivintr.h> 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate /*LINTLIBRARY*/ 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate static uint_t pbm_error_intr(caddr_t a); 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate /* The nexus interrupt priority values */ 55*0Sstevel@tonic-gate int pci_pil[] = {14, 14, 14, 14, 14, 14}; 56*0Sstevel@tonic-gate void 57*0Sstevel@tonic-gate pbm_create(pci_t *pci_p) 58*0Sstevel@tonic-gate { 59*0Sstevel@tonic-gate pbm_t *pbm_p; 60*0Sstevel@tonic-gate int i, len; 61*0Sstevel@tonic-gate int nrange = pci_p->pci_ranges_length / sizeof (pci_ranges_t); 62*0Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 63*0Sstevel@tonic-gate pci_ranges_t *rangep = pci_p->pci_ranges; 64*0Sstevel@tonic-gate uint64_t base_addr, last_addr; 65*0Sstevel@tonic-gate 66*0Sstevel@tonic-gate #ifdef lint 67*0Sstevel@tonic-gate dip = dip; 68*0Sstevel@tonic-gate #endif 69*0Sstevel@tonic-gate 70*0Sstevel@tonic-gate /* 71*0Sstevel@tonic-gate * Allocate a state structure for the PBM and cross-link it 72*0Sstevel@tonic-gate * to its per pci node state structure. 73*0Sstevel@tonic-gate */ 74*0Sstevel@tonic-gate pbm_p = (pbm_t *)kmem_zalloc(sizeof (pbm_t), KM_SLEEP); 75*0Sstevel@tonic-gate pci_p->pci_pbm_p = pbm_p; 76*0Sstevel@tonic-gate pbm_p->pbm_pci_p = pci_p; 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate len = snprintf(pbm_p->pbm_nameinst_str, 79*0Sstevel@tonic-gate sizeof (pbm_p->pbm_nameinst_str), 80*0Sstevel@tonic-gate "%s%d", NAMEINST(dip)); 81*0Sstevel@tonic-gate pbm_p->pbm_nameaddr_str = pbm_p->pbm_nameinst_str + ++len; 82*0Sstevel@tonic-gate (void) snprintf(pbm_p->pbm_nameaddr_str, 83*0Sstevel@tonic-gate sizeof (pbm_p->pbm_nameinst_str) - len, 84*0Sstevel@tonic-gate "%s@%s", NAMEADDR(dip)); 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate pci_pbm_setup(pbm_p); 87*0Sstevel@tonic-gate 88*0Sstevel@tonic-gate /* 89*0Sstevel@tonic-gate * Get this pbm's mem32 and mem64 segments to determine whether 90*0Sstevel@tonic-gate * a dma object originates from ths pbm. i.e. dev to dev dma 91*0Sstevel@tonic-gate */ 92*0Sstevel@tonic-gate /* Init all of our boundaries */ 93*0Sstevel@tonic-gate base_addr = -1ull; 94*0Sstevel@tonic-gate last_addr = 0ull; 95*0Sstevel@tonic-gate 96*0Sstevel@tonic-gate for (i = 0; i < nrange; i++, rangep++) { 97*0Sstevel@tonic-gate uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 98*0Sstevel@tonic-gate if (rng_type == PCI_ADDR_MEM32 || rng_type == PCI_ADDR_MEM64) { 99*0Sstevel@tonic-gate uint64_t rng_addr, rng_size; 100*0Sstevel@tonic-gate 101*0Sstevel@tonic-gate rng_addr = (uint64_t)rangep->parent_high << 32; 102*0Sstevel@tonic-gate rng_addr |= (uint64_t)rangep->parent_low; 103*0Sstevel@tonic-gate rng_size = (uint64_t)rangep->size_high << 32; 104*0Sstevel@tonic-gate rng_size |= (uint64_t)rangep->size_low; 105*0Sstevel@tonic-gate base_addr = MIN(rng_addr, base_addr); 106*0Sstevel@tonic-gate last_addr = MAX(rng_addr + rng_size, last_addr); 107*0Sstevel@tonic-gate } 108*0Sstevel@tonic-gate } 109*0Sstevel@tonic-gate pbm_p->pbm_base_pfn = mmu_btop(base_addr); 110*0Sstevel@tonic-gate pbm_p->pbm_last_pfn = mmu_btop(last_addr); 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate DEBUG4(DBG_ATTACH, dip, 113*0Sstevel@tonic-gate "pbm_create: ctrl=%x, afsr=%x, afar=%x, diag=%x\n", 114*0Sstevel@tonic-gate pbm_p->pbm_ctrl_reg, pbm_p->pbm_async_flt_status_reg, 115*0Sstevel@tonic-gate pbm_p->pbm_async_flt_addr_reg, pbm_p->pbm_diag_reg); 116*0Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_create: conf=%x\n", 117*0Sstevel@tonic-gate pbm_p->pbm_config_header); 118*0Sstevel@tonic-gate 119*0Sstevel@tonic-gate /* 120*0Sstevel@tonic-gate * Register a function to disable pbm error interrupts during a panic. 121*0Sstevel@tonic-gate */ 122*0Sstevel@tonic-gate bus_func_register(BF_TYPE_ERRDIS, 123*0Sstevel@tonic-gate (busfunc_t)pbm_disable_pci_errors, pbm_p); 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate /* 126*0Sstevel@tonic-gate * create the interrupt-priorities property if it doesn't 127*0Sstevel@tonic-gate * already exist to provide a hint as to the PIL level for 128*0Sstevel@tonic-gate * our interrupt. 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate if (ddi_getproplen(DDI_DEV_T_ANY, dip, 131*0Sstevel@tonic-gate DDI_PROP_DONTPASS, "interrupt-priorities", 132*0Sstevel@tonic-gate &len) != DDI_PROP_SUCCESS) { 133*0Sstevel@tonic-gate /* Create the interrupt-priorities property. */ 134*0Sstevel@tonic-gate (void) ddi_prop_create(DDI_DEV_T_NONE, dip, 135*0Sstevel@tonic-gate DDI_PROP_CANSLEEP, "interrupt-priorities", 136*0Sstevel@tonic-gate (caddr_t)pci_pil, sizeof (pci_pil)); 137*0Sstevel@tonic-gate } 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate pbm_configure(pbm_p); 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate /* 142*0Sstevel@tonic-gate * Determine if we need to apply the Sun Fire 15k AXQ/PIO 143*0Sstevel@tonic-gate * workaround. 144*0Sstevel@tonic-gate */ 145*0Sstevel@tonic-gate pci_axq_pio_limit(pbm_p); 146*0Sstevel@tonic-gate } 147*0Sstevel@tonic-gate 148*0Sstevel@tonic-gate int 149*0Sstevel@tonic-gate pbm_register_intr(pbm_t *pbm_p) 150*0Sstevel@tonic-gate { 151*0Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 152*0Sstevel@tonic-gate uint32_t mondo; 153*0Sstevel@tonic-gate int r = DDI_SUCCESS; 154*0Sstevel@tonic-gate 155*0Sstevel@tonic-gate ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 156*0Sstevel@tonic-gate 157*0Sstevel@tonic-gate /* 158*0Sstevel@tonic-gate * Install the PCI error interrupt handler. 159*0Sstevel@tonic-gate */ 160*0Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 161*0Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 162*0Sstevel@tonic-gate 163*0Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_PBM], pbm_error_intr, 164*0Sstevel@tonic-gate (caddr_t)pci_p, NULL) == 0); 165*0Sstevel@tonic-gate 166*0Sstevel@tonic-gate pbm_p->pbm_iblock_cookie = (void *)pci_pil[CBNINTR_PBM]; 167*0Sstevel@tonic-gate 168*0Sstevel@tonic-gate /* 169*0Sstevel@tonic-gate * Create the pokefault mutex at the PIL below the error interrupt. 170*0Sstevel@tonic-gate */ 171*0Sstevel@tonic-gate mutex_init(&pbm_p->pbm_pokefault_mutex, NULL, MUTEX_DRIVER, 172*0Sstevel@tonic-gate (void *)ipltospl(spltoipl((int)pbm_p->pbm_iblock_cookie) - 1)); 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate if (!r) 175*0Sstevel@tonic-gate r = pci_pbm_add_intr(pci_p); 176*0Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_PBM_OBJ, PCI_OBJ_INTR_ADD, r)); 177*0Sstevel@tonic-gate } 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate void 180*0Sstevel@tonic-gate pbm_destroy(pci_t *pci_p) 181*0Sstevel@tonic-gate { 182*0Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 183*0Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 184*0Sstevel@tonic-gate uint32_t mondo; 185*0Sstevel@tonic-gate 186*0Sstevel@tonic-gate DEBUG0(DBG_DETACH, pci_p->pci_dip, "pbm_destroy:\n"); 187*0Sstevel@tonic-gate 188*0Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 189*0Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 190*0Sstevel@tonic-gate 191*0Sstevel@tonic-gate /* 192*0Sstevel@tonic-gate * Free the pokefault mutex. 193*0Sstevel@tonic-gate */ 194*0Sstevel@tonic-gate mutex_destroy(&pbm_p->pbm_pokefault_mutex); 195*0Sstevel@tonic-gate 196*0Sstevel@tonic-gate /* 197*0Sstevel@tonic-gate * Remove the error interrupt and consistent dma sync handler. 198*0Sstevel@tonic-gate */ 199*0Sstevel@tonic-gate intr_dist_rem(pbm_intr_dist, pbm_p); 200*0Sstevel@tonic-gate pci_pbm_rem_intr(pci_p); 201*0Sstevel@tonic-gate ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_WAIT); 202*0Sstevel@tonic-gate rem_ivintr(mondo, NULL); 203*0Sstevel@tonic-gate 204*0Sstevel@tonic-gate /* 205*0Sstevel@tonic-gate * Remove the error disable function. 206*0Sstevel@tonic-gate */ 207*0Sstevel@tonic-gate bus_func_unregister(BF_TYPE_ERRDIS, 208*0Sstevel@tonic-gate (busfunc_t)pbm_disable_pci_errors, pbm_p); 209*0Sstevel@tonic-gate 210*0Sstevel@tonic-gate pci_pbm_teardown(pbm_p); 211*0Sstevel@tonic-gate 212*0Sstevel@tonic-gate /* 213*0Sstevel@tonic-gate * Free the pbm state structure. 214*0Sstevel@tonic-gate */ 215*0Sstevel@tonic-gate kmem_free(pbm_p, sizeof (pbm_t)); 216*0Sstevel@tonic-gate pci_p->pci_pbm_p = NULL; 217*0Sstevel@tonic-gate } 218*0Sstevel@tonic-gate 219*0Sstevel@tonic-gate static uint_t 220*0Sstevel@tonic-gate pbm_error_intr(caddr_t a) 221*0Sstevel@tonic-gate { 222*0Sstevel@tonic-gate pci_t *pci_p = (pci_t *)a; 223*0Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 224*0Sstevel@tonic-gate ddi_fm_error_t derr; 225*0Sstevel@tonic-gate int err = DDI_FM_OK; 226*0Sstevel@tonic-gate on_trap_data_t *otp = pbm_p->pbm_ontrap_data; 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate bzero(&derr, sizeof (ddi_fm_error_t)); 229*0Sstevel@tonic-gate derr.fme_version = DDI_FME_VERSION; 230*0Sstevel@tonic-gate mutex_enter(&pci_p->pci_common_p->pci_fm_mutex); 231*0Sstevel@tonic-gate if ((otp != NULL) && (otp->ot_prot & OT_DATA_ACCESS)) { 232*0Sstevel@tonic-gate /* 233*0Sstevel@tonic-gate * ddi_poke protection, check nexus and children for 234*0Sstevel@tonic-gate * expected errors. 235*0Sstevel@tonic-gate */ 236*0Sstevel@tonic-gate otp->ot_trap |= OT_DATA_ACCESS; 237*0Sstevel@tonic-gate membar_sync(); 238*0Sstevel@tonic-gate derr.fme_flag = DDI_FM_ERR_POKE; 239*0Sstevel@tonic-gate err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 240*0Sstevel@tonic-gate PCI_INTR_CALL); 241*0Sstevel@tonic-gate } else if (pbm_p->pbm_excl_handle != NULL) { 242*0Sstevel@tonic-gate /* 243*0Sstevel@tonic-gate * cautious write protection, protected from all errors. 244*0Sstevel@tonic-gate */ 245*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pbm_p->pbm_pokefault_mutex)); 246*0Sstevel@tonic-gate ddi_fm_acc_err_get(pbm_p->pbm_excl_handle, &derr, 247*0Sstevel@tonic-gate DDI_FME_VERSION); 248*0Sstevel@tonic-gate derr.fme_flag = DDI_FM_ERR_EXPECTED; 249*0Sstevel@tonic-gate derr.fme_acc_handle = pbm_p->pbm_excl_handle; 250*0Sstevel@tonic-gate err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 251*0Sstevel@tonic-gate PCI_INTR_CALL); 252*0Sstevel@tonic-gate } else if (pci_check_error(pci_p) != 0) { 253*0Sstevel@tonic-gate /* 254*0Sstevel@tonic-gate * unprotected error, check for all errors. 255*0Sstevel@tonic-gate */ 256*0Sstevel@tonic-gate if (pci_errtrig_pa) 257*0Sstevel@tonic-gate (void) ldphysio(pci_errtrig_pa); 258*0Sstevel@tonic-gate derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 259*0Sstevel@tonic-gate err = pci_pbm_err_handler(pci_p->pci_dip, &derr, (void *)pci_p, 260*0Sstevel@tonic-gate PCI_INTR_CALL); 261*0Sstevel@tonic-gate } 262*0Sstevel@tonic-gate 263*0Sstevel@tonic-gate if (err == DDI_FM_FATAL) { 264*0Sstevel@tonic-gate if (pci_panic_on_fatal_errors) { 265*0Sstevel@tonic-gate mutex_exit(&pci_p->pci_common_p->pci_fm_mutex); 266*0Sstevel@tonic-gate fm_panic("%s-%d: Fatal PCI bus error(s)\n", 267*0Sstevel@tonic-gate ddi_driver_name(pci_p->pci_dip), 268*0Sstevel@tonic-gate ddi_get_instance(pci_p->pci_dip)); 269*0Sstevel@tonic-gate } 270*0Sstevel@tonic-gate } 271*0Sstevel@tonic-gate 272*0Sstevel@tonic-gate mutex_exit(&pci_p->pci_common_p->pci_fm_mutex); 273*0Sstevel@tonic-gate ib_nintr_clear(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_PBM]); 274*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 275*0Sstevel@tonic-gate } 276*0Sstevel@tonic-gate 277*0Sstevel@tonic-gate void 278*0Sstevel@tonic-gate pbm_suspend(pbm_t *pbm_p) 279*0Sstevel@tonic-gate { 280*0Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 281*0Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM]; 282*0Sstevel@tonic-gate pbm_p->pbm_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 283*0Sstevel@tonic-gate 284*0Sstevel@tonic-gate pci_pbm_suspend(pci_p); 285*0Sstevel@tonic-gate } 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate void 288*0Sstevel@tonic-gate pbm_resume(pbm_t *pbm_p) 289*0Sstevel@tonic-gate { 290*0Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 291*0Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_PBM]; 292*0Sstevel@tonic-gate 293*0Sstevel@tonic-gate ib_nintr_clear(pci_p->pci_ib_p, ino); 294*0Sstevel@tonic-gate *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_imr_save; 295*0Sstevel@tonic-gate 296*0Sstevel@tonic-gate pci_pbm_resume(pci_p); 297*0Sstevel@tonic-gate } 298*0Sstevel@tonic-gate 299*0Sstevel@tonic-gate void 300*0Sstevel@tonic-gate pbm_intr_dist(void *arg) 301*0Sstevel@tonic-gate { 302*0Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)arg; 303*0Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 304*0Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 305*0Sstevel@tonic-gate ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_PBM]); 306*0Sstevel@tonic-gate 307*0Sstevel@tonic-gate mutex_enter(&ib_p->ib_intr_lock); 308*0Sstevel@tonic-gate ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 309*0Sstevel@tonic-gate pci_pbm_intr_dist(pbm_p); 310*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_intr_lock); 311*0Sstevel@tonic-gate } 312*0Sstevel@tonic-gate 313*0Sstevel@tonic-gate /* 314*0Sstevel@tonic-gate * Function used to log PBM AFSR register bits and to lookup and fault 315*0Sstevel@tonic-gate * handle associated with PBM AFAR register. Called by pci_pbm_err_handler with 316*0Sstevel@tonic-gate * pci_fm_mutex held. 317*0Sstevel@tonic-gate */ 318*0Sstevel@tonic-gate int 319*0Sstevel@tonic-gate pbm_afsr_report(dev_info_t *dip, uint64_t fme_ena, pbm_errstate_t *pbm_err_p) 320*0Sstevel@tonic-gate { 321*0Sstevel@tonic-gate int fatal = 0; 322*0Sstevel@tonic-gate int ret = 0; 323*0Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 324*0Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 325*0Sstevel@tonic-gate pci_target_err_t tgt_err; 326*0Sstevel@tonic-gate 327*0Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 328*0Sstevel@tonic-gate 329*0Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 330*0Sstevel@tonic-gate (void) pci_pbm_classify(pbm_err_p); 331*0Sstevel@tonic-gate 332*0Sstevel@tonic-gate pci_format_addr(dip, &pbm_err_p->pbm_pci.pci_pa, pbm_err_p->pbm_afsr); 333*0Sstevel@tonic-gate 334*0Sstevel@tonic-gate if (pbm_err_p->pbm_log == FM_LOG_PBM) 335*0Sstevel@tonic-gate pbm_ereport_post(dip, fme_ena, pbm_err_p); 336*0Sstevel@tonic-gate 337*0Sstevel@tonic-gate /* 338*0Sstevel@tonic-gate * Lookup and fault errant handle 339*0Sstevel@tonic-gate */ 340*0Sstevel@tonic-gate if (((ret = pci_handle_lookup(dip, ACC_HANDLE, fme_ena, 341*0Sstevel@tonic-gate (void *)&pbm_err_p->pbm_pci.pci_pa)) 342*0Sstevel@tonic-gate == DDI_FM_FATAL) || (ret == DDI_FM_UNKNOWN)) { 343*0Sstevel@tonic-gate fatal++; 344*0Sstevel@tonic-gate } 345*0Sstevel@tonic-gate 346*0Sstevel@tonic-gate /* 347*0Sstevel@tonic-gate * queue target ereport if appropriate 348*0Sstevel@tonic-gate */ 349*0Sstevel@tonic-gate if (pbm_err_p->pbm_terr_class) { 350*0Sstevel@tonic-gate tgt_err.tgt_err_ena = fme_ena; 351*0Sstevel@tonic-gate tgt_err.tgt_err_class = pbm_err_p->pbm_terr_class; 352*0Sstevel@tonic-gate if (pbm_err_p->pbm_log == FM_LOG_PCI) 353*0Sstevel@tonic-gate tgt_err.tgt_bridge_type = "pci"; 354*0Sstevel@tonic-gate else 355*0Sstevel@tonic-gate tgt_err.tgt_bridge_type = pbm_err_p->pbm_bridge_type; 356*0Sstevel@tonic-gate tgt_err.tgt_err_addr = pbm_err_p->pbm_pci.pci_pa; 357*0Sstevel@tonic-gate errorq_dispatch(pci_target_queue, (void *)&tgt_err, 358*0Sstevel@tonic-gate sizeof (pci_target_err_t), ERRORQ_ASYNC); 359*0Sstevel@tonic-gate } 360*0Sstevel@tonic-gate 361*0Sstevel@tonic-gate /* 362*0Sstevel@tonic-gate * We are currently not dealing with the multiple error 363*0Sstevel@tonic-gate * case, for any secondary errors we will panic. 364*0Sstevel@tonic-gate */ 365*0Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_SECONDARY; 366*0Sstevel@tonic-gate if (pci_pbm_classify(pbm_err_p)) { 367*0Sstevel@tonic-gate fatal++; 368*0Sstevel@tonic-gate if (pbm_err_p->pbm_log == FM_LOG_PBM) 369*0Sstevel@tonic-gate pbm_ereport_post(dip, fme_ena, pbm_err_p); 370*0Sstevel@tonic-gate } 371*0Sstevel@tonic-gate 372*0Sstevel@tonic-gate if (fatal) 373*0Sstevel@tonic-gate return (DDI_FM_FATAL); 374*0Sstevel@tonic-gate 375*0Sstevel@tonic-gate return (DDI_FM_NONFATAL); 376*0Sstevel@tonic-gate } 377