1*0Sstevel@tonic-gate/* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate/* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate#pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate/* 30*0Sstevel@tonic-gate * Assembly language support for physical big/little endian access of pcitool 31*0Sstevel@tonic-gate * in the PCI drivers. 32*0Sstevel@tonic-gate */ 33*0Sstevel@tonic-gate 34*0Sstevel@tonic-gate#include <sys/asm_linkage.h> 35*0Sstevel@tonic-gate#include <sys/machthread.h> 36*0Sstevel@tonic-gate#include <sys/privregs.h> 37*0Sstevel@tonic-gate 38*0Sstevel@tonic-gate/*LINTLIBRARY*/ 39*0Sstevel@tonic-gate 40*0Sstevel@tonic-gate#if defined(lint) 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate/*ARGSUSED*/ 43*0Sstevel@tonic-gateint pci_do_phys_peek(size_t size, uint64_t paddr, uint64_t *value, int type) 44*0Sstevel@tonic-gate{ return (0); } 45*0Sstevel@tonic-gate 46*0Sstevel@tonic-gateint pci_do_phys_poke(size_t size, uint64_t paddr, uint64_t *value, int type) 47*0Sstevel@tonic-gate{ return (0); } 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate#else /* lint */ 50*0Sstevel@tonic-gate 51*0Sstevel@tonic-gate! pci_do_phys_peek: Do physical address read. 52*0Sstevel@tonic-gate! 53*0Sstevel@tonic-gate! %o0 is size in bytes - Must be 8, 4, 2 or 1. Invalid sizes default to 1. 54*0Sstevel@tonic-gate! %o1 is address to read 55*0Sstevel@tonic-gate! %o2 is address to save value into 56*0Sstevel@tonic-gate! %o3 is 0 for little endian, non-zero for big endian 57*0Sstevel@tonic-gate! 58*0Sstevel@tonic-gate! To be called from an on_trap environment. 59*0Sstevel@tonic-gate! Interrupts will be disabled for the duration of the read, to prevent 60*0Sstevel@tonic-gate! an interrupt from raising the trap level to 1 and then a possible 61*0Sstevel@tonic-gate! data access exception being delivered while the trap level > 0. 62*0Sstevel@tonic-gate! 63*0Sstevel@tonic-gate! Assumes alignment is correct. 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate ENTRY(pci_do_phys_peek) 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate rdpr %pstate, %o4 ! Disable interrupts if not already 68*0Sstevel@tonic-gate andcc %o4, PSTATE_IE, %g2 ! Save original state first 69*0Sstevel@tonic-gate bz .peek_ints_disabled 70*0Sstevel@tonic-gate nop 71*0Sstevel@tonic-gate wrpr %o4, PSTATE_IE, %pstate 72*0Sstevel@tonic-gate.peek_ints_disabled: 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate tst %o3 ! Set up %asi with modifier for 75*0Sstevel@tonic-gate movz %xcc, ASI_IOL, %g1 ! Big/little endian physical space 76*0Sstevel@tonic-gate movnz %xcc, ASI_IO, %g1 77*0Sstevel@tonic-gate mov %g1, %asi 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate cmp %o0, 8 ! 64-bit? 80*0Sstevel@tonic-gate bne .peek_int 81*0Sstevel@tonic-gate cmp %o0, 4 ! 32-bit? 82*0Sstevel@tonic-gate ldxa [%o1]%asi, %g1 83*0Sstevel@tonic-gate ba .peekdone 84*0Sstevel@tonic-gate stx %g1, [%o2] 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate.peek_int: 87*0Sstevel@tonic-gate bne .peek_half 88*0Sstevel@tonic-gate cmp %o0, 2 ! 16-bit? 89*0Sstevel@tonic-gate lduwa [%o1]%asi, %g1 90*0Sstevel@tonic-gate ba .peekdone 91*0Sstevel@tonic-gate stuw %g1, [%o2] 92*0Sstevel@tonic-gate 93*0Sstevel@tonic-gate.peek_half: 94*0Sstevel@tonic-gate bne .peek_byte 95*0Sstevel@tonic-gate nop 96*0Sstevel@tonic-gate lduha [%o1]%asi, %g1 97*0Sstevel@tonic-gate ba .peekdone 98*0Sstevel@tonic-gate stuh %g1, [%o2] 99*0Sstevel@tonic-gate 100*0Sstevel@tonic-gate.peek_byte: 101*0Sstevel@tonic-gate lduba [%o1]%asi, %g1 ! 8-bit! 102*0Sstevel@tonic-gate stub %g1, [%o2] 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate.peekdone: 105*0Sstevel@tonic-gate membar #Sync ! Make sure the loads take 106*0Sstevel@tonic-gate tst %g2 ! No need to reenable interrupts 107*0Sstevel@tonic-gate bz .peek_ints_done ! if not enabled at entry 108*0Sstevel@tonic-gate rdpr %pstate, %o4 109*0Sstevel@tonic-gate wrpr %o4, PSTATE_IE, %pstate 110*0Sstevel@tonic-gate.peek_ints_done: 111*0Sstevel@tonic-gate mov %g0, %o0 112*0Sstevel@tonic-gate retl 113*0Sstevel@tonic-gate nop 114*0Sstevel@tonic-gate SET_SIZE(pci_do_phys_peek) 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate 117*0Sstevel@tonic-gate! pci_do_phys_poke: Do physical address write. 118*0Sstevel@tonic-gate! 119*0Sstevel@tonic-gate! %o0 is size in bytes - Must be 8, 4, 2 or 1. Invalid sizes default to 1. 120*0Sstevel@tonic-gate! %o1 is address to write to 121*0Sstevel@tonic-gate! %o2 is address to read from 122*0Sstevel@tonic-gate! %o3 is 0 for little endian, non-zero for big endian 123*0Sstevel@tonic-gate! 124*0Sstevel@tonic-gate! Always returns success (0) in %o0 125*0Sstevel@tonic-gate! 126*0Sstevel@tonic-gate! Assumes alignment is correct and that on_trap handling has been installed 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate ENTRY(pci_do_phys_poke) 129*0Sstevel@tonic-gate 130*0Sstevel@tonic-gate tst %o3 131*0Sstevel@tonic-gate bz .poke_asi_set 132*0Sstevel@tonic-gate mov ASI_IOL, %asi 133*0Sstevel@tonic-gate mov ASI_IO, %asi 134*0Sstevel@tonic-gate.poke_asi_set: 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate cmp %o0, 8 ! 64 bit? 137*0Sstevel@tonic-gate bne .poke_int 138*0Sstevel@tonic-gate cmp %o0, 4 ! 32-bit? 139*0Sstevel@tonic-gate ldx [%o2], %g1 140*0Sstevel@tonic-gate ba .pokedone 141*0Sstevel@tonic-gate stxa %g1, [%o1]%asi 142*0Sstevel@tonic-gate 143*0Sstevel@tonic-gate.poke_int: 144*0Sstevel@tonic-gate bne .poke_half 145*0Sstevel@tonic-gate cmp %o0, 2 ! 16-bit? 146*0Sstevel@tonic-gate lduw [%o2], %g1 147*0Sstevel@tonic-gate ba .pokedone 148*0Sstevel@tonic-gate stuwa %g1, [%o1]%asi 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate.poke_half: 151*0Sstevel@tonic-gate bne .poke_byte 152*0Sstevel@tonic-gate nop 153*0Sstevel@tonic-gate lduh [%o2], %g1 154*0Sstevel@tonic-gate ba .pokedone 155*0Sstevel@tonic-gate stuha %g1, [%o1]%asi 156*0Sstevel@tonic-gate 157*0Sstevel@tonic-gate.poke_byte: 158*0Sstevel@tonic-gate ldub [%o2], %g1 ! 8-bit! 159*0Sstevel@tonic-gate stuba %g1, [%o1]%asi 160*0Sstevel@tonic-gate 161*0Sstevel@tonic-gate.pokedone: 162*0Sstevel@tonic-gate membar #Sync 163*0Sstevel@tonic-gate retl 164*0Sstevel@tonic-gate mov %g0, %o0 165*0Sstevel@tonic-gate SET_SIZE(pci_do_phys_poke) 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate#endif 168