1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2000-2002 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate #include <sys/param.h>
30*0Sstevel@tonic-gate #include <sys/systm.h>
31*0Sstevel@tonic-gate #include <sys/sunddi.h>
32*0Sstevel@tonic-gate #include <sys/esunddi.h>
33*0Sstevel@tonic-gate #include <sys/ddi.h>
34*0Sstevel@tonic-gate
35*0Sstevel@tonic-gate #include <sys/platform_module.h>
36*0Sstevel@tonic-gate #include <sys/errno.h>
37*0Sstevel@tonic-gate
38*0Sstevel@tonic-gate void
startup_platform(void)39*0Sstevel@tonic-gate startup_platform(void)
40*0Sstevel@tonic-gate {
41*0Sstevel@tonic-gate }
42*0Sstevel@tonic-gate
43*0Sstevel@tonic-gate int
set_platform_tsb_spares()44*0Sstevel@tonic-gate set_platform_tsb_spares()
45*0Sstevel@tonic-gate {
46*0Sstevel@tonic-gate return (0);
47*0Sstevel@tonic-gate }
48*0Sstevel@tonic-gate
49*0Sstevel@tonic-gate void
set_platform_defaults(void)50*0Sstevel@tonic-gate set_platform_defaults(void)
51*0Sstevel@tonic-gate {
52*0Sstevel@tonic-gate }
53*0Sstevel@tonic-gate
54*0Sstevel@tonic-gate
55*0Sstevel@tonic-gate /*
56*0Sstevel@tonic-gate * Definitions for accessing the pci config space of the isa node
57*0Sstevel@tonic-gate * of Southbridge.
58*0Sstevel@tonic-gate */
59*0Sstevel@tonic-gate #define GROVER_ISA_PATHNAME "/pci@1f,0/isa@7"
60*0Sstevel@tonic-gate ddi_acc_handle_t grover_isa_handle; /* handle for isa pci space */
61*0Sstevel@tonic-gate
62*0Sstevel@tonic-gate void
load_platform_drivers(void)63*0Sstevel@tonic-gate load_platform_drivers(void)
64*0Sstevel@tonic-gate {
65*0Sstevel@tonic-gate dev_info_t *dip; /* dip of the isa driver */
66*0Sstevel@tonic-gate
67*0Sstevel@tonic-gate
68*0Sstevel@tonic-gate if (i_ddi_attach_hw_nodes("power") != DDI_SUCCESS)
69*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"power\" driver.");
70*0Sstevel@tonic-gate
71*0Sstevel@tonic-gate /*
72*0Sstevel@tonic-gate * It is OK to return error because 'us' driver is not available
73*0Sstevel@tonic-gate * in all clusters (e.g. missing in Core cluster).
74*0Sstevel@tonic-gate */
75*0Sstevel@tonic-gate (void) i_ddi_attach_hw_nodes("us");
76*0Sstevel@tonic-gate
77*0Sstevel@tonic-gate if (i_ddi_attach_hw_nodes("grbeep") != DDI_SUCCESS)
78*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"beep\" driver.");
79*0Sstevel@tonic-gate
80*0Sstevel@tonic-gate /*
81*0Sstevel@tonic-gate * Install Isa driver. This is required for the southbridge IDE
82*0Sstevel@tonic-gate * workaround - to reset the IDE channel during IDE bus reset.
83*0Sstevel@tonic-gate * Panic the system in case ISA driver could not be loaded or
84*0Sstevel@tonic-gate * any problem in accessing its pci config space. Since the register
85*0Sstevel@tonic-gate * to reset the channel for IDE is in ISA config space!.
86*0Sstevel@tonic-gate */
87*0Sstevel@tonic-gate
88*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(GROVER_ISA_PATHNAME, 0);
89*0Sstevel@tonic-gate if (dip == NULL) {
90*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not install the isa driver\n");
91*0Sstevel@tonic-gate return;
92*0Sstevel@tonic-gate }
93*0Sstevel@tonic-gate
94*0Sstevel@tonic-gate if (pci_config_setup(dip, &grover_isa_handle) != DDI_SUCCESS) {
95*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not get the config space of isa\n");
96*0Sstevel@tonic-gate return;
97*0Sstevel@tonic-gate }
98*0Sstevel@tonic-gate }
99*0Sstevel@tonic-gate
100*0Sstevel@tonic-gate /*
101*0Sstevel@tonic-gate * This routine provides a workaround for a bug in the SB chip which
102*0Sstevel@tonic-gate * can cause data corruption. Will be invoked from the IDE HBA driver for
103*0Sstevel@tonic-gate * Acer SouthBridge at the time of IDE bus reset.
104*0Sstevel@tonic-gate */
105*0Sstevel@tonic-gate /*ARGSUSED*/
106*0Sstevel@tonic-gate int
plat_ide_chipreset(dev_info_t * dip,int chno)107*0Sstevel@tonic-gate plat_ide_chipreset(dev_info_t *dip, int chno)
108*0Sstevel@tonic-gate {
109*0Sstevel@tonic-gate uint8_t val;
110*0Sstevel@tonic-gate int ret = DDI_SUCCESS;
111*0Sstevel@tonic-gate
112*0Sstevel@tonic-gate val = pci_config_get8(grover_isa_handle, 0x58);
113*0Sstevel@tonic-gate /*
114*0Sstevel@tonic-gate * The dip passed as the argument is not used for grover.
115*0Sstevel@tonic-gate * This will be needed for platforms which have multiple on-board SB,
116*0Sstevel@tonic-gate * The dip passed will be used to match the corresponding ISA node.
117*0Sstevel@tonic-gate */
118*0Sstevel@tonic-gate switch (chno) {
119*0Sstevel@tonic-gate case 0:
120*0Sstevel@tonic-gate /*
121*0Sstevel@tonic-gate * First disable the primary channel then re-enable it.
122*0Sstevel@tonic-gate * As per ALI no wait should be required in between have
123*0Sstevel@tonic-gate * given 1ms delay in between to be on safer side.
124*0Sstevel@tonic-gate * bit 2 of register 0x58 when 0 disable the channel 0.
125*0Sstevel@tonic-gate * bit 2 of register 0x58 when 1 enables the channel 0.
126*0Sstevel@tonic-gate */
127*0Sstevel@tonic-gate pci_config_put8(grover_isa_handle, 0x58, val & 0xFB);
128*0Sstevel@tonic-gate drv_usecwait(1000);
129*0Sstevel@tonic-gate pci_config_put8(grover_isa_handle, 0x58, val);
130*0Sstevel@tonic-gate break;
131*0Sstevel@tonic-gate case 1:
132*0Sstevel@tonic-gate /*
133*0Sstevel@tonic-gate * bit 3 of register 0x58 when 0 disable the channel 1.
134*0Sstevel@tonic-gate * bit 3 of register 0x58 when 1 enables the channel 1.
135*0Sstevel@tonic-gate */
136*0Sstevel@tonic-gate pci_config_put8(grover_isa_handle, 0x58, val & 0xF7);
137*0Sstevel@tonic-gate drv_usecwait(1000);
138*0Sstevel@tonic-gate pci_config_put8(grover_isa_handle, 0x58, val);
139*0Sstevel@tonic-gate break;
140*0Sstevel@tonic-gate default:
141*0Sstevel@tonic-gate /*
142*0Sstevel@tonic-gate * Unknown channel number passed. Return failure.
143*0Sstevel@tonic-gate */
144*0Sstevel@tonic-gate ret = DDI_FAILURE;
145*0Sstevel@tonic-gate }
146*0Sstevel@tonic-gate
147*0Sstevel@tonic-gate return (ret);
148*0Sstevel@tonic-gate }
149*0Sstevel@tonic-gate
150*0Sstevel@tonic-gate
151*0Sstevel@tonic-gate
152*0Sstevel@tonic-gate /*ARGSUSED*/
153*0Sstevel@tonic-gate int
plat_cpu_poweron(struct cpu * cp)154*0Sstevel@tonic-gate plat_cpu_poweron(struct cpu *cp)
155*0Sstevel@tonic-gate {
156*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
157*0Sstevel@tonic-gate }
158*0Sstevel@tonic-gate
159*0Sstevel@tonic-gate /*ARGSUSED*/
160*0Sstevel@tonic-gate int
plat_cpu_poweroff(struct cpu * cp)161*0Sstevel@tonic-gate plat_cpu_poweroff(struct cpu *cp)
162*0Sstevel@tonic-gate {
163*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
164*0Sstevel@tonic-gate }
165*0Sstevel@tonic-gate
166*0Sstevel@tonic-gate /*ARGSUSED*/
167*0Sstevel@tonic-gate void
plat_freelist_process(int mnode)168*0Sstevel@tonic-gate plat_freelist_process(int mnode)
169*0Sstevel@tonic-gate {
170*0Sstevel@tonic-gate }
171*0Sstevel@tonic-gate
172*0Sstevel@tonic-gate char *platform_module_list[] = {
173*0Sstevel@tonic-gate "grppm",
174*0Sstevel@tonic-gate (char *)0
175*0Sstevel@tonic-gate };
176*0Sstevel@tonic-gate
177*0Sstevel@tonic-gate /*ARGSUSED*/
178*0Sstevel@tonic-gate void
plat_tod_fault(enum tod_fault_type tod_bad)179*0Sstevel@tonic-gate plat_tod_fault(enum tod_fault_type tod_bad)
180*0Sstevel@tonic-gate {
181*0Sstevel@tonic-gate }
182