1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1999-2001 by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate /* 28*0Sstevel@tonic-gate * Platform Power Management 29*0Sstevel@tonic-gate * 30*0Sstevel@tonic-gate * Register and bit definitions of the power-related parts 31*0Sstevel@tonic-gate */ 32*0Sstevel@tonic-gate 33*0Sstevel@tonic-gate #ifndef _SYS_XCALPPM_REG_H 34*0Sstevel@tonic-gate #define _SYS_XCALPPM_REG_H 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 37*0Sstevel@tonic-gate 38*0Sstevel@tonic-gate #ifdef __cplusplus 39*0Sstevel@tonic-gate extern "C" { 40*0Sstevel@tonic-gate #endif 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate /* 43*0Sstevel@tonic-gate * Registers accessed by the ppm driver. These registers actually come 44*0Sstevel@tonic-gate * from different ASICs on the system and are collected for us 45*0Sstevel@tonic-gate * by the prom into a single device node. These registers are: 46*0Sstevel@tonic-gate * 47*0Sstevel@tonic-gate * BBC E* Control Register (other registers like E* Assert Change Time 48*0Sstevel@tonic-gate * or E* PLL Settle Time are offseted from this address) 49*0Sstevel@tonic-gate * Mode Auxio Register 50*0Sstevel@tonic-gate * SuperI/O Configuration Register 51*0Sstevel@tonic-gate * SuperI/O GPIO Registers 52*0Sstevel@tonic-gate */ 53*0Sstevel@tonic-gate struct xcppmreg { 54*0Sstevel@tonic-gate volatile uint16_t *bbc_estar_ctrl; /* set cpu clock rate */ 55*0Sstevel@tonic-gate volatile uint32_t *bbc_assert_change; /* set t1 cpu trans time */ 56*0Sstevel@tonic-gate volatile uint32_t *bbc_pll_settle; /* set t4 cpu trans time */ 57*0Sstevel@tonic-gate volatile uint32_t *rio_mode_auxio; /* transition cpu clock */ 58*0Sstevel@tonic-gate volatile uint8_t *gpio_bank_sel_index; /* index GPIO bank sel. */ 59*0Sstevel@tonic-gate volatile uint8_t *gpio_bank_sel_data; /* data GPIO bank select */ 60*0Sstevel@tonic-gate volatile uint8_t *gpio_port1_data; /* set LED */ 61*0Sstevel@tonic-gate volatile uint8_t *gpio_port2_data; /* set DC-DC, 1394, FET */ 62*0Sstevel@tonic-gate }; 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate struct xcppmhndl { 65*0Sstevel@tonic-gate ddi_acc_handle_t bbc_estar_ctrl; 66*0Sstevel@tonic-gate ddi_acc_handle_t rio_mode_auxio; 67*0Sstevel@tonic-gate ddi_acc_handle_t gpio_bank_select; 68*0Sstevel@tonic-gate ddi_acc_handle_t gpio_data_ports; 69*0Sstevel@tonic-gate }; 70*0Sstevel@tonic-gate 71*0Sstevel@tonic-gate /* 72*0Sstevel@tonic-gate * Register offsets 73*0Sstevel@tonic-gate */ 74*0Sstevel@tonic-gate #define BBC_ESTAR_CTRL_OFFSET 0x0 75*0Sstevel@tonic-gate #define BBC_ASSERT_CHANGE_OFFSET 0x2 76*0Sstevel@tonic-gate #define BBC_PLL_SETTLE_OFFSET 0xa 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate #define GPIO_BANK_SEL_INDEX_OFFSET 0x0 79*0Sstevel@tonic-gate #define GPIO_BANK_SEL_DATA_OFFSET 0x1 80*0Sstevel@tonic-gate 81*0Sstevel@tonic-gate #define GPIO_PORT1_DATA_OFFSET 0x0 82*0Sstevel@tonic-gate #define GPIO_PORT2_DATA_OFFSET 0x4 83*0Sstevel@tonic-gate 84*0Sstevel@tonic-gate /* 85*0Sstevel@tonic-gate * Definitions for the RIO Mode Auxio register 86*0Sstevel@tonic-gate */ 87*0Sstevel@tonic-gate #define RIO_BBC_ESTAR_MODE 0x800 88*0Sstevel@tonic-gate 89*0Sstevel@tonic-gate /* 90*0Sstevel@tonic-gate * Index for SuperIO Configuration 2 register 91*0Sstevel@tonic-gate */ 92*0Sstevel@tonic-gate #define SIO_CONFIG2_INDEX 0x22 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* 95*0Sstevel@tonic-gate * GPIO Data Port 1 bit assignments 96*0Sstevel@tonic-gate */ 97*0Sstevel@tonic-gate #define LED 0x02 /* Controls front panel LED */ 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate /* 100*0Sstevel@tonic-gate * GPIO Data Port 2 bit assignments 101*0Sstevel@tonic-gate */ 102*0Sstevel@tonic-gate #define CPEN 0x02 /* Controls 1394 cable power [1 = on] */ 103*0Sstevel@tonic-gate #define HIGHPWR 0x08 /* Enter/Leave low pwr mode [1 = high pwr] */ 104*0Sstevel@tonic-gate #define DRVON 0x10 /* Controls pwr to internal drives [1 = on] */ 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate /* 107*0Sstevel@tonic-gate * BBC timing registers are set according to "bbc_delay" variable 108*0Sstevel@tonic-gate * and adjusted based on current clock speed. 109*0Sstevel@tonic-gate */ 110*0Sstevel@tonic-gate extern int bbc_delay; /* microsec */ 111*0Sstevel@tonic-gate #define BBC_DELAY (bbc_delay * 1000000) /* nanosec */ 112*0Sstevel@tonic-gate #define EXCAL_CLOCK 10 /* 10 nsec or 100 MHz */ 113*0Sstevel@tonic-gate #define BBC_CLOCK (2 * EXCAL_CLOCK) /* BBC clock is half speed */ 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate #define XCPPM_BBC_DELAY(index) \ 116*0Sstevel@tonic-gate (index == 0) ? (BBC_DELAY/(BBC_CLOCK * 32)) : \ 117*0Sstevel@tonic-gate ((index == 1) ? (BBC_DELAY/(BBC_CLOCK * 2)) : \ 118*0Sstevel@tonic-gate BBC_DELAY/BBC_CLOCK) 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate /* 121*0Sstevel@tonic-gate * BBC E* Control Reg bit masks 122*0Sstevel@tonic-gate */ 123*0Sstevel@tonic-gate #define BBC_ESTAR_SLOW 0x20 /* 1/32 speed */ 124*0Sstevel@tonic-gate #define BBC_ESTAR_MEDIUM 0x2 /* 1/2 speed */ 125*0Sstevel@tonic-gate #define BBC_ESTAR_FAST 0x1 /* full speed */ 126*0Sstevel@tonic-gate 127*0Sstevel@tonic-gate /* 128*0Sstevel@tonic-gate * register access IO 129*0Sstevel@tonic-gate */ 130*0Sstevel@tonic-gate #define XCPPM_CLRBIT 0x0 131*0Sstevel@tonic-gate #define XCPPM_SETBIT 0x1 132*0Sstevel@tonic-gate #define XCPPM_GETBIT 0x2 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate #ifdef __cplusplus 135*0Sstevel@tonic-gate } 136*0Sstevel@tonic-gate #endif 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate #endif /* _SYS_XCALPPM_REG_H */ 139