1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate * CDDL HEADER START
3*0Sstevel@tonic-gate *
4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance
7*0Sstevel@tonic-gate * with the License.
8*0Sstevel@tonic-gate *
9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate * and limitations under the License.
13*0Sstevel@tonic-gate *
14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate *
20*0Sstevel@tonic-gate * CDDL HEADER END
21*0Sstevel@tonic-gate */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate * Copyright 2002 Sun Microsystems, Inc. All rights reserved.
24*0Sstevel@tonic-gate * Use is subject to license terms.
25*0Sstevel@tonic-gate */
26*0Sstevel@tonic-gate
27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI"
28*0Sstevel@tonic-gate
29*0Sstevel@tonic-gate #include <sys/param.h>
30*0Sstevel@tonic-gate #include <sys/systm.h>
31*0Sstevel@tonic-gate #include <sys/sunddi.h>
32*0Sstevel@tonic-gate #include <sys/esunddi.h>
33*0Sstevel@tonic-gate #include <sys/ddi.h>
34*0Sstevel@tonic-gate
35*0Sstevel@tonic-gate #include <sys/platform_module.h>
36*0Sstevel@tonic-gate #include <sys/modctl.h>
37*0Sstevel@tonic-gate #include <sys/lom_priv.h>
38*0Sstevel@tonic-gate #include <sys/errno.h>
39*0Sstevel@tonic-gate #include <sys/utsname.h>
40*0Sstevel@tonic-gate
41*0Sstevel@tonic-gate #define TOD_DRIVER_NAME "todblade"
42*0Sstevel@tonic-gate #define BSC_DRV SUNW_KERN_BSCV_MODULENAME
43*0Sstevel@tonic-gate #define BSC_DRV_FUNC SUNW_KERN_BSCV_IDI_FN
44*0Sstevel@tonic-gate
45*0Sstevel@tonic-gate
46*0Sstevel@tonic-gate /* local functions */
47*0Sstevel@tonic-gate static void cpu_sgn_update(ushort_t, uchar_t, uchar_t, int);
48*0Sstevel@tonic-gate
49*0Sstevel@tonic-gate /* Globals */
50*0Sstevel@tonic-gate void (*bsc_drv_func_ptr)(struct bscv_idi_info *) = NULL;
51*0Sstevel@tonic-gate
52*0Sstevel@tonic-gate
53*0Sstevel@tonic-gate void
startup_platform(void)54*0Sstevel@tonic-gate startup_platform(void)
55*0Sstevel@tonic-gate {
56*0Sstevel@tonic-gate extern char *tod_module_name;
57*0Sstevel@tonic-gate extern int watchdog_available;
58*0Sstevel@tonic-gate extern int watchdog_enable;
59*0Sstevel@tonic-gate extern int disable_watchdog_on_exit;
60*0Sstevel@tonic-gate
61*0Sstevel@tonic-gate /* Set appropriate tod module for blade */
62*0Sstevel@tonic-gate tod_module_name = TOD_DRIVER_NAME;
63*0Sstevel@tonic-gate
64*0Sstevel@tonic-gate /* Set watchdog default configuration */
65*0Sstevel@tonic-gate watchdog_available = 1;
66*0Sstevel@tonic-gate watchdog_enable = 1;
67*0Sstevel@tonic-gate disable_watchdog_on_exit = 1;
68*0Sstevel@tonic-gate }
69*0Sstevel@tonic-gate
70*0Sstevel@tonic-gate int
set_platform_tsb_spares()71*0Sstevel@tonic-gate set_platform_tsb_spares()
72*0Sstevel@tonic-gate {
73*0Sstevel@tonic-gate return (0);
74*0Sstevel@tonic-gate }
75*0Sstevel@tonic-gate
76*0Sstevel@tonic-gate void
set_platform_defaults(void)77*0Sstevel@tonic-gate set_platform_defaults(void)
78*0Sstevel@tonic-gate {
79*0Sstevel@tonic-gate /* Set the CPU signature function pointer */
80*0Sstevel@tonic-gate cpu_sgn_func = cpu_sgn_update;
81*0Sstevel@tonic-gate }
82*0Sstevel@tonic-gate
83*0Sstevel@tonic-gate /*
84*0Sstevel@tonic-gate * Definitions for accessing the pci config space of the isa node
85*0Sstevel@tonic-gate * of Southbridge.
86*0Sstevel@tonic-gate */
87*0Sstevel@tonic-gate #define PLATFORM_ISA_PATHNAME "/pci@1f,0/isa@7"
88*0Sstevel@tonic-gate #define PLATFORM_ISA_PATHNAME_WITH_SIMBA "/pci@1f,0/pci@1,1/isa@7"
89*0Sstevel@tonic-gate static ddi_acc_handle_t platform_isa_handle; /* handle for isa pci space */
90*0Sstevel@tonic-gate
91*0Sstevel@tonic-gate void
load_platform_drivers(void)92*0Sstevel@tonic-gate load_platform_drivers(void)
93*0Sstevel@tonic-gate {
94*0Sstevel@tonic-gate extern int watchdog_available;
95*0Sstevel@tonic-gate extern int watchdog_enable;
96*0Sstevel@tonic-gate dev_info_t *dip; /* dip of the isa driver */
97*0Sstevel@tonic-gate int simba_present = 0;
98*0Sstevel@tonic-gate dev_info_t *root_child_node;
99*0Sstevel@tonic-gate major_t major;
100*0Sstevel@tonic-gate
101*0Sstevel@tonic-gate if (ddi_install_driver("power") != DDI_SUCCESS)
102*0Sstevel@tonic-gate cmn_err(CE_WARN, "Failed to install \"power\" driver.");
103*0Sstevel@tonic-gate
104*0Sstevel@tonic-gate /*
105*0Sstevel@tonic-gate * Install Isa driver. This is required for the southbridge IDE
106*0Sstevel@tonic-gate * workaround - to reset the IDE channel during IDE bus reset.
107*0Sstevel@tonic-gate * Panic the system in case ISA driver could not be loaded or
108*0Sstevel@tonic-gate * any problem in accessing its pci config space. Since the register
109*0Sstevel@tonic-gate * to reset the channel for IDE is in ISA config space!.
110*0Sstevel@tonic-gate */
111*0Sstevel@tonic-gate root_child_node = ddi_get_child(ddi_root_node());
112*0Sstevel@tonic-gate
113*0Sstevel@tonic-gate while (root_child_node != NULL) {
114*0Sstevel@tonic-gate if (strcmp(ddi_node_name(root_child_node), "pci") == 0) {
115*0Sstevel@tonic-gate root_child_node = ddi_get_child(root_child_node);
116*0Sstevel@tonic-gate if (strcmp(ddi_node_name(root_child_node), "pci") == 0)
117*0Sstevel@tonic-gate simba_present = 1;
118*0Sstevel@tonic-gate break;
119*0Sstevel@tonic-gate }
120*0Sstevel@tonic-gate root_child_node = ddi_get_next_sibling(root_child_node);
121*0Sstevel@tonic-gate }
122*0Sstevel@tonic-gate
123*0Sstevel@tonic-gate if (simba_present)
124*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME_WITH_SIMBA,
125*0Sstevel@tonic-gate 0);
126*0Sstevel@tonic-gate else
127*0Sstevel@tonic-gate dip = e_ddi_hold_devi_by_path(PLATFORM_ISA_PATHNAME, 0);
128*0Sstevel@tonic-gate
129*0Sstevel@tonic-gate if (dip == NULL) {
130*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not install the isa driver\n");
131*0Sstevel@tonic-gate return;
132*0Sstevel@tonic-gate }
133*0Sstevel@tonic-gate
134*0Sstevel@tonic-gate if (pci_config_setup(dip, &platform_isa_handle) != DDI_SUCCESS) {
135*0Sstevel@tonic-gate cmn_err(CE_PANIC, "Could not get the config space of isa\n");
136*0Sstevel@tonic-gate return;
137*0Sstevel@tonic-gate }
138*0Sstevel@tonic-gate
139*0Sstevel@tonic-gate /*
140*0Sstevel@tonic-gate * Load the blade support chip driver.
141*0Sstevel@tonic-gate *
142*0Sstevel@tonic-gate */
143*0Sstevel@tonic-gate
144*0Sstevel@tonic-gate if (((major = ddi_name_to_major(BSC_DRV)) == -1) ||
145*0Sstevel@tonic-gate (ddi_hold_installed_driver(major) == NULL)) {
146*0Sstevel@tonic-gate cmn_err(CE_WARN, "%s: failed to load", BSC_DRV);
147*0Sstevel@tonic-gate } else {
148*0Sstevel@tonic-gate
149*0Sstevel@tonic-gate bsc_drv_func_ptr = (void (*)(struct bscv_idi_info *))
150*0Sstevel@tonic-gate modgetsymvalue(BSC_DRV_FUNC, 0);
151*0Sstevel@tonic-gate
152*0Sstevel@tonic-gate if (bsc_drv_func_ptr == NULL) {
153*0Sstevel@tonic-gate cmn_err(CE_WARN, "load_platform_defaults: %s()"
154*0Sstevel@tonic-gate " not found; signatures will not be updated\n",
155*0Sstevel@tonic-gate BSC_DRV_FUNC);
156*0Sstevel@tonic-gate watchdog_available = 0;
157*0Sstevel@tonic-gate if (watchdog_enable) {
158*0Sstevel@tonic-gate cmn_err(CE_WARN, "load_platform_defaults: %s()"
159*0Sstevel@tonic-gate " not found; BSC OS watchdog service not available\n",
160*0Sstevel@tonic-gate BSC_DRV_FUNC);
161*0Sstevel@tonic-gate }
162*0Sstevel@tonic-gate }
163*0Sstevel@tonic-gate }
164*0Sstevel@tonic-gate }
165*0Sstevel@tonic-gate
166*0Sstevel@tonic-gate /*
167*0Sstevel@tonic-gate * This routine provides a workaround for a bug in the SB chip which
168*0Sstevel@tonic-gate * can cause data corruption. Will be invoked from the IDE HBA driver for
169*0Sstevel@tonic-gate * Acer SouthBridge at the time of IDE bus reset.
170*0Sstevel@tonic-gate */
171*0Sstevel@tonic-gate /*ARGSUSED*/
172*0Sstevel@tonic-gate int
plat_ide_chipreset(dev_info_t * dip,int chno)173*0Sstevel@tonic-gate plat_ide_chipreset(dev_info_t *dip, int chno)
174*0Sstevel@tonic-gate {
175*0Sstevel@tonic-gate uint8_t val;
176*0Sstevel@tonic-gate int ret = DDI_SUCCESS;
177*0Sstevel@tonic-gate
178*0Sstevel@tonic-gate if (platform_isa_handle == NULL)
179*0Sstevel@tonic-gate return (DDI_FAILURE);
180*0Sstevel@tonic-gate
181*0Sstevel@tonic-gate val = pci_config_get8(platform_isa_handle, 0x58);
182*0Sstevel@tonic-gate /*
183*0Sstevel@tonic-gate * The dip passed as the argument is not used for platform.
184*0Sstevel@tonic-gate * This will be needed for platforms which have multiple on-board SB,
185*0Sstevel@tonic-gate * The dip passed will be used to match the corresponding ISA node.
186*0Sstevel@tonic-gate */
187*0Sstevel@tonic-gate switch (chno) {
188*0Sstevel@tonic-gate case 0:
189*0Sstevel@tonic-gate /*
190*0Sstevel@tonic-gate * First disable the primary channel then re-enable it.
191*0Sstevel@tonic-gate * As per ALI no wait should be required in between have
192*0Sstevel@tonic-gate * given 1ms delay in between to be on safer side.
193*0Sstevel@tonic-gate * bit 2 of register 0x58 when 0 disable the channel 0.
194*0Sstevel@tonic-gate * bit 2 of register 0x58 when 1 enables the channel 0.
195*0Sstevel@tonic-gate */
196*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val & 0xFB);
197*0Sstevel@tonic-gate drv_usecwait(1000);
198*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val);
199*0Sstevel@tonic-gate break;
200*0Sstevel@tonic-gate case 1:
201*0Sstevel@tonic-gate /*
202*0Sstevel@tonic-gate * bit 3 of register 0x58 when 0 disable the channel 1.
203*0Sstevel@tonic-gate * bit 3 of register 0x58 when 1 enables the channel 1.
204*0Sstevel@tonic-gate */
205*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val & 0xF7);
206*0Sstevel@tonic-gate drv_usecwait(1000);
207*0Sstevel@tonic-gate pci_config_put8(platform_isa_handle, 0x58, val);
208*0Sstevel@tonic-gate break;
209*0Sstevel@tonic-gate default:
210*0Sstevel@tonic-gate /*
211*0Sstevel@tonic-gate * Unknown channel number passed. Return failure.
212*0Sstevel@tonic-gate */
213*0Sstevel@tonic-gate ret = DDI_FAILURE;
214*0Sstevel@tonic-gate }
215*0Sstevel@tonic-gate
216*0Sstevel@tonic-gate return (ret);
217*0Sstevel@tonic-gate }
218*0Sstevel@tonic-gate
219*0Sstevel@tonic-gate
220*0Sstevel@tonic-gate
221*0Sstevel@tonic-gate /*ARGSUSED*/
222*0Sstevel@tonic-gate int
plat_cpu_poweron(struct cpu * cp)223*0Sstevel@tonic-gate plat_cpu_poweron(struct cpu *cp)
224*0Sstevel@tonic-gate {
225*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
226*0Sstevel@tonic-gate }
227*0Sstevel@tonic-gate
228*0Sstevel@tonic-gate /*ARGSUSED*/
229*0Sstevel@tonic-gate int
plat_cpu_poweroff(struct cpu * cp)230*0Sstevel@tonic-gate plat_cpu_poweroff(struct cpu *cp)
231*0Sstevel@tonic-gate {
232*0Sstevel@tonic-gate return (ENOTSUP); /* not supported on this platform */
233*0Sstevel@tonic-gate }
234*0Sstevel@tonic-gate
235*0Sstevel@tonic-gate /*ARGSUSED*/
236*0Sstevel@tonic-gate void
plat_freelist_process(int mnode)237*0Sstevel@tonic-gate plat_freelist_process(int mnode)
238*0Sstevel@tonic-gate {
239*0Sstevel@tonic-gate }
240*0Sstevel@tonic-gate
241*0Sstevel@tonic-gate char *platform_module_list[] = {
242*0Sstevel@tonic-gate (char *)0
243*0Sstevel@tonic-gate };
244*0Sstevel@tonic-gate
245*0Sstevel@tonic-gate /*ARGSUSED*/
246*0Sstevel@tonic-gate void
plat_tod_fault(enum tod_fault_type tod_bad)247*0Sstevel@tonic-gate plat_tod_fault(enum tod_fault_type tod_bad)
248*0Sstevel@tonic-gate {
249*0Sstevel@tonic-gate }
250*0Sstevel@tonic-gate
251*0Sstevel@tonic-gate /*
252*0Sstevel@tonic-gate * Our nodename has been set, pass it along to the BSC.
253*0Sstevel@tonic-gate */
254*0Sstevel@tonic-gate void
plat_nodename_set(void)255*0Sstevel@tonic-gate plat_nodename_set(void)
256*0Sstevel@tonic-gate {
257*0Sstevel@tonic-gate struct bscv_idi_info bscv_info;
258*0Sstevel@tonic-gate
259*0Sstevel@tonic-gate bscv_info.type = BSCV_IDI_NODENAME;
260*0Sstevel@tonic-gate bscv_info.data = utsname.nodename;
261*0Sstevel@tonic-gate bscv_info.size = strlen(utsname.nodename);
262*0Sstevel@tonic-gate
263*0Sstevel@tonic-gate if (bsc_drv_func_ptr != NULL)
264*0Sstevel@tonic-gate (bsc_drv_func_ptr)(&bscv_info);
265*0Sstevel@tonic-gate }
266*0Sstevel@tonic-gate
267*0Sstevel@tonic-gate /*
268*0Sstevel@tonic-gate * Send an updated CPU signature to the BSC.
269*0Sstevel@tonic-gate */
270*0Sstevel@tonic-gate
271*0Sstevel@tonic-gate static void
cpu_sgn_update(ushort_t sig,uchar_t state,uchar_t sub_state,int cpuid)272*0Sstevel@tonic-gate cpu_sgn_update(ushort_t sig, uchar_t state, uchar_t sub_state, int cpuid)
273*0Sstevel@tonic-gate {
274*0Sstevel@tonic-gate struct bscv_idi_info bscv_info;
275*0Sstevel@tonic-gate bscv_sig_t sc;
276*0Sstevel@tonic-gate
277*0Sstevel@tonic-gate sc.sig_info.signature = CPU_SIG_BLD(sig, state, sub_state);
278*0Sstevel@tonic-gate sc.cpu = cpuid;
279*0Sstevel@tonic-gate
280*0Sstevel@tonic-gate bscv_info.type = BSCV_IDI_SIG;
281*0Sstevel@tonic-gate bscv_info.data = ≻
282*0Sstevel@tonic-gate bscv_info.size = sizeof (sc);
283*0Sstevel@tonic-gate
284*0Sstevel@tonic-gate
285*0Sstevel@tonic-gate if (bsc_drv_func_ptr != NULL)
286*0Sstevel@tonic-gate (*bsc_drv_func_ptr)(&bscv_info);
287*0Sstevel@tonic-gate }
288