10Sstevel@tonic-gate /* 20Sstevel@tonic-gate * CDDL HEADER START 30Sstevel@tonic-gate * 40Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*1455Sandrei * Common Development and Distribution License (the "License"). 6*1455Sandrei * You may not use this file except in compliance with the License. 70Sstevel@tonic-gate * 80Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 100Sstevel@tonic-gate * See the License for the specific language governing permissions 110Sstevel@tonic-gate * and limitations under the License. 120Sstevel@tonic-gate * 130Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 140Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 160Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 170Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 180Sstevel@tonic-gate * 190Sstevel@tonic-gate * CDDL HEADER END 200Sstevel@tonic-gate */ 210Sstevel@tonic-gate /* 22*1455Sandrei * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 230Sstevel@tonic-gate * Use is subject to license terms. 240Sstevel@tonic-gate */ 250Sstevel@tonic-gate 260Sstevel@tonic-gate #ifndef _SYS_INTR_H 270Sstevel@tonic-gate #define _SYS_INTR_H 280Sstevel@tonic-gate 290Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 300Sstevel@tonic-gate 310Sstevel@tonic-gate #ifdef __cplusplus 320Sstevel@tonic-gate extern "C" { 330Sstevel@tonic-gate #endif 340Sstevel@tonic-gate 350Sstevel@tonic-gate /* 360Sstevel@tonic-gate * Each cpu allocates an interrupt request pool with the size of 370Sstevel@tonic-gate * INTR_PENDING_MAX entries. 380Sstevel@tonic-gate * XXX this number needs to be tuned 390Sstevel@tonic-gate */ 400Sstevel@tonic-gate #define INTR_PENDING_MAX 64 410Sstevel@tonic-gate #define INTR_POOL_SIZE (sizeof (struct intr_req) * INTR_PENDING_MAX) 420Sstevel@tonic-gate 430Sstevel@tonic-gate /* 440Sstevel@tonic-gate * Each cpu allocates two arrays, intr_head[] and intr_tail[], with the size of 450Sstevel@tonic-gate * PIL_LEVELS each. 460Sstevel@tonic-gate * 470Sstevel@tonic-gate * The entry 0 of the arrays are the head and the tail of the interrupt 480Sstevel@tonic-gate * request free list. 490Sstevel@tonic-gate * 500Sstevel@tonic-gate * The entries 1-15 of the arrays are the head and the tail of interrupt 510Sstevel@tonic-gate * level 1-15 request queues. 520Sstevel@tonic-gate */ 530Sstevel@tonic-gate #define PIL_LEVELS 16 /* 0 : for the interrupt request free list */ 540Sstevel@tonic-gate /* 1-15 : for the pil level 1-15 */ 550Sstevel@tonic-gate 560Sstevel@tonic-gate #define PIL_1 1 570Sstevel@tonic-gate #define PIL_2 2 580Sstevel@tonic-gate #define PIL_3 3 590Sstevel@tonic-gate #define PIL_4 4 600Sstevel@tonic-gate #define PIL_5 5 610Sstevel@tonic-gate #define PIL_6 6 620Sstevel@tonic-gate #define PIL_7 7 630Sstevel@tonic-gate #define PIL_8 8 640Sstevel@tonic-gate #define PIL_9 9 650Sstevel@tonic-gate #define PIL_10 10 660Sstevel@tonic-gate #define PIL_11 11 670Sstevel@tonic-gate #define PIL_12 12 680Sstevel@tonic-gate #define PIL_13 13 690Sstevel@tonic-gate #define PIL_14 14 700Sstevel@tonic-gate #define PIL_15 15 710Sstevel@tonic-gate 720Sstevel@tonic-gate #ifndef _ASM 730Sstevel@tonic-gate extern uint_t poke_cpu_inum; 740Sstevel@tonic-gate extern size_t intr_add_max; 750Sstevel@tonic-gate extern uint_t intr_add_div; 760Sstevel@tonic-gate extern size_t intr_add_pools; 770Sstevel@tonic-gate extern struct intr_req *intr_add_head; 780Sstevel@tonic-gate extern struct intr_req *intr_add_tail; 790Sstevel@tonic-gate extern void intr_init(struct cpu *); 800Sstevel@tonic-gate extern void init_intr_pool(struct cpu *); 810Sstevel@tonic-gate extern void cleanup_intr_pool(struct cpu *); 820Sstevel@tonic-gate 830Sstevel@tonic-gate /* 840Sstevel@tonic-gate * interrupt request entry 850Sstevel@tonic-gate * 860Sstevel@tonic-gate * - each cpu has an interrupt request free list formed thru 870Sstevel@tonic-gate * init_intr_pool(); intr_head[0] and intr_tail[0] are the head 880Sstevel@tonic-gate * and tail of the free list 890Sstevel@tonic-gate * 900Sstevel@tonic-gate * - always get a free intr_req from the intr_head[0] and 910Sstevel@tonic-gate * return a served intr_req to intr_tail[0] 920Sstevel@tonic-gate * 930Sstevel@tonic-gate * - when vec_interrupt() is called, an interrupt request queue is built 940Sstevel@tonic-gate * according to the pil level, intr_head[pil] points to the first 950Sstevel@tonic-gate * interrupt request entry and intr_tail[pil] points to the last one 960Sstevel@tonic-gate * 970Sstevel@tonic-gate */ 980Sstevel@tonic-gate struct intr_req { 990Sstevel@tonic-gate uint_t intr_number; 1000Sstevel@tonic-gate struct intr_req *intr_next; 1010Sstevel@tonic-gate }; 1020Sstevel@tonic-gate 1030Sstevel@tonic-gate #endif /* !_ASM */ 1040Sstevel@tonic-gate 1050Sstevel@tonic-gate #ifdef __cplusplus 1060Sstevel@tonic-gate } 1070Sstevel@tonic-gate #endif 1080Sstevel@tonic-gate 1090Sstevel@tonic-gate #endif /* _SYS_INTR_H */ 110