xref: /onnv-gate/usr/src/uts/sun4/sys/intr.h (revision 0)
1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate  * CDDL HEADER START
3*0Sstevel@tonic-gate  *
4*0Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*0Sstevel@tonic-gate  * with the License.
8*0Sstevel@tonic-gate  *
9*0Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate  * and limitations under the License.
13*0Sstevel@tonic-gate  *
14*0Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate  *
20*0Sstevel@tonic-gate  * CDDL HEADER END
21*0Sstevel@tonic-gate  */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate  * Copyright 1994, 1997-2002 Sun Microsystems, Inc.  All rights reserved.
24*0Sstevel@tonic-gate  * Use is subject to license terms.
25*0Sstevel@tonic-gate  */
26*0Sstevel@tonic-gate 
27*0Sstevel@tonic-gate #ifndef	_SYS_INTR_H
28*0Sstevel@tonic-gate #define	_SYS_INTR_H
29*0Sstevel@tonic-gate 
30*0Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*0Sstevel@tonic-gate 
32*0Sstevel@tonic-gate #ifdef	__cplusplus
33*0Sstevel@tonic-gate extern "C" {
34*0Sstevel@tonic-gate #endif
35*0Sstevel@tonic-gate 
36*0Sstevel@tonic-gate /*
37*0Sstevel@tonic-gate  * Each cpu allocates an interrupt request pool with the size of
38*0Sstevel@tonic-gate  * INTR_PENDING_MAX entries.
39*0Sstevel@tonic-gate  * XXX this number needs to be tuned
40*0Sstevel@tonic-gate  */
41*0Sstevel@tonic-gate #define	INTR_PENDING_MAX	64
42*0Sstevel@tonic-gate #define	INTR_POOL_SIZE		(sizeof (struct intr_req) * INTR_PENDING_MAX)
43*0Sstevel@tonic-gate 
44*0Sstevel@tonic-gate /*
45*0Sstevel@tonic-gate  * Allocate threads and stacks for interrupt handling.
46*0Sstevel@tonic-gate  */
47*0Sstevel@tonic-gate #define	NINTR_THREADS	(LOCK_LEVEL)	/* number of interrupt threads */
48*0Sstevel@tonic-gate 
49*0Sstevel@tonic-gate /*
50*0Sstevel@tonic-gate  * Each cpu allocates two arrays, intr_head[] and intr_tail[], with the size of
51*0Sstevel@tonic-gate  * PIL_LEVELS each.
52*0Sstevel@tonic-gate  *
53*0Sstevel@tonic-gate  * The entry 0 of the arrays are the head and the tail of the interrupt
54*0Sstevel@tonic-gate  * request free list.
55*0Sstevel@tonic-gate  *
56*0Sstevel@tonic-gate  * The entries 1-15 of the arrays are the head and the tail of interrupt
57*0Sstevel@tonic-gate  * level 1-15 request queues.
58*0Sstevel@tonic-gate  */
59*0Sstevel@tonic-gate #define	PIL_LEVELS	16	/* 0    : for the interrupt request free list */
60*0Sstevel@tonic-gate 				/* 1-15 : for the pil level 1-15 */
61*0Sstevel@tonic-gate 
62*0Sstevel@tonic-gate #define	PIL_1	1
63*0Sstevel@tonic-gate #define	PIL_2	2
64*0Sstevel@tonic-gate #define	PIL_3	3
65*0Sstevel@tonic-gate #define	PIL_4	4
66*0Sstevel@tonic-gate #define	PIL_5	5
67*0Sstevel@tonic-gate #define	PIL_6	6
68*0Sstevel@tonic-gate #define	PIL_7	7
69*0Sstevel@tonic-gate #define	PIL_8	8
70*0Sstevel@tonic-gate #define	PIL_9	9
71*0Sstevel@tonic-gate #define	PIL_10	10
72*0Sstevel@tonic-gate #define	PIL_11	11
73*0Sstevel@tonic-gate #define	PIL_12	12
74*0Sstevel@tonic-gate #define	PIL_13	13
75*0Sstevel@tonic-gate #define	PIL_14	14
76*0Sstevel@tonic-gate #define	PIL_15	15
77*0Sstevel@tonic-gate 
78*0Sstevel@tonic-gate #ifndef _ASM
79*0Sstevel@tonic-gate extern uint_t poke_cpu_inum;
80*0Sstevel@tonic-gate extern size_t intr_add_max;
81*0Sstevel@tonic-gate extern uint_t intr_add_div;
82*0Sstevel@tonic-gate extern size_t intr_add_pools;
83*0Sstevel@tonic-gate extern struct intr_req *intr_add_head;
84*0Sstevel@tonic-gate extern struct intr_req *intr_add_tail;
85*0Sstevel@tonic-gate extern void intr_init(struct cpu *);
86*0Sstevel@tonic-gate extern void init_intr_pool(struct cpu *);
87*0Sstevel@tonic-gate extern void cleanup_intr_pool(struct cpu *);
88*0Sstevel@tonic-gate 
89*0Sstevel@tonic-gate /*
90*0Sstevel@tonic-gate  * interrupt request entry
91*0Sstevel@tonic-gate  *
92*0Sstevel@tonic-gate  *    - each cpu has an interrupt request free list formed thru
93*0Sstevel@tonic-gate  *      init_intr_pool(); intr_head[0] and intr_tail[0] are the head
94*0Sstevel@tonic-gate  *      and tail of the free list
95*0Sstevel@tonic-gate  *
96*0Sstevel@tonic-gate  *    - always get a free intr_req from the intr_head[0] and
97*0Sstevel@tonic-gate  *      return a served intr_req to intr_tail[0]
98*0Sstevel@tonic-gate  *
99*0Sstevel@tonic-gate  *    - when vec_interrupt() is called, an interrupt request queue is built
100*0Sstevel@tonic-gate  *      according to the pil level, intr_head[pil] points to the first
101*0Sstevel@tonic-gate  *      interrupt request entry and intr_tail[pil] points to the last one
102*0Sstevel@tonic-gate  *
103*0Sstevel@tonic-gate  */
104*0Sstevel@tonic-gate struct intr_req {
105*0Sstevel@tonic-gate 	uint_t 		intr_number;
106*0Sstevel@tonic-gate 	struct intr_req *intr_next;
107*0Sstevel@tonic-gate };
108*0Sstevel@tonic-gate 
109*0Sstevel@tonic-gate #endif	/* !_ASM */
110*0Sstevel@tonic-gate 
111*0Sstevel@tonic-gate #ifdef	__cplusplus
112*0Sstevel@tonic-gate }
113*0Sstevel@tonic-gate #endif
114*0Sstevel@tonic-gate 
115*0Sstevel@tonic-gate #endif	/* _SYS_INTR_H */
116