1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_EBUS_H 28*0Sstevel@tonic-gate #define _SYS_EBUS_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * driver state type: 38*0Sstevel@tonic-gate */ 39*0Sstevel@tonic-gate typedef enum { NEW = 0, ATTACHED, RESUMED, DETACHED, 40*0Sstevel@tonic-gate SUSPENDED, PM_SUSPENDED } driver_state_t; 41*0Sstevel@tonic-gate 42*0Sstevel@tonic-gate /* 43*0Sstevel@tonic-gate * The i86pc specific code fragments are to support the debug of "honeynut" 44*0Sstevel@tonic-gate * and "multigrain" prototypes on i86pc platform. Most of the fragments 45*0Sstevel@tonic-gate * deal with differences in the interrupt dispatching between the prototypes 46*0Sstevel@tonic-gate * and the cheerio ebus. On the prototype boards, all interrupt lines are 47*0Sstevel@tonic-gate * tied together. For this case, the nexus driver uses a common interrupt 48*0Sstevel@tonic-gate * handler to poll all of its children. 49*0Sstevel@tonic-gate */ 50*0Sstevel@tonic-gate #if defined(i86pc) 51*0Sstevel@tonic-gate #define MAX_EBUS_DEVS 6 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate /* 54*0Sstevel@tonic-gate * ebus device interrupt info; 55*0Sstevel@tonic-gate */ 56*0Sstevel@tonic-gate typedef struct { 57*0Sstevel@tonic-gate char *name; 58*0Sstevel@tonic-gate uint_t inuse; 59*0Sstevel@tonic-gate uint_t (*handler)(); 60*0Sstevel@tonic-gate caddr_t arg; 61*0Sstevel@tonic-gate } ebus_intr_slot_t; 62*0Sstevel@tonic-gate #endif 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate struct ebus_intr_map { 65*0Sstevel@tonic-gate uint32_t ebus_phys_hi; 66*0Sstevel@tonic-gate uint32_t ebus_phys_low; 67*0Sstevel@tonic-gate uint32_t ebus_intr; 68*0Sstevel@tonic-gate uint32_t intr_ctlr_nodeid; 69*0Sstevel@tonic-gate uint32_t ino; 70*0Sstevel@tonic-gate }; 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate struct ebus_intr_map_mask { 73*0Sstevel@tonic-gate uint32_t ebus_phys_hi; 74*0Sstevel@tonic-gate uint32_t ebus_phys_low; 75*0Sstevel@tonic-gate uint32_t ebus_intr; 76*0Sstevel@tonic-gate }; 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate /* 79*0Sstevel@tonic-gate * driver soft state structure: 80*0Sstevel@tonic-gate */ 81*0Sstevel@tonic-gate typedef struct { 82*0Sstevel@tonic-gate dev_info_t *dip; 83*0Sstevel@tonic-gate driver_state_t state; 84*0Sstevel@tonic-gate pci_regspec_t *reg; 85*0Sstevel@tonic-gate int nreg; 86*0Sstevel@tonic-gate 87*0Sstevel@tonic-gate union { 88*0Sstevel@tonic-gate struct ebus_pci_rangespec *rangep; 89*0Sstevel@tonic-gate struct febus_rangespec *ferangep; 90*0Sstevel@tonic-gate } rangespec; 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate int range_cnt; 93*0Sstevel@tonic-gate kmutex_t ebus_mutex; 94*0Sstevel@tonic-gate uint_t ebus_soft_state; 95*0Sstevel@tonic-gate #define EBUS_SOFT_STATE_CLOSED 0x00 96*0Sstevel@tonic-gate #define EBUS_SOFT_STATE_OPEN 0x01 97*0Sstevel@tonic-gate #define EBUS_SOFT_STATE_OPEN_EXCL 0x02 98*0Sstevel@tonic-gate 99*0Sstevel@tonic-gate #if defined(i86pc) 100*0Sstevel@tonic-gate ddi_iblock_cookie_t iblock; 101*0Sstevel@tonic-gate ddi_idevice_cookie_t idevice; 102*0Sstevel@tonic-gate ebus_intr_slot_t intr_slot[MAX_EBUS_DEVS]; 103*0Sstevel@tonic-gate #endif 104*0Sstevel@tonic-gate #if defined(__sparc) 105*0Sstevel@tonic-gate /* Interrupt support */ 106*0Sstevel@tonic-gate int intr_map_size; 107*0Sstevel@tonic-gate struct ebus_intr_map *intr_map; 108*0Sstevel@tonic-gate struct ebus_intr_map_mask *intr_map_mask; 109*0Sstevel@tonic-gate #endif 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate uint_t type; 112*0Sstevel@tonic-gate #define EBUS_TYPE 0x00 113*0Sstevel@tonic-gate #define FEBUS_TYPE 0x01 114*0Sstevel@tonic-gate } ebus_devstate_t; 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate /* 117*0Sstevel@tonic-gate * definition of ebus reg spec entry: 118*0Sstevel@tonic-gate */ 119*0Sstevel@tonic-gate typedef struct { 120*0Sstevel@tonic-gate uint32_t addr_hi; 121*0Sstevel@tonic-gate uint32_t addr_low; 122*0Sstevel@tonic-gate uint32_t size; 123*0Sstevel@tonic-gate } ebus_regspec_t; 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate /* EBUS range entry */ 126*0Sstevel@tonic-gate struct ebus_pci_rangespec { 127*0Sstevel@tonic-gate uint32_t ebus_phys_hi; /* Child hi range address */ 128*0Sstevel@tonic-gate uint32_t ebus_phys_low; /* Child low range address */ 129*0Sstevel@tonic-gate uint32_t pci_phys_hi; /* Parent hi rng addr */ 130*0Sstevel@tonic-gate uint32_t pci_phys_mid; /* Parent mid rng addr */ 131*0Sstevel@tonic-gate uint32_t pci_phys_low; /* Parent low rng addr */ 132*0Sstevel@tonic-gate uint32_t rng_size; /* Range size */ 133*0Sstevel@tonic-gate }; 134*0Sstevel@tonic-gate 135*0Sstevel@tonic-gate /* FEBUS range entry */ 136*0Sstevel@tonic-gate struct febus_rangespec { 137*0Sstevel@tonic-gate uint32_t febus_phys_hi; /* Child hi range address */ 138*0Sstevel@tonic-gate uint32_t febus_phys_low; /* Child low range address */ 139*0Sstevel@tonic-gate uint32_t parent_phys_hi; /* Parent hi rng addr */ 140*0Sstevel@tonic-gate uint32_t parent_phys_low; /* Parent low rng addr */ 141*0Sstevel@tonic-gate uint32_t rng_size; /* Range size */ 142*0Sstevel@tonic-gate }; 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate /* 145*0Sstevel@tonic-gate * use macros for soft state and driver properties: 146*0Sstevel@tonic-gate */ 147*0Sstevel@tonic-gate #define get_ebus_soft_state(i) \ 148*0Sstevel@tonic-gate ((ebus_devstate_t *)ddi_get_soft_state(per_ebus_state, (i))) 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate #define alloc_ebus_soft_state(i) \ 151*0Sstevel@tonic-gate ddi_soft_state_zalloc(per_ebus_state, (i)) 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate #define free_ebus_soft_state(i) \ 154*0Sstevel@tonic-gate ddi_soft_state_free(per_ebus_state, (i)) 155*0Sstevel@tonic-gate 156*0Sstevel@tonic-gate 157*0Sstevel@tonic-gate #define getprop(dip, name, addr, intp) \ 158*0Sstevel@tonic-gate ddi_getlongprop(DDI_DEV_T_NONE, (dip), DDI_PROP_DONTPASS, \ 159*0Sstevel@tonic-gate (name), (caddr_t)(addr), (intp)) 160*0Sstevel@tonic-gate 161*0Sstevel@tonic-gate #define IS_RIO(dip) \ 162*0Sstevel@tonic-gate ((ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \ 163*0Sstevel@tonic-gate "device-id", -1) == 0x1100) && \ 164*0Sstevel@tonic-gate (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \ 165*0Sstevel@tonic-gate "vendor-id", -1) == 0x108e)) 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate #define EBUS_4MHZ 4000 168*0Sstevel@tonic-gate 169*0Sstevel@tonic-gate /* 170*0Sstevel@tonic-gate * register offsets and lengths: 171*0Sstevel@tonic-gate */ 172*0Sstevel@tonic-gate #define TCR_OFFSET 0x710000 173*0Sstevel@tonic-gate #define TCR_LENGTH 12 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate /* 176*0Sstevel@tonic-gate * timing control register settings: 177*0Sstevel@tonic-gate */ 178*0Sstevel@tonic-gate #define TCR1 0x08101008 179*0Sstevel@tonic-gate #define TCR2 0x08100020 180*0Sstevel@tonic-gate #define TCR3 0x00000020 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate #if defined(DEBUG) 183*0Sstevel@tonic-gate #define D_IDENTIFY 0x00000001 184*0Sstevel@tonic-gate #define D_ATTACH 0x00000002 185*0Sstevel@tonic-gate #define D_DETACH 0x00000004 186*0Sstevel@tonic-gate #define D_MAP 0x00000008 187*0Sstevel@tonic-gate #define D_CTLOPS 0x00000010 188*0Sstevel@tonic-gate #define D_INTR 0x00000100 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate #define DBG(flag, psp, fmt) \ 191*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, 0, 0, 0, 0, 0); 192*0Sstevel@tonic-gate #define DBG1(flag, psp, fmt, a1) \ 193*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0); 194*0Sstevel@tonic-gate #define DBG2(flag, psp, fmt, a1, a2) \ 195*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0); 196*0Sstevel@tonic-gate #define DBG3(flag, psp, fmt, a1, a2, a3) \ 197*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 198*0Sstevel@tonic-gate (uintptr_t)(a3), 0, 0); 199*0Sstevel@tonic-gate #define DBG4(flag, psp, fmt, a1, a2, a3, a4) \ 200*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 201*0Sstevel@tonic-gate (uintptr_t)(a3), \ 202*0Sstevel@tonic-gate (uintptr_t)(a4), 0); 203*0Sstevel@tonic-gate #define DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) \ 204*0Sstevel@tonic-gate ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 205*0Sstevel@tonic-gate (uintptr_t)(a3), \ 206*0Sstevel@tonic-gate (uintptr_t)(a4), (uintptr_t)(a5)); 207*0Sstevel@tonic-gate static void 208*0Sstevel@tonic-gate ebus_debug(uint_t, ebus_devstate_t *, char *, uintptr_t, uintptr_t, uintptr_t, 209*0Sstevel@tonic-gate uintptr_t, uintptr_t); 210*0Sstevel@tonic-gate #else 211*0Sstevel@tonic-gate #define DBG(flag, psp, fmt) 212*0Sstevel@tonic-gate #define DBG1(flag, psp, fmt, a1) 213*0Sstevel@tonic-gate #define DBG2(flag, psp, fmt, a1, a2) 214*0Sstevel@tonic-gate #define DBG3(flag, psp, fmt, a1, a2, a3) 215*0Sstevel@tonic-gate #define DBG4(flag, psp, fmt, a1, a2, a3, a4) 216*0Sstevel@tonic-gate #define DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) 217*0Sstevel@tonic-gate #endif 218*0Sstevel@tonic-gate 219*0Sstevel@tonic-gate #ifdef __cplusplus 220*0Sstevel@tonic-gate } 221*0Sstevel@tonic-gate #endif 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate #endif /* _SYS_EBUS_H */ 224