xref: /onnv-gate/usr/src/uts/sun4/sys/ebus.h (revision 558:242c3cde6d15)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
50Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
60Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
70Sstevel@tonic-gate  * with the License.
80Sstevel@tonic-gate  *
90Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
100Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
110Sstevel@tonic-gate  * See the License for the specific language governing permissions
120Sstevel@tonic-gate  * and limitations under the License.
130Sstevel@tonic-gate  *
140Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
150Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
160Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
170Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
180Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
190Sstevel@tonic-gate  *
200Sstevel@tonic-gate  * CDDL HEADER END
210Sstevel@tonic-gate  */
220Sstevel@tonic-gate /*
230Sstevel@tonic-gate  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
240Sstevel@tonic-gate  * Use is subject to license terms.
250Sstevel@tonic-gate  */
260Sstevel@tonic-gate 
270Sstevel@tonic-gate #ifndef _SYS_EBUS_H
280Sstevel@tonic-gate #define	_SYS_EBUS_H
290Sstevel@tonic-gate 
300Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
310Sstevel@tonic-gate 
320Sstevel@tonic-gate #ifdef	__cplusplus
330Sstevel@tonic-gate extern "C" {
340Sstevel@tonic-gate #endif
350Sstevel@tonic-gate 
360Sstevel@tonic-gate /*
370Sstevel@tonic-gate  * driver state type:
380Sstevel@tonic-gate  */
390Sstevel@tonic-gate typedef enum { NEW = 0, ATTACHED, RESUMED, DETACHED,
400Sstevel@tonic-gate 		SUSPENDED, PM_SUSPENDED } driver_state_t;
410Sstevel@tonic-gate 
420Sstevel@tonic-gate /*
430Sstevel@tonic-gate  * The i86pc specific code fragments are to support the debug of "honeynut"
440Sstevel@tonic-gate  * and "multigrain" prototypes on i86pc platform.  Most of the fragments
450Sstevel@tonic-gate  * deal with differences in the interrupt dispatching between the prototypes
460Sstevel@tonic-gate  * and the cheerio ebus.  On the prototype boards, all interrupt lines are
470Sstevel@tonic-gate  * tied together.  For this case, the nexus driver uses a common interrupt
480Sstevel@tonic-gate  * handler to poll all of its children.
490Sstevel@tonic-gate  */
500Sstevel@tonic-gate #if defined(i86pc)
510Sstevel@tonic-gate #define	MAX_EBUS_DEVS	6
520Sstevel@tonic-gate 
530Sstevel@tonic-gate /*
540Sstevel@tonic-gate  * ebus device interrupt info;
550Sstevel@tonic-gate  */
560Sstevel@tonic-gate typedef struct {
570Sstevel@tonic-gate 	char *name;
580Sstevel@tonic-gate 	uint_t inuse;
590Sstevel@tonic-gate 	uint_t (*handler)();
600Sstevel@tonic-gate 	caddr_t arg;
610Sstevel@tonic-gate } ebus_intr_slot_t;
620Sstevel@tonic-gate #endif
630Sstevel@tonic-gate 
640Sstevel@tonic-gate struct ebus_intr_map {
650Sstevel@tonic-gate 	uint32_t ebus_phys_hi;
660Sstevel@tonic-gate 	uint32_t ebus_phys_low;
670Sstevel@tonic-gate 	uint32_t ebus_intr;
680Sstevel@tonic-gate 	uint32_t intr_ctlr_nodeid;
690Sstevel@tonic-gate 	uint32_t ino;
700Sstevel@tonic-gate };
710Sstevel@tonic-gate 
720Sstevel@tonic-gate struct ebus_intr_map_mask {
730Sstevel@tonic-gate 	uint32_t ebus_phys_hi;
740Sstevel@tonic-gate 	uint32_t ebus_phys_low;
750Sstevel@tonic-gate 	uint32_t ebus_intr;
760Sstevel@tonic-gate };
770Sstevel@tonic-gate 
780Sstevel@tonic-gate /*
79*558Sjasonwu  * definition of ebus reg spec entry:
80*558Sjasonwu  */
81*558Sjasonwu typedef struct {
82*558Sjasonwu 	uint32_t addr_hi;
83*558Sjasonwu 	uint32_t addr_low;
84*558Sjasonwu 	uint32_t size;
85*558Sjasonwu } ebus_regspec_t;
86*558Sjasonwu 
87*558Sjasonwu /* Range entry for 3-cell parent address */
88*558Sjasonwu struct ebus_pci_rangespec {
89*558Sjasonwu 	uint32_t phys_hi;			/* Child hi range address */
90*558Sjasonwu 	uint32_t phys_low;			/* Child low range address */
91*558Sjasonwu 	uint32_t par_phys_hi;			/* Parent hi rng addr */
92*558Sjasonwu 	uint32_t par_phys_mid;			/* Parent mid rng addr */
93*558Sjasonwu 	uint32_t par_phys_low;			/* Parent low rng addr */
94*558Sjasonwu 	uint32_t rng_size;			/* Range size */
95*558Sjasonwu };
96*558Sjasonwu 
97*558Sjasonwu /* Range entry for 2-cell parent address */
98*558Sjasonwu struct ebus_jbus_rangespec {
99*558Sjasonwu 	uint32_t phys_hi;			/* Child hi range address */
100*558Sjasonwu 	uint32_t phys_low;			/* Child low range address */
101*558Sjasonwu 	uint32_t par_phys_hi;			/* Parent hi rng addr */
102*558Sjasonwu 	uint32_t par_phys_low;			/* Parent low rng addr */
103*558Sjasonwu 	uint32_t rng_size;			/* Range size */
104*558Sjasonwu };
105*558Sjasonwu 
106*558Sjasonwu typedef union vrangespec {
107*558Sjasonwu 	struct ebus_pci_rangespec	pci_rangespec;
108*558Sjasonwu 	struct ebus_jbus_rangespec	jbus_rangespec;
109*558Sjasonwu } vrangespec_t;
110*558Sjasonwu 
111*558Sjasonwu typedef union vregspec {
112*558Sjasonwu 	struct pci_phys_spec	pci_regspec;
113*558Sjasonwu 	struct regspec		jbus_regspec;
114*558Sjasonwu } vregspec_t;
115*558Sjasonwu 
116*558Sjasonwu /*
1170Sstevel@tonic-gate  * driver soft state structure:
1180Sstevel@tonic-gate  */
1190Sstevel@tonic-gate typedef struct {
1200Sstevel@tonic-gate 	dev_info_t *dip;
1210Sstevel@tonic-gate 	driver_state_t state;
1220Sstevel@tonic-gate 	pci_regspec_t *reg;
1230Sstevel@tonic-gate 	int nreg;
1240Sstevel@tonic-gate 
125*558Sjasonwu 	vrangespec_t *vrangep;
126*558Sjasonwu 	int vrange_len;
127*558Sjasonwu 	int vrange_cnt;
1280Sstevel@tonic-gate 
1290Sstevel@tonic-gate 	kmutex_t ebus_mutex;
1300Sstevel@tonic-gate 	uint_t ebus_soft_state;
1310Sstevel@tonic-gate #define	EBUS_SOFT_STATE_CLOSED		0x00
1320Sstevel@tonic-gate #define	EBUS_SOFT_STATE_OPEN		0x01
1330Sstevel@tonic-gate #define	EBUS_SOFT_STATE_OPEN_EXCL	0x02
1340Sstevel@tonic-gate 
1350Sstevel@tonic-gate #if defined(i86pc)
1360Sstevel@tonic-gate 	ddi_iblock_cookie_t iblock;
1370Sstevel@tonic-gate 	ddi_idevice_cookie_t idevice;
1380Sstevel@tonic-gate 	ebus_intr_slot_t intr_slot[MAX_EBUS_DEVS];
1390Sstevel@tonic-gate #endif
1400Sstevel@tonic-gate #if defined(__sparc)
1410Sstevel@tonic-gate 	/* Interrupt support */
1420Sstevel@tonic-gate 	int intr_map_size;
1430Sstevel@tonic-gate 	struct ebus_intr_map *intr_map;
1440Sstevel@tonic-gate 	struct ebus_intr_map_mask *intr_map_mask;
1450Sstevel@tonic-gate #endif
146*558Sjasonwu 	int ebus_addr_cells;
147*558Sjasonwu 	int ebus_paddr_cells;
148*558Sjasonwu 	int ebus_psz_cells;
149*558Sjasonwu 	int ebus_sz_cells;
1500Sstevel@tonic-gate } ebus_devstate_t;
1510Sstevel@tonic-gate 
1520Sstevel@tonic-gate 
1530Sstevel@tonic-gate /*
1540Sstevel@tonic-gate  * use macros for soft state and driver properties:
1550Sstevel@tonic-gate  */
1560Sstevel@tonic-gate #define	get_ebus_soft_state(i)	\
1570Sstevel@tonic-gate 	((ebus_devstate_t *)ddi_get_soft_state(per_ebus_state, (i)))
1580Sstevel@tonic-gate 
1590Sstevel@tonic-gate #define	alloc_ebus_soft_state(i)	\
1600Sstevel@tonic-gate 	ddi_soft_state_zalloc(per_ebus_state, (i))
1610Sstevel@tonic-gate 
1620Sstevel@tonic-gate #define	free_ebus_soft_state(i)	\
1630Sstevel@tonic-gate 	ddi_soft_state_free(per_ebus_state, (i))
1640Sstevel@tonic-gate 
1650Sstevel@tonic-gate 
1660Sstevel@tonic-gate #define	getprop(dip, name, addr, intp)		\
167506Scth 		ddi_getlongprop(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, \
1680Sstevel@tonic-gate 				(name), (caddr_t)(addr), (intp))
1690Sstevel@tonic-gate 
1700Sstevel@tonic-gate #define	IS_RIO(dip) \
1710Sstevel@tonic-gate 		((ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \
1720Sstevel@tonic-gate 		"device-id", -1) == 0x1100) && \
1730Sstevel@tonic-gate 		(ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \
1740Sstevel@tonic-gate 		"vendor-id", -1) == 0x108e))
1750Sstevel@tonic-gate 
1760Sstevel@tonic-gate #define	EBUS_4MHZ	4000
1770Sstevel@tonic-gate 
1780Sstevel@tonic-gate /*
1790Sstevel@tonic-gate  * register offsets and lengths:
1800Sstevel@tonic-gate  */
1810Sstevel@tonic-gate #define	TCR_OFFSET	0x710000
1820Sstevel@tonic-gate #define	TCR_LENGTH	12
1830Sstevel@tonic-gate 
1840Sstevel@tonic-gate /*
1850Sstevel@tonic-gate  * timing control register settings:
1860Sstevel@tonic-gate  */
1870Sstevel@tonic-gate #define	TCR1		0x08101008
1880Sstevel@tonic-gate #define	TCR2		0x08100020
1890Sstevel@tonic-gate #define	TCR3		0x00000020
1900Sstevel@tonic-gate 
1910Sstevel@tonic-gate #if defined(DEBUG)
1920Sstevel@tonic-gate #define	D_IDENTIFY	0x00000001
1930Sstevel@tonic-gate #define	D_ATTACH	0x00000002
1940Sstevel@tonic-gate #define	D_DETACH	0x00000004
1950Sstevel@tonic-gate #define	D_MAP		0x00000008
1960Sstevel@tonic-gate #define	D_CTLOPS	0x00000010
1970Sstevel@tonic-gate #define	D_INTR		0x00000100
1980Sstevel@tonic-gate 
1990Sstevel@tonic-gate #define	DBG(flag, psp, fmt)	\
2000Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, 0, 0, 0, 0, 0);
2010Sstevel@tonic-gate #define	DBG1(flag, psp, fmt, a1)	\
2020Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
2030Sstevel@tonic-gate #define	DBG2(flag, psp, fmt, a1, a2)	\
2040Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
2050Sstevel@tonic-gate #define	DBG3(flag, psp, fmt, a1, a2, a3)	\
2060Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
2070Sstevel@tonic-gate 	    (uintptr_t)(a3), 0, 0);
2080Sstevel@tonic-gate #define	DBG4(flag, psp, fmt, a1, a2, a3, a4)	\
2090Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
2100Sstevel@tonic-gate 	    (uintptr_t)(a3), \
2110Sstevel@tonic-gate 		(uintptr_t)(a4), 0);
2120Sstevel@tonic-gate #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)	\
2130Sstevel@tonic-gate 	ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
2140Sstevel@tonic-gate 	    (uintptr_t)(a3), \
2150Sstevel@tonic-gate 		(uintptr_t)(a4), (uintptr_t)(a5));
2160Sstevel@tonic-gate static void
2170Sstevel@tonic-gate ebus_debug(uint_t, ebus_devstate_t *, char *, uintptr_t, uintptr_t, uintptr_t,
2180Sstevel@tonic-gate     uintptr_t, uintptr_t);
2190Sstevel@tonic-gate #else
2200Sstevel@tonic-gate #define	DBG(flag, psp, fmt)
2210Sstevel@tonic-gate #define	DBG1(flag, psp, fmt, a1)
2220Sstevel@tonic-gate #define	DBG2(flag, psp, fmt, a1, a2)
2230Sstevel@tonic-gate #define	DBG3(flag, psp, fmt, a1, a2, a3)
2240Sstevel@tonic-gate #define	DBG4(flag, psp, fmt, a1, a2, a3, a4)
2250Sstevel@tonic-gate #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)
2260Sstevel@tonic-gate #endif
2270Sstevel@tonic-gate 
2280Sstevel@tonic-gate #ifdef	__cplusplus
2290Sstevel@tonic-gate }
2300Sstevel@tonic-gate #endif
2310Sstevel@tonic-gate 
2320Sstevel@tonic-gate #endif	/* _SYS_EBUS_H */
233