1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate #include <sys/types.h> 30*0Sstevel@tonic-gate #include <sys/systm.h> 31*0Sstevel@tonic-gate #include <sys/archsystm.h> 32*0Sstevel@tonic-gate #include <sys/machsystm.h> 33*0Sstevel@tonic-gate #include <sys/disp.h> 34*0Sstevel@tonic-gate #include <sys/autoconf.h> 35*0Sstevel@tonic-gate #include <sys/promif.h> 36*0Sstevel@tonic-gate #include <sys/prom_plat.h> 37*0Sstevel@tonic-gate #include <sys/clock.h> 38*0Sstevel@tonic-gate #include <sys/pte.h> 39*0Sstevel@tonic-gate #include <sys/scb.h> 40*0Sstevel@tonic-gate #include <sys/cpu.h> 41*0Sstevel@tonic-gate #include <sys/stack.h> 42*0Sstevel@tonic-gate #include <sys/intreg.h> 43*0Sstevel@tonic-gate #include <sys/ivintr.h> 44*0Sstevel@tonic-gate #include <vm/as.h> 45*0Sstevel@tonic-gate #include <vm/hat_sfmmu.h> 46*0Sstevel@tonic-gate #include <sys/reboot.h> 47*0Sstevel@tonic-gate #include <sys/sysmacros.h> 48*0Sstevel@tonic-gate #include <sys/vtrace.h> 49*0Sstevel@tonic-gate #include <sys/trap.h> 50*0Sstevel@tonic-gate #include <sys/machtrap.h> 51*0Sstevel@tonic-gate #include <sys/privregs.h> 52*0Sstevel@tonic-gate #include <sys/machpcb.h> 53*0Sstevel@tonic-gate #include <sys/proc.h> 54*0Sstevel@tonic-gate #include <sys/cpupart.h> 55*0Sstevel@tonic-gate #include <sys/pset.h> 56*0Sstevel@tonic-gate #include <sys/cpu_module.h> 57*0Sstevel@tonic-gate #include <sys/copyops.h> 58*0Sstevel@tonic-gate #include <sys/panic.h> 59*0Sstevel@tonic-gate #include <sys/bootconf.h> /* for bootops */ 60*0Sstevel@tonic-gate #include <sys/chip.h> 61*0Sstevel@tonic-gate #include <sys/kdi.h> 62*0Sstevel@tonic-gate #include <sys/fpras.h> 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate #include <sys/prom_debug.h> 65*0Sstevel@tonic-gate #include <sys/debug.h> 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate #include <sys/sunddi.h> 68*0Sstevel@tonic-gate #include <sys/lgrp.h> 69*0Sstevel@tonic-gate 70*0Sstevel@tonic-gate #ifdef TRAPTRACE 71*0Sstevel@tonic-gate #include <sys/traptrace.h> 72*0Sstevel@tonic-gate #endif /* TRAPTRACE */ 73*0Sstevel@tonic-gate 74*0Sstevel@tonic-gate /* 75*0Sstevel@tonic-gate * External Routines: 76*0Sstevel@tonic-gate */ 77*0Sstevel@tonic-gate extern void map_wellknown_devices(void); 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate int dcache_size; 80*0Sstevel@tonic-gate int dcache_linesize; 81*0Sstevel@tonic-gate int icache_size; 82*0Sstevel@tonic-gate int icache_linesize; 83*0Sstevel@tonic-gate int ecache_size; 84*0Sstevel@tonic-gate int ecache_alignsize; 85*0Sstevel@tonic-gate int ecache_associativity; 86*0Sstevel@tonic-gate int ecache_setsize; /* max possible e$ setsize */ 87*0Sstevel@tonic-gate int cpu_setsize; /* max e$ setsize of configured cpus */ 88*0Sstevel@tonic-gate int dcache_line_mask; /* spitfire only */ 89*0Sstevel@tonic-gate int vac_size; /* cache size in bytes */ 90*0Sstevel@tonic-gate uint_t vac_mask; /* VAC alignment consistency mask */ 91*0Sstevel@tonic-gate int vac_shift; /* log2(vac_size) for ppmapout() */ 92*0Sstevel@tonic-gate int vac = 0; /* virtual address cache type (none == 0) */ 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* 95*0Sstevel@tonic-gate * fpRAS. An individual sun4* machine class (or perhaps subclass, 96*0Sstevel@tonic-gate * eg sun4u/cheetah) must set fpras_implemented to indicate that it implements 97*0Sstevel@tonic-gate * the fpRAS feature. The feature can be suppressed by setting fpras_disable 98*0Sstevel@tonic-gate * or the mechanism can be disabled for individual copy operations with 99*0Sstevel@tonic-gate * fpras_disableids. All these are checked in post_startup() code so 100*0Sstevel@tonic-gate * fpras_disable and fpras_disableids can be set in /etc/system. 101*0Sstevel@tonic-gate * If/when fpRAS is implemented on non-sun4 architectures these 102*0Sstevel@tonic-gate * definitions will need to move up to the common level. 103*0Sstevel@tonic-gate */ 104*0Sstevel@tonic-gate int fpras_implemented; 105*0Sstevel@tonic-gate int fpras_disable; 106*0Sstevel@tonic-gate int fpras_disableids; 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate /* 109*0Sstevel@tonic-gate * Static Routines: 110*0Sstevel@tonic-gate */ 111*0Sstevel@tonic-gate static void kern_splr_preprom(void); 112*0Sstevel@tonic-gate static void kern_splx_postprom(void); 113*0Sstevel@tonic-gate 114*0Sstevel@tonic-gate /* 115*0Sstevel@tonic-gate * Setup routine called right before main(). Interposing this function 116*0Sstevel@tonic-gate * before main() allows us to call it in a machine-independent fashion. 117*0Sstevel@tonic-gate */ 118*0Sstevel@tonic-gate 119*0Sstevel@tonic-gate void 120*0Sstevel@tonic-gate mlsetup(struct regs *rp, void *cif, kfpu_t *fp) 121*0Sstevel@tonic-gate { 122*0Sstevel@tonic-gate struct machpcb *mpcb; 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate extern char t0stack[]; 125*0Sstevel@tonic-gate extern struct classfuncs sys_classfuncs; 126*0Sstevel@tonic-gate extern disp_t cpu0_disp; 127*0Sstevel@tonic-gate unsigned long long pa; 128*0Sstevel@tonic-gate 129*0Sstevel@tonic-gate #ifdef TRAPTRACE 130*0Sstevel@tonic-gate TRAP_TRACE_CTL *ctlp; 131*0Sstevel@tonic-gate #endif /* TRAPTRACE */ 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate /* 134*0Sstevel@tonic-gate * initialize cpu_self 135*0Sstevel@tonic-gate */ 136*0Sstevel@tonic-gate cpu0.cpu_self = &cpu0; 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate /* 139*0Sstevel@tonic-gate * initialize t0 140*0Sstevel@tonic-gate */ 141*0Sstevel@tonic-gate t0.t_stk = (caddr_t)rp - REGOFF; 142*0Sstevel@tonic-gate /* Can't use va_to_pa here - wait until prom_ initialized */ 143*0Sstevel@tonic-gate t0.t_stkbase = t0stack; 144*0Sstevel@tonic-gate t0.t_pri = maxclsyspri - 3; 145*0Sstevel@tonic-gate t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 146*0Sstevel@tonic-gate t0.t_procp = &p0; 147*0Sstevel@tonic-gate t0.t_plockp = &p0lock.pl_lock; 148*0Sstevel@tonic-gate t0.t_lwp = &lwp0; 149*0Sstevel@tonic-gate t0.t_forw = &t0; 150*0Sstevel@tonic-gate t0.t_back = &t0; 151*0Sstevel@tonic-gate t0.t_next = &t0; 152*0Sstevel@tonic-gate t0.t_prev = &t0; 153*0Sstevel@tonic-gate t0.t_cpu = &cpu0; /* loaded by _start */ 154*0Sstevel@tonic-gate t0.t_disp_queue = &cpu0_disp; 155*0Sstevel@tonic-gate t0.t_bind_cpu = PBIND_NONE; 156*0Sstevel@tonic-gate t0.t_bind_pset = PS_NONE; 157*0Sstevel@tonic-gate t0.t_cpupart = &cp_default; 158*0Sstevel@tonic-gate t0.t_clfuncs = &sys_classfuncs.thread; 159*0Sstevel@tonic-gate t0.t_copyops = NULL; 160*0Sstevel@tonic-gate THREAD_ONPROC(&t0, CPU); 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate lwp0.lwp_thread = &t0; 163*0Sstevel@tonic-gate lwp0.lwp_procp = &p0; 164*0Sstevel@tonic-gate lwp0.lwp_regs = (void *)rp; 165*0Sstevel@tonic-gate t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate mpcb = lwptompcb(&lwp0); 168*0Sstevel@tonic-gate mpcb->mpcb_fpu = fp; 169*0Sstevel@tonic-gate mpcb->mpcb_fpu->fpu_q = mpcb->mpcb_fpu_q; 170*0Sstevel@tonic-gate mpcb->mpcb_thread = &t0; 171*0Sstevel@tonic-gate lwp0.lwp_fpu = (void *)mpcb->mpcb_fpu; 172*0Sstevel@tonic-gate 173*0Sstevel@tonic-gate p0.p_exec = NULL; 174*0Sstevel@tonic-gate p0.p_stat = SRUN; 175*0Sstevel@tonic-gate p0.p_flag = SSYS; 176*0Sstevel@tonic-gate p0.p_tlist = &t0; 177*0Sstevel@tonic-gate p0.p_stksize = 2*PAGESIZE; 178*0Sstevel@tonic-gate p0.p_stkpageszc = 0; 179*0Sstevel@tonic-gate p0.p_as = &kas; 180*0Sstevel@tonic-gate p0.p_lockp = &p0lock; 181*0Sstevel@tonic-gate p0.p_utraps = NULL; 182*0Sstevel@tonic-gate p0.p_brkpageszc = 0; 183*0Sstevel@tonic-gate sigorset(&p0.p_ignore, &ignoredefault); 184*0Sstevel@tonic-gate 185*0Sstevel@tonic-gate CPU->cpu_thread = &t0; 186*0Sstevel@tonic-gate CPU->cpu_dispthread = &t0; 187*0Sstevel@tonic-gate bzero(&cpu0_disp, sizeof (disp_t)); 188*0Sstevel@tonic-gate CPU->cpu_disp = &cpu0_disp; 189*0Sstevel@tonic-gate CPU->cpu_disp->disp_cpu = CPU; 190*0Sstevel@tonic-gate CPU->cpu_idle_thread = &t0; 191*0Sstevel@tonic-gate CPU->cpu_flags = CPU_RUNNING; 192*0Sstevel@tonic-gate CPU->cpu_id = getprocessorid(); 193*0Sstevel@tonic-gate CPU->cpu_dispatch_pri = t0.t_pri; 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate /* 196*0Sstevel@tonic-gate * Initialize thread/cpu microstate accounting here 197*0Sstevel@tonic-gate */ 198*0Sstevel@tonic-gate init_mstate(&t0, LMS_SYSTEM); 199*0Sstevel@tonic-gate init_cpu_mstate(CPU, CMS_SYSTEM); 200*0Sstevel@tonic-gate 201*0Sstevel@tonic-gate /* 202*0Sstevel@tonic-gate * Initialize lists of available and active CPUs. 203*0Sstevel@tonic-gate */ 204*0Sstevel@tonic-gate cpu_list_init(CPU); 205*0Sstevel@tonic-gate 206*0Sstevel@tonic-gate prom_init("kernel", cif); 207*0Sstevel@tonic-gate (void) prom_set_preprom(kern_splr_preprom); 208*0Sstevel@tonic-gate (void) prom_set_postprom(kern_splx_postprom); 209*0Sstevel@tonic-gate 210*0Sstevel@tonic-gate PRM_INFO("mlsetup: now ok to call prom_printf"); 211*0Sstevel@tonic-gate 212*0Sstevel@tonic-gate mpcb->mpcb_pa = va_to_pa(t0.t_stk); 213*0Sstevel@tonic-gate 214*0Sstevel@tonic-gate /* 215*0Sstevel@tonic-gate * Claim the physical and virtual resources used by panicbuf, 216*0Sstevel@tonic-gate * then map panicbuf. This operation removes the phys and 217*0Sstevel@tonic-gate * virtual addresses from the free lists. 218*0Sstevel@tonic-gate */ 219*0Sstevel@tonic-gate if (prom_claim_virt(PANICBUFSIZE, panicbuf) != panicbuf) 220*0Sstevel@tonic-gate prom_panic("Can't claim panicbuf virtual address"); 221*0Sstevel@tonic-gate 222*0Sstevel@tonic-gate if (prom_retain("panicbuf", PANICBUFSIZE, MMU_PAGESIZE, &pa) != 0) 223*0Sstevel@tonic-gate prom_panic("Can't allocate retained panicbuf physical address"); 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate if (prom_map_phys(-1, PANICBUFSIZE, panicbuf, pa) != 0) 226*0Sstevel@tonic-gate prom_panic("Can't map panicbuf"); 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate PRM_DEBUG(panicbuf); 229*0Sstevel@tonic-gate PRM_DEBUG(pa); 230*0Sstevel@tonic-gate 231*0Sstevel@tonic-gate #ifdef TRAPTRACE 232*0Sstevel@tonic-gate /* 233*0Sstevel@tonic-gate * initialize the trap trace buffer for the boot cpu 234*0Sstevel@tonic-gate * XXX todo, dynamically allocate this buffer too 235*0Sstevel@tonic-gate */ 236*0Sstevel@tonic-gate ctlp = &trap_trace_ctl[CPU->cpu_id]; 237*0Sstevel@tonic-gate ctlp->d.vaddr_base = trap_tr0; 238*0Sstevel@tonic-gate ctlp->d.offset = ctlp->d.last_offset = 0; 239*0Sstevel@tonic-gate ctlp->d.limit = TRAP_TSIZE; /* XXX dynamic someday */ 240*0Sstevel@tonic-gate ctlp->d.paddr_base = va_to_pa(trap_tr0); 241*0Sstevel@tonic-gate /* 242*0Sstevel@tonic-gate * initialize HV trap trace buffer for the boot cpu 243*0Sstevel@tonic-gate */ 244*0Sstevel@tonic-gate htrap_trace_setup((trap_tr0 + TRAP_TSIZE), CPU->cpu_id); 245*0Sstevel@tonic-gate htrap_trace_register(CPU->cpu_id); 246*0Sstevel@tonic-gate #endif /* TRAPTRACE */ 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate /* 249*0Sstevel@tonic-gate * lgroup framework initialization. This must be done prior 250*0Sstevel@tonic-gate * to devices being mapped. 251*0Sstevel@tonic-gate */ 252*0Sstevel@tonic-gate lgrp_init(); 253*0Sstevel@tonic-gate 254*0Sstevel@tonic-gate cpu_setup(); 255*0Sstevel@tonic-gate 256*0Sstevel@tonic-gate if (boothowto & RB_HALT) { 257*0Sstevel@tonic-gate prom_printf("unix: kernel halted by -h flag\n"); 258*0Sstevel@tonic-gate prom_enter_mon(); 259*0Sstevel@tonic-gate } 260*0Sstevel@tonic-gate 261*0Sstevel@tonic-gate setcputype(); 262*0Sstevel@tonic-gate map_wellknown_devices(); 263*0Sstevel@tonic-gate setcpudelay(); 264*0Sstevel@tonic-gate 265*0Sstevel@tonic-gate /* 266*0Sstevel@tonic-gate * Associate the boot cpu with a physical processor. 267*0Sstevel@tonic-gate * This needs to be done after devices are mapped, since 268*0Sstevel@tonic-gate * we need to know what type of physical processor this is. 269*0Sstevel@tonic-gate * (CMP for example) 270*0Sstevel@tonic-gate */ 271*0Sstevel@tonic-gate chip_cpu_init(CPU); 272*0Sstevel@tonic-gate chip_cpu_assign(CPU); 273*0Sstevel@tonic-gate } 274*0Sstevel@tonic-gate 275*0Sstevel@tonic-gate /* 276*0Sstevel@tonic-gate * These routines are called immediately before and 277*0Sstevel@tonic-gate * immediately after calling into the firmware. The 278*0Sstevel@tonic-gate * firmware is significantly confused by preemption - 279*0Sstevel@tonic-gate * particularly on MP machines - but also on UP's too. 280*0Sstevel@tonic-gate */ 281*0Sstevel@tonic-gate 282*0Sstevel@tonic-gate static int saved_spl; 283*0Sstevel@tonic-gate 284*0Sstevel@tonic-gate static void 285*0Sstevel@tonic-gate kern_splr_preprom(void) 286*0Sstevel@tonic-gate { 287*0Sstevel@tonic-gate saved_spl = spl7(); 288*0Sstevel@tonic-gate } 289*0Sstevel@tonic-gate 290*0Sstevel@tonic-gate static void 291*0Sstevel@tonic-gate kern_splx_postprom(void) 292*0Sstevel@tonic-gate { 293*0Sstevel@tonic-gate splx(saved_spl); 294*0Sstevel@tonic-gate } 295