10Sstevel@tonic-gate /* 20Sstevel@tonic-gate * CDDL HEADER START 30Sstevel@tonic-gate * 40Sstevel@tonic-gate * The contents of this file are subject to the terms of the 51455Sandrei * Common Development and Distribution License (the "License"). 61455Sandrei * You may not use this file except in compliance with the License. 70Sstevel@tonic-gate * 80Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 100Sstevel@tonic-gate * See the License for the specific language governing permissions 110Sstevel@tonic-gate * and limitations under the License. 120Sstevel@tonic-gate * 130Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 140Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 160Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 170Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 180Sstevel@tonic-gate * 190Sstevel@tonic-gate * CDDL HEADER END 200Sstevel@tonic-gate */ 210Sstevel@tonic-gate /* 224652Scwb * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 230Sstevel@tonic-gate * Use is subject to license terms. 240Sstevel@tonic-gate */ 250Sstevel@tonic-gate 260Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 270Sstevel@tonic-gate 280Sstevel@tonic-gate #include <sys/sysmacros.h> 290Sstevel@tonic-gate #include <sys/stack.h> 300Sstevel@tonic-gate #include <sys/cpuvar.h> 310Sstevel@tonic-gate #include <sys/ivintr.h> 320Sstevel@tonic-gate #include <sys/intreg.h> 330Sstevel@tonic-gate #include <sys/membar.h> 340Sstevel@tonic-gate #include <sys/kmem.h> 350Sstevel@tonic-gate #include <sys/intr.h> 36*5107Seota #include <sys/sunddi.h> 370Sstevel@tonic-gate #include <sys/sunndi.h> 380Sstevel@tonic-gate #include <sys/cmn_err.h> 390Sstevel@tonic-gate #include <sys/privregs.h> 400Sstevel@tonic-gate #include <sys/systm.h> 410Sstevel@tonic-gate #include <sys/archsystm.h> 420Sstevel@tonic-gate #include <sys/machsystm.h> 430Sstevel@tonic-gate #include <sys/x_call.h> 440Sstevel@tonic-gate #include <vm/seg_kp.h> 450Sstevel@tonic-gate #include <sys/debug.h> 460Sstevel@tonic-gate #include <sys/cyclic.h> 474652Scwb #include <sys/kdi_impl.h> 48*5107Seota #include <sys/ddi_timer.h> 490Sstevel@tonic-gate 500Sstevel@tonic-gate #include <sys/cpu_sgnblk_defs.h> 510Sstevel@tonic-gate 520Sstevel@tonic-gate /* Global locks which protect the interrupt distribution lists */ 530Sstevel@tonic-gate static kmutex_t intr_dist_lock; 540Sstevel@tonic-gate static kmutex_t intr_dist_cpu_lock; 550Sstevel@tonic-gate 560Sstevel@tonic-gate /* Head of the interrupt distribution lists */ 570Sstevel@tonic-gate static struct intr_dist *intr_dist_head = NULL; 580Sstevel@tonic-gate static struct intr_dist *intr_dist_whead = NULL; 590Sstevel@tonic-gate 60*5107Seota static uint64_t siron_inum[DDI_IPL_10]; /* software interrupt numbers */ 615076Smishra uint64_t *siron_cpu_inum = NULL; 625076Smishra uint64_t siron_poke_cpu_inum; 635076Smishra static int siron_cpu_setup(cpu_setup_t, int, void *); 645076Smishra extern uint_t softlevel1(); 655076Smishra 66*5107Seota static uint64_t siron1_inum; /* backward compatibility */ 672973Sgovinda uint64_t poke_cpu_inum; 682973Sgovinda uint_t poke_cpu_intr(caddr_t arg1, caddr_t arg2); 695076Smishra uint_t siron_poke_cpu_intr(caddr_t arg1, caddr_t arg2); 702973Sgovinda 71522Ssudheer /* 72522Ssudheer * Note:- 73522Ssudheer * siron_pending was originally created to prevent a resource over consumption 74522Ssudheer * bug in setsoftint(exhaustion of interrupt pool free list). 75522Ssudheer * It's original intention is obsolete with the use of iv_pending in 76522Ssudheer * setsoftint. However, siron_pending stayed around, acting as a second 77522Ssudheer * gatekeeper preventing soft interrupts from being queued. In this capacity, 78522Ssudheer * it can lead to hangs on MP systems, where due to global visibility issues 79522Ssudheer * it can end up set while iv_pending is reset, preventing soft interrupts from 80522Ssudheer * ever being processed. In addition to its gatekeeper role, init_intr also 81522Ssudheer * uses it to flag the situation where siron() was called before siron_inum has 82522Ssudheer * been defined. 83522Ssudheer * 84522Ssudheer * siron() does not need an extra gatekeeper; any cpu that wishes should be 85522Ssudheer * allowed to queue a soft interrupt. It is softint()'s job to ensure 86522Ssudheer * correct handling of the queues. Therefore, siron_pending has been 87522Ssudheer * stripped of its gatekeeper task, retaining only its intr_init job, where 88522Ssudheer * it indicates that there is a pending need to call siron(). 89522Ssudheer */ 90*5107Seota static int siron_pending[DDI_IPL_10]; /* software interrupt pending flags */ 91*5107Seota static int siron1_pending; /* backward compatibility */ 920Sstevel@tonic-gate 930Sstevel@tonic-gate int intr_policy = INTR_WEIGHTED_DIST; /* interrupt distribution policy */ 940Sstevel@tonic-gate int intr_dist_debug = 0; 950Sstevel@tonic-gate int32_t intr_dist_weight_max = 1; 960Sstevel@tonic-gate int32_t intr_dist_weight_maxmax = 1000; 970Sstevel@tonic-gate int intr_dist_weight_maxfactor = 2; 980Sstevel@tonic-gate #define INTR_DEBUG(args) if (intr_dist_debug) cmn_err args 990Sstevel@tonic-gate 1000Sstevel@tonic-gate /* 1012973Sgovinda * intr_init() - Interrupt initialization 1022973Sgovinda * Initialize the system's interrupt vector table. 1030Sstevel@tonic-gate */ 1040Sstevel@tonic-gate void 1050Sstevel@tonic-gate intr_init(cpu_t *cp) 1060Sstevel@tonic-gate { 107*5107Seota int i; 1082973Sgovinda extern uint_t softlevel1(); 1092973Sgovinda 1100Sstevel@tonic-gate init_ivintr(); 1112973Sgovinda REGISTER_BBUS_INTR(); 1122973Sgovinda 1135076Smishra /* 1145076Smishra * We just allocate memory for per-cpu siron right now. Rest of 1155076Smishra * the work is done when CPU is configured. 1165076Smishra */ 1175076Smishra siron_cpu_inum = kmem_zalloc(sizeof (uint64_t) * NCPU, KM_SLEEP); 118*5107Seota /* 119*5107Seota * Register these software interrupts for ddi timer. 120*5107Seota * Software interrupts up to the level 10 are supported. 121*5107Seota */ 122*5107Seota for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) { 123*5107Seota siron_inum[i-1] = add_softintr(i, (softintrfunc)timer_softintr, 124*5107Seota (caddr_t)(uintptr_t)(i), SOFTINT_ST); 125*5107Seota } 126*5107Seota 127*5107Seota siron1_inum = add_softintr(PIL_1, softlevel1, 0, SOFTINT_ST); 1282973Sgovinda poke_cpu_inum = add_softintr(PIL_13, poke_cpu_intr, 0, SOFTINT_MT); 1295076Smishra siron_poke_cpu_inum = add_softintr(PIL_13, 1305076Smishra siron_poke_cpu_intr, 0, SOFTINT_MT); 1312973Sgovinda cp->cpu_m.poke_cpu_outstanding = B_FALSE; 1320Sstevel@tonic-gate 1330Sstevel@tonic-gate mutex_init(&intr_dist_lock, NULL, MUTEX_DEFAULT, NULL); 1340Sstevel@tonic-gate mutex_init(&intr_dist_cpu_lock, NULL, MUTEX_DEFAULT, NULL); 1350Sstevel@tonic-gate 1360Sstevel@tonic-gate /* 1370Sstevel@tonic-gate * A soft interrupt may have been requested prior to the initialization 1380Sstevel@tonic-gate * of soft interrupts. Soft interrupts can't be dispatched until after 1392973Sgovinda * init_intr(), so we have to wait until now before we can dispatch the 1402973Sgovinda * pending soft interrupt (if any). 1410Sstevel@tonic-gate */ 142*5107Seota for (i = DDI_IPL_1; i <= DDI_IPL_10; i++) { 143*5107Seota if (siron_pending[i-1]) { 144*5107Seota siron_pending[i-1] = 0; 145*5107Seota sir_on(i); 146*5107Seota } 147*5107Seota } 148*5107Seota if (siron1_pending) { 149*5107Seota siron1_pending = 0; 150522Ssudheer siron(); 151522Ssudheer } 1520Sstevel@tonic-gate } 1530Sstevel@tonic-gate 1540Sstevel@tonic-gate /* 1550Sstevel@tonic-gate * poke_cpu_intr - fall through when poke_cpu calls 1560Sstevel@tonic-gate */ 1570Sstevel@tonic-gate /* ARGSUSED */ 1580Sstevel@tonic-gate uint_t 1590Sstevel@tonic-gate poke_cpu_intr(caddr_t arg1, caddr_t arg2) 1600Sstevel@tonic-gate { 1610Sstevel@tonic-gate CPU->cpu_m.poke_cpu_outstanding = B_FALSE; 1620Sstevel@tonic-gate membar_stld_stst(); 1630Sstevel@tonic-gate return (1); 1640Sstevel@tonic-gate } 1650Sstevel@tonic-gate 1660Sstevel@tonic-gate /* 167*5107Seota * Trigger software interrupts dedicated to ddi timer. 168*5107Seota */ 169*5107Seota void 170*5107Seota sir_on(int level) 171*5107Seota { 172*5107Seota ASSERT(level >= DDI_IPL_1 && level <= DDI_IPL_10); 173*5107Seota if (siron_inum[level-1]) 174*5107Seota setsoftint(siron_inum[level-1]); 175*5107Seota else 176*5107Seota siron_pending[level-1] = 1; 177*5107Seota } 178*5107Seota 179*5107Seota /* 1804652Scwb * kmdb uses siron (and thus setsoftint) while the world is stopped in order to 1814652Scwb * inform its driver component that there's work to be done. We need to keep 1824652Scwb * DTrace from instrumenting kmdb's siron and setsoftint. We duplicate siron, 1834652Scwb * giving kmdb's version a kdi_ prefix to keep DTrace at bay. The 1844652Scwb * implementation of setsoftint is complicated enough that we don't want to 1854652Scwb * duplicate it, but at the same time we don't want to preclude tracing either. 1864652Scwb * The meat of setsoftint() therefore goes into kdi_setsoftint, with 1874652Scwb * setsoftint() implemented as a wrapper. This allows tracing, while still 1884652Scwb * providing a way for kmdb to sneak in unmolested. 1890Sstevel@tonic-gate */ 1900Sstevel@tonic-gate void 1914652Scwb kdi_siron(void) 1924652Scwb { 193*5107Seota if (siron1_inum != 0) 194*5107Seota kdi_setsoftint(siron1_inum); 1954652Scwb else 196*5107Seota siron1_pending = 1; 1974652Scwb } 1984652Scwb 1994652Scwb void 2004652Scwb setsoftint(uint64_t inum) 2014652Scwb { 2024652Scwb kdi_setsoftint(inum); 2034652Scwb } 2044652Scwb 2055076Smishra /* 2065076Smishra * Generates softlevel1 interrupt on current CPU if it 2075076Smishra * is not pending already. 2085076Smishra */ 2094652Scwb void 2100Sstevel@tonic-gate siron(void) 2110Sstevel@tonic-gate { 2125076Smishra uint64_t inum; 2135076Smishra 214*5107Seota if (siron1_inum != 0) { 2155076Smishra if (siron_cpu_inum[CPU->cpu_id] != 0) 2165076Smishra inum = siron_cpu_inum[CPU->cpu_id]; 2175076Smishra else 218*5107Seota inum = siron1_inum; 2195076Smishra 2205076Smishra setsoftint(inum); 2215076Smishra } else 222*5107Seota siron1_pending = 1; 2230Sstevel@tonic-gate } 2240Sstevel@tonic-gate 2250Sstevel@tonic-gate /* 2265076Smishra * This routine creates per-CPU siron inum for CPUs which are 2275076Smishra * configured during boot. 2285076Smishra */ 2295076Smishra void 2305076Smishra siron_mp_init() 2315076Smishra { 2325076Smishra cpu_t *c; 2335076Smishra 2345076Smishra mutex_enter(&cpu_lock); 2355076Smishra c = cpu_list; 2365076Smishra do { 2375076Smishra (void) siron_cpu_setup(CPU_CONFIG, c->cpu_id, NULL); 2385076Smishra } while ((c = c->cpu_next) != cpu_list); 2395076Smishra 2405076Smishra register_cpu_setup_func(siron_cpu_setup, NULL); 2415076Smishra mutex_exit(&cpu_lock); 2425076Smishra } 2435076Smishra 2445076Smishra /* 2455076Smishra * siron_poke_cpu_intr - cross-call handler. 2465076Smishra */ 2475076Smishra /* ARGSUSED */ 2485076Smishra uint_t 2495076Smishra siron_poke_cpu_intr(caddr_t arg1, caddr_t arg2) 2505076Smishra { 2515076Smishra /* generate level1 softint */ 2525076Smishra siron(); 2535076Smishra return (1); 2545076Smishra } 2555076Smishra 2565076Smishra /* 2575076Smishra * This routine generates a cross-call on target CPU(s). 2585076Smishra */ 2595076Smishra void 2605076Smishra siron_poke_cpu(cpuset_t poke) 2615076Smishra { 2625076Smishra int cpuid = CPU->cpu_id; 2635076Smishra 2645076Smishra if (CPU_IN_SET(poke, cpuid)) { 2655076Smishra siron(); 2665076Smishra CPUSET_DEL(poke, cpuid); 2675076Smishra if (CPUSET_ISNULL(poke)) 2685076Smishra return; 2695076Smishra } 2705076Smishra 2715076Smishra xt_some(poke, setsoftint_tl1, siron_poke_cpu_inum, 0); 2725076Smishra } 2735076Smishra 2745076Smishra /* 2755076Smishra * This callback function allows us to create per-CPU siron inum. 2765076Smishra */ 2775076Smishra /* ARGSUSED */ 2785076Smishra static int 2795076Smishra siron_cpu_setup(cpu_setup_t what, int id, void *arg) 2805076Smishra { 2815076Smishra cpu_t *cp = cpu[id]; 2825076Smishra 2835076Smishra ASSERT(MUTEX_HELD(&cpu_lock)); 2845076Smishra ASSERT(cp != NULL); 2855076Smishra 2865076Smishra switch (what) { 2875076Smishra case CPU_CONFIG: 2885076Smishra siron_cpu_inum[cp->cpu_id] = add_softintr(PIL_1, 2895076Smishra (softintrfunc)softlevel1, 0, SOFTINT_ST); 2905076Smishra break; 2915076Smishra case CPU_UNCONFIG: 2925076Smishra (void) rem_softintr(siron_cpu_inum[cp->cpu_id]); 2935076Smishra siron_cpu_inum[cp->cpu_id] = 0; 2945076Smishra break; 2955076Smishra default: 2965076Smishra break; 2975076Smishra } 2985076Smishra 2995076Smishra return (0); 3005076Smishra } 3015076Smishra 3025076Smishra /* 3030Sstevel@tonic-gate * no_ivintr() 3042973Sgovinda * called by setvecint_tl1() through sys_trap() 3050Sstevel@tonic-gate * vector interrupt received but not valid or not 3062973Sgovinda * registered in intr_vec_table 3070Sstevel@tonic-gate * considered as a spurious mondo interrupt 3080Sstevel@tonic-gate */ 3090Sstevel@tonic-gate /* ARGSUSED */ 3100Sstevel@tonic-gate void 3110Sstevel@tonic-gate no_ivintr(struct regs *rp, int inum, int pil) 3120Sstevel@tonic-gate { 3130Sstevel@tonic-gate cmn_err(CE_WARN, "invalid vector intr: number 0x%x, pil 0x%x", 3140Sstevel@tonic-gate inum, pil); 3150Sstevel@tonic-gate 3160Sstevel@tonic-gate #ifdef DEBUG_VEC_INTR 3170Sstevel@tonic-gate prom_enter_mon(); 3180Sstevel@tonic-gate #endif /* DEBUG_VEC_INTR */ 3190Sstevel@tonic-gate } 3200Sstevel@tonic-gate 3210Sstevel@tonic-gate void 3222973Sgovinda intr_dequeue_req(uint_t pil, uint64_t inum) 3230Sstevel@tonic-gate { 3242973Sgovinda intr_vec_t *iv, *next, *prev; 3252973Sgovinda struct machcpu *mcpu; 3262973Sgovinda uint32_t clr; 3272973Sgovinda processorid_t cpu_id; 3282973Sgovinda extern uint_t getpstate(void); 3290Sstevel@tonic-gate 3300Sstevel@tonic-gate ASSERT((getpstate() & PSTATE_IE) == 0); 3310Sstevel@tonic-gate 3320Sstevel@tonic-gate mcpu = &CPU->cpu_m; 3332973Sgovinda cpu_id = CPU->cpu_id; 3342973Sgovinda 3352973Sgovinda iv = (intr_vec_t *)inum; 3362973Sgovinda prev = NULL; 3372973Sgovinda next = mcpu->intr_head[pil]; 3380Sstevel@tonic-gate 3390Sstevel@tonic-gate /* Find a matching entry in the list */ 3402973Sgovinda while (next != NULL) { 3412973Sgovinda if (next == iv) 3420Sstevel@tonic-gate break; 3432973Sgovinda prev = next; 3442973Sgovinda next = IV_GET_PIL_NEXT(next, cpu_id); 3450Sstevel@tonic-gate } 3460Sstevel@tonic-gate 3472973Sgovinda if (next != NULL) { 3482973Sgovinda intr_vec_t *next_iv = IV_GET_PIL_NEXT(next, cpu_id); 3492973Sgovinda 3502973Sgovinda /* Remove entry from list */ 3512973Sgovinda if (prev != NULL) 3522973Sgovinda IV_SET_PIL_NEXT(prev, cpu_id, next_iv); /* non-head */ 3532973Sgovinda else 3542973Sgovinda mcpu->intr_head[pil] = next_iv; /* head */ 3552973Sgovinda 3562973Sgovinda if (next_iv == NULL) 3572973Sgovinda mcpu->intr_tail[pil] = prev; /* tail */ 3582973Sgovinda } 3592973Sgovinda 3602973Sgovinda /* Clear pending interrupts at this level if the list is empty */ 3610Sstevel@tonic-gate if (mcpu->intr_head[pil] == NULL) { 3620Sstevel@tonic-gate clr = 1 << pil; 3630Sstevel@tonic-gate if (pil == PIL_14) 3640Sstevel@tonic-gate clr |= (TICK_INT_MASK | STICK_INT_MASK); 3650Sstevel@tonic-gate wr_clr_softint(clr); 3660Sstevel@tonic-gate } 3670Sstevel@tonic-gate } 3680Sstevel@tonic-gate 3690Sstevel@tonic-gate 3700Sstevel@tonic-gate /* 3710Sstevel@tonic-gate * Send a directed interrupt of specified interrupt number id to a cpu. 3720Sstevel@tonic-gate */ 3730Sstevel@tonic-gate void 3740Sstevel@tonic-gate send_dirint( 3750Sstevel@tonic-gate int cpuix, /* cpu to be interrupted */ 3760Sstevel@tonic-gate int intr_id) /* interrupt number id */ 3770Sstevel@tonic-gate { 3780Sstevel@tonic-gate xt_one(cpuix, setsoftint_tl1, intr_id, 0); 3790Sstevel@tonic-gate } 3800Sstevel@tonic-gate 3810Sstevel@tonic-gate /* 3820Sstevel@tonic-gate * Take the specified CPU out of participation in interrupts. 3830Sstevel@tonic-gate * Called by p_online(2) when a processor is being taken off-line. 3840Sstevel@tonic-gate * This allows interrupt threads being handled on the processor to 3850Sstevel@tonic-gate * complete before the processor is idled. 3860Sstevel@tonic-gate */ 3870Sstevel@tonic-gate int 3880Sstevel@tonic-gate cpu_disable_intr(struct cpu *cp) 3890Sstevel@tonic-gate { 3900Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 3910Sstevel@tonic-gate 3920Sstevel@tonic-gate /* 3930Sstevel@tonic-gate * Turn off the CPU_ENABLE flag before calling the redistribution 3940Sstevel@tonic-gate * function, since it checks for this in the cpu flags. 3950Sstevel@tonic-gate */ 3960Sstevel@tonic-gate cp->cpu_flags &= ~CPU_ENABLE; 3970Sstevel@tonic-gate 3980Sstevel@tonic-gate intr_redist_all_cpus(); 3990Sstevel@tonic-gate 4000Sstevel@tonic-gate return (0); 4010Sstevel@tonic-gate } 4020Sstevel@tonic-gate 4030Sstevel@tonic-gate /* 4040Sstevel@tonic-gate * Allow the specified CPU to participate in interrupts. 4050Sstevel@tonic-gate * Called by p_online(2) if a processor could not be taken off-line 4060Sstevel@tonic-gate * because of bound threads, in order to resume processing interrupts. 4070Sstevel@tonic-gate * Also called after starting a processor. 4080Sstevel@tonic-gate */ 4090Sstevel@tonic-gate void 4100Sstevel@tonic-gate cpu_enable_intr(struct cpu *cp) 4110Sstevel@tonic-gate { 4120Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 4130Sstevel@tonic-gate 4140Sstevel@tonic-gate cp->cpu_flags |= CPU_ENABLE; 4150Sstevel@tonic-gate 4160Sstevel@tonic-gate intr_redist_all_cpus(); 4170Sstevel@tonic-gate } 4180Sstevel@tonic-gate 4190Sstevel@tonic-gate /* 4200Sstevel@tonic-gate * Add function to callback list for intr_redist_all_cpus. We keep two lists, 4210Sstevel@tonic-gate * one for weighted callbacks and one for normal callbacks. Weighted callbacks 4220Sstevel@tonic-gate * are issued to redirect interrupts of a specified weight, from heavy to 4230Sstevel@tonic-gate * light. This allows all the interrupts of a given weight to be redistributed 4240Sstevel@tonic-gate * for all weighted nexus drivers prior to those of less weight. 4250Sstevel@tonic-gate */ 4260Sstevel@tonic-gate static void 4270Sstevel@tonic-gate intr_dist_add_list(struct intr_dist **phead, void (*func)(void *), void *arg) 4280Sstevel@tonic-gate { 4290Sstevel@tonic-gate struct intr_dist *new = kmem_alloc(sizeof (*new), KM_SLEEP); 4300Sstevel@tonic-gate struct intr_dist *iptr; 4310Sstevel@tonic-gate struct intr_dist **pptr; 4320Sstevel@tonic-gate 4330Sstevel@tonic-gate ASSERT(func); 4340Sstevel@tonic-gate new->func = func; 4350Sstevel@tonic-gate new->arg = arg; 4360Sstevel@tonic-gate new->next = NULL; 4370Sstevel@tonic-gate 4380Sstevel@tonic-gate /* Add to tail so that redistribution occurs in original order. */ 4390Sstevel@tonic-gate mutex_enter(&intr_dist_lock); 4400Sstevel@tonic-gate for (iptr = *phead, pptr = phead; iptr != NULL; 4410Sstevel@tonic-gate pptr = &iptr->next, iptr = iptr->next) { 4420Sstevel@tonic-gate /* check for problems as we locate the tail */ 4430Sstevel@tonic-gate if ((iptr->func == func) && (iptr->arg == arg)) { 4440Sstevel@tonic-gate cmn_err(CE_PANIC, "intr_dist_add_list(): duplicate"); 4450Sstevel@tonic-gate /*NOTREACHED*/ 4460Sstevel@tonic-gate } 4470Sstevel@tonic-gate } 4480Sstevel@tonic-gate *pptr = new; 4490Sstevel@tonic-gate 4500Sstevel@tonic-gate mutex_exit(&intr_dist_lock); 4510Sstevel@tonic-gate } 4520Sstevel@tonic-gate 4530Sstevel@tonic-gate void 4540Sstevel@tonic-gate intr_dist_add(void (*func)(void *), void *arg) 4550Sstevel@tonic-gate { 4560Sstevel@tonic-gate intr_dist_add_list(&intr_dist_head, (void (*)(void *))func, arg); 4570Sstevel@tonic-gate } 4580Sstevel@tonic-gate 4590Sstevel@tonic-gate void 4600Sstevel@tonic-gate intr_dist_add_weighted(void (*func)(void *, int32_t, int32_t), void *arg) 4610Sstevel@tonic-gate { 4620Sstevel@tonic-gate intr_dist_add_list(&intr_dist_whead, (void (*)(void *))func, arg); 4630Sstevel@tonic-gate } 4640Sstevel@tonic-gate 4650Sstevel@tonic-gate /* 4660Sstevel@tonic-gate * Search for the interrupt distribution structure with the specified 4670Sstevel@tonic-gate * mondo vec reg in the interrupt distribution list. If a match is found, 4680Sstevel@tonic-gate * then delete the entry from the list. The caller is responsible for 4690Sstevel@tonic-gate * modifying the mondo vector registers. 4700Sstevel@tonic-gate */ 4710Sstevel@tonic-gate static void 4720Sstevel@tonic-gate intr_dist_rem_list(struct intr_dist **headp, void (*func)(void *), void *arg) 4730Sstevel@tonic-gate { 4740Sstevel@tonic-gate struct intr_dist *iptr; 4750Sstevel@tonic-gate struct intr_dist **vect; 4760Sstevel@tonic-gate 4770Sstevel@tonic-gate mutex_enter(&intr_dist_lock); 4780Sstevel@tonic-gate for (iptr = *headp, vect = headp; 4790Sstevel@tonic-gate iptr != NULL; vect = &iptr->next, iptr = iptr->next) { 4800Sstevel@tonic-gate if ((iptr->func == func) && (iptr->arg == arg)) { 4810Sstevel@tonic-gate *vect = iptr->next; 4820Sstevel@tonic-gate kmem_free(iptr, sizeof (struct intr_dist)); 4830Sstevel@tonic-gate mutex_exit(&intr_dist_lock); 4840Sstevel@tonic-gate return; 4850Sstevel@tonic-gate } 4860Sstevel@tonic-gate } 4870Sstevel@tonic-gate 4880Sstevel@tonic-gate if (!panicstr) 4890Sstevel@tonic-gate cmn_err(CE_PANIC, "intr_dist_rem_list: not found"); 4900Sstevel@tonic-gate mutex_exit(&intr_dist_lock); 4910Sstevel@tonic-gate } 4920Sstevel@tonic-gate 4930Sstevel@tonic-gate void 4940Sstevel@tonic-gate intr_dist_rem(void (*func)(void *), void *arg) 4950Sstevel@tonic-gate { 4960Sstevel@tonic-gate intr_dist_rem_list(&intr_dist_head, (void (*)(void *))func, arg); 4970Sstevel@tonic-gate } 4980Sstevel@tonic-gate 4990Sstevel@tonic-gate void 5000Sstevel@tonic-gate intr_dist_rem_weighted(void (*func)(void *, int32_t, int32_t), void *arg) 5010Sstevel@tonic-gate { 5020Sstevel@tonic-gate intr_dist_rem_list(&intr_dist_whead, (void (*)(void *))func, arg); 5030Sstevel@tonic-gate } 5040Sstevel@tonic-gate 5050Sstevel@tonic-gate /* 5060Sstevel@tonic-gate * Initiate interrupt redistribution. Redistribution improves the isolation 5070Sstevel@tonic-gate * associated with interrupt weights by ordering operations from heavy weight 5080Sstevel@tonic-gate * to light weight. When a CPUs orientation changes relative to interrupts, 5090Sstevel@tonic-gate * there is *always* a redistribution to accommodate this change (call to 5100Sstevel@tonic-gate * intr_redist_all_cpus()). As devices (not CPUs) attach/detach it is possible 5110Sstevel@tonic-gate * that a redistribution could improve the quality of an initialization. For 5120Sstevel@tonic-gate * example, if you are not using a NIC it may not be attached with s10 (devfs). 5130Sstevel@tonic-gate * If you then configure the NIC (ifconfig), this may cause the NIC to attach 5140Sstevel@tonic-gate * and plumb interrupts. The CPU assignment for the NIC's interrupts is 5150Sstevel@tonic-gate * occurring late, so optimal "isolation" relative to weight is not occurring. 5160Sstevel@tonic-gate * The same applies to detach, although in this case doing the redistribution 5170Sstevel@tonic-gate * might improve "spread" for medium weight devices since the "isolation" of 5180Sstevel@tonic-gate * a higher weight device may no longer be present. 5190Sstevel@tonic-gate * 5200Sstevel@tonic-gate * NB: We should provide a utility to trigger redistribution (ala "intradm -r"). 5210Sstevel@tonic-gate * 5220Sstevel@tonic-gate * NB: There is risk associated with automatically triggering execution of the 5230Sstevel@tonic-gate * redistribution code at arbitrary times. The risk comes from the fact that 5240Sstevel@tonic-gate * there is a lot of low-level hardware interaction associated with a 5250Sstevel@tonic-gate * redistribution. At some point we may want this code to perform automatic 5260Sstevel@tonic-gate * redistribution (redistribution thread; trigger timeout when add/remove 5270Sstevel@tonic-gate * weight delta is large enough, and call cv_signal from timeout - causing 5280Sstevel@tonic-gate * thead to call i_ddi_intr_redist_all_cpus()) but this is considered too 5290Sstevel@tonic-gate * risky at this time. 5300Sstevel@tonic-gate */ 5310Sstevel@tonic-gate void 5320Sstevel@tonic-gate i_ddi_intr_redist_all_cpus() 5330Sstevel@tonic-gate { 5340Sstevel@tonic-gate mutex_enter(&cpu_lock); 5350Sstevel@tonic-gate INTR_DEBUG((CE_CONT, "intr_dist: i_ddi_intr_redist_all_cpus\n")); 5360Sstevel@tonic-gate intr_redist_all_cpus(); 5370Sstevel@tonic-gate mutex_exit(&cpu_lock); 5380Sstevel@tonic-gate } 5390Sstevel@tonic-gate 5400Sstevel@tonic-gate /* 5410Sstevel@tonic-gate * Redistribute all interrupts 5420Sstevel@tonic-gate * 5430Sstevel@tonic-gate * This function redistributes all interrupting devices, running the 5440Sstevel@tonic-gate * parent callback functions for each node. 5450Sstevel@tonic-gate */ 5460Sstevel@tonic-gate void 5470Sstevel@tonic-gate intr_redist_all_cpus(void) 5480Sstevel@tonic-gate { 5490Sstevel@tonic-gate struct cpu *cp; 5500Sstevel@tonic-gate struct intr_dist *iptr; 5510Sstevel@tonic-gate int32_t weight, max_weight; 5520Sstevel@tonic-gate 5530Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cpu_lock)); 5540Sstevel@tonic-gate mutex_enter(&intr_dist_lock); 5550Sstevel@tonic-gate 5560Sstevel@tonic-gate /* 5570Sstevel@tonic-gate * zero cpu_intr_weight on all cpus - it is safe to traverse 5580Sstevel@tonic-gate * cpu_list since we hold cpu_lock. 5590Sstevel@tonic-gate */ 5600Sstevel@tonic-gate cp = cpu_list; 5610Sstevel@tonic-gate do { 5620Sstevel@tonic-gate cp->cpu_intr_weight = 0; 5630Sstevel@tonic-gate } while ((cp = cp->cpu_next) != cpu_list); 5640Sstevel@tonic-gate 5650Sstevel@tonic-gate /* 5660Sstevel@tonic-gate * Assume that this redistribution may encounter a device weight 5670Sstevel@tonic-gate * via driver.conf tuning of "ddi-intr-weight" that is at most 5680Sstevel@tonic-gate * intr_dist_weight_maxfactor times larger. 5690Sstevel@tonic-gate */ 5700Sstevel@tonic-gate max_weight = intr_dist_weight_max * intr_dist_weight_maxfactor; 5710Sstevel@tonic-gate if (max_weight > intr_dist_weight_maxmax) 5720Sstevel@tonic-gate max_weight = intr_dist_weight_maxmax; 5730Sstevel@tonic-gate intr_dist_weight_max = 1; 5740Sstevel@tonic-gate 5750Sstevel@tonic-gate INTR_DEBUG((CE_CONT, "intr_dist: " 5760Sstevel@tonic-gate "intr_redist_all_cpus: %d-0\n", max_weight)); 5770Sstevel@tonic-gate 5780Sstevel@tonic-gate /* 5790Sstevel@tonic-gate * Redistribute weighted, from heavy to light. The callback that 5800Sstevel@tonic-gate * specifies a weight equal to weight_max should redirect all 5810Sstevel@tonic-gate * interrupts of weight weight_max or greater [weight_max, inf.). 5820Sstevel@tonic-gate * Interrupts of lesser weight should be processed on the call with 5830Sstevel@tonic-gate * the matching weight. This allows all the heaver weight interrupts 5840Sstevel@tonic-gate * on all weighted busses (multiple pci busses) to be redirected prior 5850Sstevel@tonic-gate * to any lesser weight interrupts. 5860Sstevel@tonic-gate */ 5870Sstevel@tonic-gate for (weight = max_weight; weight >= 0; weight--) 5880Sstevel@tonic-gate for (iptr = intr_dist_whead; iptr != NULL; iptr = iptr->next) 5890Sstevel@tonic-gate ((void (*)(void *, int32_t, int32_t))iptr->func) 5900Sstevel@tonic-gate (iptr->arg, max_weight, weight); 5910Sstevel@tonic-gate 5920Sstevel@tonic-gate /* redistribute normal (non-weighted) interrupts */ 5930Sstevel@tonic-gate for (iptr = intr_dist_head; iptr != NULL; iptr = iptr->next) 5940Sstevel@tonic-gate ((void (*)(void *))iptr->func)(iptr->arg); 5950Sstevel@tonic-gate mutex_exit(&intr_dist_lock); 5960Sstevel@tonic-gate } 5970Sstevel@tonic-gate 5980Sstevel@tonic-gate void 5990Sstevel@tonic-gate intr_redist_all_cpus_shutdown(void) 6000Sstevel@tonic-gate { 6010Sstevel@tonic-gate intr_policy = INTR_CURRENT_CPU; 6020Sstevel@tonic-gate intr_redist_all_cpus(); 6030Sstevel@tonic-gate } 6040Sstevel@tonic-gate 6050Sstevel@tonic-gate /* 6060Sstevel@tonic-gate * Determine what CPU to target, based on interrupt policy. 6070Sstevel@tonic-gate * 6080Sstevel@tonic-gate * INTR_FLAT_DIST: hold a current CPU pointer in a static variable and 6090Sstevel@tonic-gate * advance through interrupt enabled cpus (round-robin). 6100Sstevel@tonic-gate * 6110Sstevel@tonic-gate * INTR_WEIGHTED_DIST: search for an enabled CPU with the lowest 6120Sstevel@tonic-gate * cpu_intr_weight, round robin when all equal. 6130Sstevel@tonic-gate * 6140Sstevel@tonic-gate * Weighted interrupt distribution provides two things: "spread" of weight 6150Sstevel@tonic-gate * (associated with algorithm itself) and "isolation" (associated with a 6160Sstevel@tonic-gate * particular device weight). A redistribution is what provides optimal 6170Sstevel@tonic-gate * "isolation" of heavy weight interrupts, optimal "spread" of weight 6180Sstevel@tonic-gate * (relative to what came before) is always occurring. 6190Sstevel@tonic-gate * 6200Sstevel@tonic-gate * An interrupt weight is a subjective number that represents the 6210Sstevel@tonic-gate * percentage of a CPU required to service a device's interrupts: the 6220Sstevel@tonic-gate * default weight is 0% (however the algorithm still maintains 6230Sstevel@tonic-gate * round-robin), a network interface controller (NIC) may have a large 6240Sstevel@tonic-gate * weight (35%). Interrupt weight only has meaning relative to the 6250Sstevel@tonic-gate * interrupt weight of other devices: a CPU can be weighted more than 6260Sstevel@tonic-gate * 100%, and a single device might consume more than 100% of a CPU. 6270Sstevel@tonic-gate * 6280Sstevel@tonic-gate * A coarse interrupt weight can be defined by the parent nexus driver 6290Sstevel@tonic-gate * based on bus specific information, like pci class codes. A nexus 6300Sstevel@tonic-gate * driver that supports device interrupt weighting for its children 6310Sstevel@tonic-gate * should call intr_dist_cpuid_add/rem_device_weight(), which adds 6320Sstevel@tonic-gate * and removes the weight of a device from the CPU that an interrupt 6330Sstevel@tonic-gate * is directed at. The quality of initialization improves when the 6340Sstevel@tonic-gate * device interrupt weights more accuracy reflect actual run-time weights, 6350Sstevel@tonic-gate * and as the assignments are ordered from is heavy to light. 6360Sstevel@tonic-gate * 6370Sstevel@tonic-gate * The implementation also supports interrupt weight being specified in 6380Sstevel@tonic-gate * driver.conf files via the property "ddi-intr-weight", which takes 6390Sstevel@tonic-gate * precedence over the nexus supplied weight. This support is added to 6400Sstevel@tonic-gate * permit possible tweaking in the product in response to customer 6410Sstevel@tonic-gate * problems. This is not a formal or committed interface. 6420Sstevel@tonic-gate * 6430Sstevel@tonic-gate * While a weighted approach chooses the CPU providing the best spread 6440Sstevel@tonic-gate * given past weights, less than optimal isolation can result in cases 6450Sstevel@tonic-gate * where heavy weight devices show up last. The nexus driver's interrupt 6460Sstevel@tonic-gate * redistribution logic should use intr_dist_add/rem_weighted so that 6470Sstevel@tonic-gate * interrupts can be redistributed heavy first for optimal isolation. 6480Sstevel@tonic-gate */ 6490Sstevel@tonic-gate uint32_t 6500Sstevel@tonic-gate intr_dist_cpuid(void) 6510Sstevel@tonic-gate { 6520Sstevel@tonic-gate static struct cpu *curr_cpu; 6530Sstevel@tonic-gate struct cpu *start_cpu; 6540Sstevel@tonic-gate struct cpu *new_cpu; 6550Sstevel@tonic-gate struct cpu *cp; 6560Sstevel@tonic-gate int cpuid = -1; 6570Sstevel@tonic-gate 6580Sstevel@tonic-gate /* Establish exclusion for curr_cpu and cpu_intr_weight manipulation */ 6590Sstevel@tonic-gate mutex_enter(&intr_dist_cpu_lock); 6600Sstevel@tonic-gate 6610Sstevel@tonic-gate switch (intr_policy) { 6620Sstevel@tonic-gate case INTR_CURRENT_CPU: 6630Sstevel@tonic-gate cpuid = CPU->cpu_id; 6640Sstevel@tonic-gate break; 6650Sstevel@tonic-gate 6660Sstevel@tonic-gate case INTR_BOOT_CPU: 6670Sstevel@tonic-gate panic("INTR_BOOT_CPU no longer supported."); 6680Sstevel@tonic-gate /*NOTREACHED*/ 6690Sstevel@tonic-gate 6700Sstevel@tonic-gate case INTR_FLAT_DIST: 6710Sstevel@tonic-gate case INTR_WEIGHTED_DIST: 6720Sstevel@tonic-gate default: 6730Sstevel@tonic-gate /* 6740Sstevel@tonic-gate * Ensure that curr_cpu is valid - cpu_next will be NULL if 6750Sstevel@tonic-gate * the cpu has been deleted (cpu structs are never freed). 6760Sstevel@tonic-gate */ 6770Sstevel@tonic-gate if (curr_cpu == NULL || curr_cpu->cpu_next == NULL) 6780Sstevel@tonic-gate curr_cpu = CPU; 6790Sstevel@tonic-gate 6800Sstevel@tonic-gate /* 6810Sstevel@tonic-gate * Advance to online CPU after curr_cpu (round-robin). For 6820Sstevel@tonic-gate * INTR_WEIGHTED_DIST we choose the cpu with the lightest 6830Sstevel@tonic-gate * weight. For a nexus that does not support weight the 6840Sstevel@tonic-gate * default weight of zero is used. We degrade to round-robin 6850Sstevel@tonic-gate * behavior among equal weightes. The default weight is zero 6860Sstevel@tonic-gate * and round-robin behavior continues. 6870Sstevel@tonic-gate * 6880Sstevel@tonic-gate * Disable preemption while traversing cpu_next_onln to 6890Sstevel@tonic-gate * ensure the list does not change. This works because 6900Sstevel@tonic-gate * modifiers of this list and other lists in a struct cpu 6910Sstevel@tonic-gate * call pause_cpus() before making changes. 6920Sstevel@tonic-gate */ 6930Sstevel@tonic-gate kpreempt_disable(); 6940Sstevel@tonic-gate cp = start_cpu = curr_cpu->cpu_next_onln; 6950Sstevel@tonic-gate new_cpu = NULL; 6960Sstevel@tonic-gate do { 6970Sstevel@tonic-gate /* Skip CPUs with interrupts disabled */ 6980Sstevel@tonic-gate if ((cp->cpu_flags & CPU_ENABLE) == 0) 6990Sstevel@tonic-gate continue; 7000Sstevel@tonic-gate 7010Sstevel@tonic-gate if (intr_policy == INTR_FLAT_DIST) { 7020Sstevel@tonic-gate /* select CPU */ 7030Sstevel@tonic-gate new_cpu = cp; 7040Sstevel@tonic-gate break; 7050Sstevel@tonic-gate } else if ((new_cpu == NULL) || 7060Sstevel@tonic-gate (cp->cpu_intr_weight < new_cpu->cpu_intr_weight)) { 7070Sstevel@tonic-gate /* Choose if lighter weight */ 7080Sstevel@tonic-gate new_cpu = cp; 7090Sstevel@tonic-gate } 7100Sstevel@tonic-gate } while ((cp = cp->cpu_next_onln) != start_cpu); 7110Sstevel@tonic-gate ASSERT(new_cpu); 7120Sstevel@tonic-gate cpuid = new_cpu->cpu_id; 7130Sstevel@tonic-gate 7140Sstevel@tonic-gate INTR_DEBUG((CE_CONT, "intr_dist: cpu %2d weight %3d: " 7150Sstevel@tonic-gate "targeted\n", cpuid, new_cpu->cpu_intr_weight)); 7160Sstevel@tonic-gate 7170Sstevel@tonic-gate /* update static pointer for next round-robin */ 7180Sstevel@tonic-gate curr_cpu = new_cpu; 7190Sstevel@tonic-gate kpreempt_enable(); 7200Sstevel@tonic-gate break; 7210Sstevel@tonic-gate } 7220Sstevel@tonic-gate mutex_exit(&intr_dist_cpu_lock); 7230Sstevel@tonic-gate return (cpuid); 7240Sstevel@tonic-gate } 7250Sstevel@tonic-gate 7260Sstevel@tonic-gate /* 7270Sstevel@tonic-gate * Add or remove the the weight of a device from a CPUs interrupt weight. 7280Sstevel@tonic-gate * 7290Sstevel@tonic-gate * We expect nexus drivers to call intr_dist_cpuid_add/rem_device_weight for 7300Sstevel@tonic-gate * their children to improve the overall quality of interrupt initialization. 7310Sstevel@tonic-gate * 7320Sstevel@tonic-gate * If a nexues shares the CPU returned by a single intr_dist_cpuid() call 7330Sstevel@tonic-gate * among multiple devices (sharing ino) then the nexus should call 7340Sstevel@tonic-gate * intr_dist_cpuid_add/rem_device_weight for each device separately. Devices 7350Sstevel@tonic-gate * that share must specify the same cpuid. 7360Sstevel@tonic-gate * 7370Sstevel@tonic-gate * If a nexus driver is unable to determine the cpu at remove_intr time 7380Sstevel@tonic-gate * for some of its interrupts, then it should not call add_device_weight - 7390Sstevel@tonic-gate * intr_dist_cpuid will still provide round-robin. 7400Sstevel@tonic-gate * 7410Sstevel@tonic-gate * An established device weight (from dev_info node) takes precedence over 7420Sstevel@tonic-gate * the weight passed in. If a device weight is not already established 7430Sstevel@tonic-gate * then the passed in nexus weight is established. 7440Sstevel@tonic-gate */ 7450Sstevel@tonic-gate void 7460Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(uint32_t cpuid, 7470Sstevel@tonic-gate dev_info_t *dip, int32_t nweight) 7480Sstevel@tonic-gate { 7490Sstevel@tonic-gate int32_t eweight; 7500Sstevel@tonic-gate 7510Sstevel@tonic-gate /* 7520Sstevel@tonic-gate * For non-weighted policy everything has weight of zero (and we get 7530Sstevel@tonic-gate * round-robin distribution from intr_dist_cpuid). 7540Sstevel@tonic-gate * NB: intr_policy is limited to this file. A weighted nexus driver is 7550Sstevel@tonic-gate * calls this rouitne even if intr_policy has been patched to 7560Sstevel@tonic-gate * INTR_FLAG_DIST. 7570Sstevel@tonic-gate */ 7580Sstevel@tonic-gate ASSERT(dip); 7590Sstevel@tonic-gate if (intr_policy != INTR_WEIGHTED_DIST) 7600Sstevel@tonic-gate return; 7610Sstevel@tonic-gate 7620Sstevel@tonic-gate eweight = i_ddi_get_intr_weight(dip); 7630Sstevel@tonic-gate INTR_DEBUG((CE_CONT, "intr_dist: cpu %2d weight %3d: +%2d/%2d for " 7640Sstevel@tonic-gate "%s#%d/%s#%d\n", cpuid, cpu[cpuid]->cpu_intr_weight, 7650Sstevel@tonic-gate nweight, eweight, ddi_driver_name(ddi_get_parent(dip)), 7660Sstevel@tonic-gate ddi_get_instance(ddi_get_parent(dip)), 7670Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 7680Sstevel@tonic-gate 7690Sstevel@tonic-gate /* if no establish weight, establish nexus weight */ 7700Sstevel@tonic-gate if (eweight < 0) { 7710Sstevel@tonic-gate if (nweight > 0) 7720Sstevel@tonic-gate (void) i_ddi_set_intr_weight(dip, nweight); 7730Sstevel@tonic-gate else 7740Sstevel@tonic-gate nweight = 0; 7750Sstevel@tonic-gate } else 7760Sstevel@tonic-gate nweight = eweight; /* use established weight */ 7770Sstevel@tonic-gate 7780Sstevel@tonic-gate /* Establish exclusion for cpu_intr_weight manipulation */ 7790Sstevel@tonic-gate mutex_enter(&intr_dist_cpu_lock); 7800Sstevel@tonic-gate cpu[cpuid]->cpu_intr_weight += nweight; 7810Sstevel@tonic-gate 7820Sstevel@tonic-gate /* update intr_dist_weight_max */ 7830Sstevel@tonic-gate if (nweight > intr_dist_weight_max) 7840Sstevel@tonic-gate intr_dist_weight_max = nweight; 7850Sstevel@tonic-gate mutex_exit(&intr_dist_cpu_lock); 7860Sstevel@tonic-gate } 7870Sstevel@tonic-gate 7880Sstevel@tonic-gate void 7890Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip) 7900Sstevel@tonic-gate { 7910Sstevel@tonic-gate struct cpu *cp; 7920Sstevel@tonic-gate int32_t weight; 7930Sstevel@tonic-gate 7940Sstevel@tonic-gate ASSERT(dip); 7950Sstevel@tonic-gate if (intr_policy != INTR_WEIGHTED_DIST) 7960Sstevel@tonic-gate return; 7970Sstevel@tonic-gate 7980Sstevel@tonic-gate /* remove weight of device from cpu */ 7990Sstevel@tonic-gate weight = i_ddi_get_intr_weight(dip); 8000Sstevel@tonic-gate if (weight < 0) 8010Sstevel@tonic-gate weight = 0; 8020Sstevel@tonic-gate INTR_DEBUG((CE_CONT, "intr_dist: cpu %2d weight %3d: -%2d for " 8030Sstevel@tonic-gate "%s#%d/%s#%d\n", cpuid, cpu[cpuid]->cpu_intr_weight, weight, 8040Sstevel@tonic-gate ddi_driver_name(ddi_get_parent(dip)), 8050Sstevel@tonic-gate ddi_get_instance(ddi_get_parent(dip)), 8060Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip))); 8070Sstevel@tonic-gate 8080Sstevel@tonic-gate /* Establish exclusion for cpu_intr_weight manipulation */ 8090Sstevel@tonic-gate mutex_enter(&intr_dist_cpu_lock); 8100Sstevel@tonic-gate cp = cpu[cpuid]; 8110Sstevel@tonic-gate cp->cpu_intr_weight -= weight; 8120Sstevel@tonic-gate if (cp->cpu_intr_weight < 0) 8130Sstevel@tonic-gate cp->cpu_intr_weight = 0; /* sanity */ 8140Sstevel@tonic-gate mutex_exit(&intr_dist_cpu_lock); 8150Sstevel@tonic-gate } 816