1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PX_VAR_H 28*0Sstevel@tonic-gate #define _SYS_PX_VAR_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * Register base definitions. 38*0Sstevel@tonic-gate * 39*0Sstevel@tonic-gate * The specific numeric values for CSR, XBUS, Configuration, 40*0Sstevel@tonic-gate * Interrupt blocks and other register bases. 41*0Sstevel@tonic-gate */ 42*0Sstevel@tonic-gate typedef enum { 43*0Sstevel@tonic-gate PX_REG_BANK0 = 0, 44*0Sstevel@tonic-gate PX_REG_BANK1, 45*0Sstevel@tonic-gate PX_REG_BANK2, 46*0Sstevel@tonic-gate PX_REG_BANK3, 47*0Sstevel@tonic-gate PX_REG_BANK4 48*0Sstevel@tonic-gate } px_reg_bank_t; 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate #ifdef sun4v 51*0Sstevel@tonic-gate #define PX_REG_CSR PX_REG_BANK1 52*0Sstevel@tonic-gate #define PX_REG_XBC PX_REG_BANK2 53*0Sstevel@tonic-gate #define PX_REG_CFG PX_REG_BANK3 54*0Sstevel@tonic-gate #define PX_REG_IC PX_REG_BANK4 55*0Sstevel@tonic-gate #else 56*0Sstevel@tonic-gate #define PX_REG_CSR PX_REG_BANK0 57*0Sstevel@tonic-gate #define PX_REG_XBC PX_REG_BANK1 58*0Sstevel@tonic-gate #define PX_REG_CFG PX_REG_BANK2 59*0Sstevel@tonic-gate #define PX_REG_IC PX_REG_BANK3 60*0Sstevel@tonic-gate #endif /* sun4v */ 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate enum px_nintr_index { 63*0Sstevel@tonic-gate PX_INTR_XBC = 0, /* all not shared */ 64*0Sstevel@tonic-gate PX_INTR_PEC = 1 /* all not shared */ 65*0Sstevel@tonic-gate }; 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate /* 68*0Sstevel@tonic-gate * offsets of PCI address spaces from base address: 69*0Sstevel@tonic-gate */ 70*0Sstevel@tonic-gate #define PX_CONFIG 0x001000000ull 71*0Sstevel@tonic-gate #define PX_A_IO 0x002000000ull 72*0Sstevel@tonic-gate #define PX_B_IO 0x002010000ull 73*0Sstevel@tonic-gate #define PX_A_MEMORY 0x100000000ull 74*0Sstevel@tonic-gate #define PX_B_MEMORY 0x180000000ull 75*0Sstevel@tonic-gate #define PX_IO_SIZE 0x000010000ull 76*0Sstevel@tonic-gate #define PX_MEM_SIZE 0x080000000ull 77*0Sstevel@tonic-gate /* 78*0Sstevel@tonic-gate * The following typedef is used to represent a 79*0Sstevel@tonic-gate * 1275 "bus-range" property of a PCI Bus node. 80*0Sstevel@tonic-gate */ 81*0Sstevel@tonic-gate typedef struct px_bus_range { 82*0Sstevel@tonic-gate uint32_t lo; 83*0Sstevel@tonic-gate uint32_t hi; 84*0Sstevel@tonic-gate } px_bus_range_t; 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate /* 87*0Sstevel@tonic-gate * The following typedef is used to represent a 88*0Sstevel@tonic-gate * 1275 "reg" property of a PCI nexus. 89*0Sstevel@tonic-gate */ 90*0Sstevel@tonic-gate typedef struct px_nexus_regspec { 91*0Sstevel@tonic-gate uint64_t phys_addr; 92*0Sstevel@tonic-gate uint64_t size; 93*0Sstevel@tonic-gate } px_nexus_regspec_t; 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate /* 96*0Sstevel@tonic-gate * The following typedef is used to represent an entry in the "ranges" 97*0Sstevel@tonic-gate * property of a device node. 98*0Sstevel@tonic-gate */ 99*0Sstevel@tonic-gate typedef struct px_ranges { 100*0Sstevel@tonic-gate uint32_t child_high; 101*0Sstevel@tonic-gate uint32_t child_mid; 102*0Sstevel@tonic-gate uint32_t child_low; 103*0Sstevel@tonic-gate uint32_t parent_high; 104*0Sstevel@tonic-gate uint32_t parent_low; 105*0Sstevel@tonic-gate uint32_t size_high; 106*0Sstevel@tonic-gate uint32_t size_low; 107*0Sstevel@tonic-gate } px_ranges_t; 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate typedef enum { PX_NEW, PX_ATTACHED, PX_DETACHED, PX_SUSPENDED } px_state_t; 110*0Sstevel@tonic-gate typedef enum { PX_OBJ_INTR_ADD, PX_OBJ_INTR_REMOVE } px_obj_op_t; 111*0Sstevel@tonic-gate typedef enum { PX_PEC_OBJ, PX_CB_OBJ } px_obj_t; 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate #define PX_ATTACH_RETCODE(obj, op, err) \ 114*0Sstevel@tonic-gate ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate #define PX_OTHER_SIDE(side) ((side) ^ 1) 117*0Sstevel@tonic-gate 118*0Sstevel@tonic-gate /* 119*0Sstevel@tonic-gate * px soft state structure: 120*0Sstevel@tonic-gate * 121*0Sstevel@tonic-gate * Each px node has a px soft state structure. 122*0Sstevel@tonic-gate */ 123*0Sstevel@tonic-gate struct px { 124*0Sstevel@tonic-gate /* 125*0Sstevel@tonic-gate * State flags and mutex: 126*0Sstevel@tonic-gate */ 127*0Sstevel@tonic-gate px_state_t px_state; 128*0Sstevel@tonic-gate uint_t px_soft_state; 129*0Sstevel@tonic-gate uint_t px_open_count; 130*0Sstevel@tonic-gate kmutex_t px_mutex; 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate /* 133*0Sstevel@tonic-gate * Links to other state structures: 134*0Sstevel@tonic-gate */ 135*0Sstevel@tonic-gate dev_info_t *px_dip; /* devinfo structure */ 136*0Sstevel@tonic-gate devhandle_t px_dev_hdl; /* device handle */ 137*0Sstevel@tonic-gate px_cb_t *px_cb_p; /* XBC block */ 138*0Sstevel@tonic-gate px_ib_t *px_ib_p; /* interrupt block */ 139*0Sstevel@tonic-gate px_pec_t *px_pec_p; /* PEC block */ 140*0Sstevel@tonic-gate px_mmu_t *px_mmu_p; /* IOMMU block */ 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate /* 143*0Sstevel@tonic-gate * px device node properties: 144*0Sstevel@tonic-gate */ 145*0Sstevel@tonic-gate px_bus_range_t px_bus_range; /* "bus-range" */ 146*0Sstevel@tonic-gate px_ranges_t *px_ranges_p; /* "ranges" data & length */ 147*0Sstevel@tonic-gate int px_ranges_length; 148*0Sstevel@tonic-gate devino_t *px_inos; /* inos from "interrupts" prop */ 149*0Sstevel@tonic-gate int px_inos_len; /* "interrupts" length */ 150*0Sstevel@tonic-gate int pci_numproxy; /* upa interrupt proxies */ 151*0Sstevel@tonic-gate int px_thermal_interrupt; /* node has thermal interrupt */ 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate /* 154*0Sstevel@tonic-gate * register mapping: 155*0Sstevel@tonic-gate * XXX - Remove the following fields and move them 156*0Sstevel@tonic-gate * to SUN4U library code, after complete virtualization 157*0Sstevel@tonic-gate * (after porting MSI and Error handling code). 158*0Sstevel@tonic-gate */ 159*0Sstevel@tonic-gate caddr_t px_address[4]; 160*0Sstevel@tonic-gate ddi_acc_handle_t px_ac[4]; 161*0Sstevel@tonic-gate 162*0Sstevel@tonic-gate /* Interrupt support */ 163*0Sstevel@tonic-gate int intr_map_size; 164*0Sstevel@tonic-gate struct intr_map *intr_map; 165*0Sstevel@tonic-gate struct intr_map_mask *intr_map_mask; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate /* Error handling */ 168*0Sstevel@tonic-gate px_fault_t px_fault; 169*0Sstevel@tonic-gate px_fault_t px_cb_fault; 170*0Sstevel@tonic-gate 171*0Sstevel@tonic-gate /* FMA */ 172*0Sstevel@tonic-gate int px_fm_cap; 173*0Sstevel@tonic-gate ddi_iblock_cookie_t px_fm_ibc; 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate /* Platform specific information */ 176*0Sstevel@tonic-gate void *px_plat_p; 177*0Sstevel@tonic-gate 178*0Sstevel@tonic-gate }; 179*0Sstevel@tonic-gate 180*0Sstevel@tonic-gate /* px soft state flag */ 181*0Sstevel@tonic-gate #define PX_SOFT_STATE_OPEN 0x01 182*0Sstevel@tonic-gate #define PX_SOFT_STATE_OPEN_EXCL 0x02 183*0Sstevel@tonic-gate #define PX_SOFT_STATE_CLOSED 0x04 184*0Sstevel@tonic-gate #define PX_BYPASS_DMA_ALLOWED 0x10 185*0Sstevel@tonic-gate 186*0Sstevel@tonic-gate #define DIP_TO_INST(dip) ddi_get_instance(dip) 187*0Sstevel@tonic-gate #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 188*0Sstevel@tonic-gate #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate #define DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 191*0Sstevel@tonic-gate px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 192*0Sstevel@tonic-gate 193*0Sstevel@tonic-gate extern void *px_state_p; 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate /* 196*0Sstevel@tonic-gate * function prototypes for bus ops routines: 197*0Sstevel@tonic-gate */ 198*0Sstevel@tonic-gate extern int 199*0Sstevel@tonic-gate px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 200*0Sstevel@tonic-gate off_t offset, off_t len, caddr_t *addrp); 201*0Sstevel@tonic-gate extern int 202*0Sstevel@tonic-gate px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 203*0Sstevel@tonic-gate ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 204*0Sstevel@tonic-gate extern int 205*0Sstevel@tonic-gate px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 206*0Sstevel@tonic-gate int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 207*0Sstevel@tonic-gate extern int 208*0Sstevel@tonic-gate px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 209*0Sstevel@tonic-gate ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 210*0Sstevel@tonic-gate ddi_dma_cookie_t *cookiep, uint_t *ccountp); 211*0Sstevel@tonic-gate extern int 212*0Sstevel@tonic-gate px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 213*0Sstevel@tonic-gate ddi_dma_handle_t handle); 214*0Sstevel@tonic-gate extern int 215*0Sstevel@tonic-gate px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 216*0Sstevel@tonic-gate enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 217*0Sstevel@tonic-gate uint_t cache_flags); 218*0Sstevel@tonic-gate extern int 219*0Sstevel@tonic-gate px_ctlops(dev_info_t *dip, dev_info_t *rdip, 220*0Sstevel@tonic-gate ddi_ctl_enum_t op, void *arg, void *result); 221*0Sstevel@tonic-gate extern int 222*0Sstevel@tonic-gate px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 223*0Sstevel@tonic-gate ddi_intr_handle_impl_t *handle, void *result); 224*0Sstevel@tonic-gate 225*0Sstevel@tonic-gate #ifdef __cplusplus 226*0Sstevel@tonic-gate } 227*0Sstevel@tonic-gate #endif 228*0Sstevel@tonic-gate 229*0Sstevel@tonic-gate #endif /* _SYS_PX_VAR_H */ 230