1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * PCI Express PEC implementation: 31*0Sstevel@tonic-gate * initialization 32*0Sstevel@tonic-gate * Bus error interrupt handler 33*0Sstevel@tonic-gate */ 34*0Sstevel@tonic-gate 35*0Sstevel@tonic-gate #include <sys/types.h> 36*0Sstevel@tonic-gate #include <sys/kmem.h> 37*0Sstevel@tonic-gate #include <sys/spl.h> 38*0Sstevel@tonic-gate #include <sys/sysmacros.h> 39*0Sstevel@tonic-gate #include <sys/sunddi.h> 40*0Sstevel@tonic-gate #include <sys/machsystm.h> /* ldphysio() */ 41*0Sstevel@tonic-gate #include <sys/async.h> 42*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 43*0Sstevel@tonic-gate #include <sys/ontrap.h> 44*0Sstevel@tonic-gate #include <sys/membar.h> 45*0Sstevel@tonic-gate #include "px_obj.h" 46*0Sstevel@tonic-gate 47*0Sstevel@tonic-gate /*LINTLIBRARY*/ 48*0Sstevel@tonic-gate 49*0Sstevel@tonic-gate extern uint_t px_ranges_phi_mask; 50*0Sstevel@tonic-gate 51*0Sstevel@tonic-gate static int px_pec_msg_add_intr(px_t *px_p); 52*0Sstevel@tonic-gate static void px_pec_msg_rem_intr(px_t *px_p); 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate static void 55*0Sstevel@tonic-gate px_ilu_attach(px_pec_t *pec_p) 56*0Sstevel@tonic-gate { 57*0Sstevel@tonic-gate /* 58*0Sstevel@tonic-gate * Register ilu error interrupt. This will 59*0Sstevel@tonic-gate * also program the correct values into the 60*0Sstevel@tonic-gate * log enable and interrupt enable registers. 61*0Sstevel@tonic-gate */ 62*0Sstevel@tonic-gate px_err_add_fh(&pec_p->pec_px_p->px_fault, PX_ERR_ILU, 63*0Sstevel@tonic-gate (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]); 64*0Sstevel@tonic-gate } 65*0Sstevel@tonic-gate 66*0Sstevel@tonic-gate int 67*0Sstevel@tonic-gate px_ilu_intr(dev_info_t *dip, px_fh_t *fh_p) 68*0Sstevel@tonic-gate { 69*0Sstevel@tonic-gate uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 70*0Sstevel@tonic-gate uint64_t stat = fh_p->fh_stat; 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate if (stat) 73*0Sstevel@tonic-gate LOG(DBG_ERR_INTR, dip, "[%x]=%16llx ilu stat\n", offset, stat); 74*0Sstevel@tonic-gate return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 75*0Sstevel@tonic-gate } 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate static void 78*0Sstevel@tonic-gate px_tlu_attach(px_pec_t *pec_p) 79*0Sstevel@tonic-gate { 80*0Sstevel@tonic-gate caddr_t csr_base = (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]; 81*0Sstevel@tonic-gate px_fault_t *px_fault_p = &pec_p->pec_px_p->px_fault; 82*0Sstevel@tonic-gate 83*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_TLU_UE, csr_base); 84*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_TLU_CE, csr_base); 85*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_TLU_OE, csr_base); 86*0Sstevel@tonic-gate } 87*0Sstevel@tonic-gate 88*0Sstevel@tonic-gate static void 89*0Sstevel@tonic-gate px_lpu_attach(px_pec_t *pec_p) 90*0Sstevel@tonic-gate { 91*0Sstevel@tonic-gate caddr_t csr_base = (caddr_t)pec_p->pec_px_p->px_address[PX_REG_CSR]; 92*0Sstevel@tonic-gate px_fault_t *px_fault_p = &pec_p->pec_px_p->px_fault; 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_LINK, csr_base); 95*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_PHY, csr_base); 96*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_REC_PHY, csr_base); 97*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_TRNS_PHY, csr_base); 98*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_LTSSM, csr_base); 99*0Sstevel@tonic-gate px_err_add_fh(px_fault_p, PX_ERR_LPU_GIGABLZ, csr_base); 100*0Sstevel@tonic-gate } 101*0Sstevel@tonic-gate 102*0Sstevel@tonic-gate int 103*0Sstevel@tonic-gate px_tlu_ue_intr(dev_info_t *dip, px_fh_t *fh_p) 104*0Sstevel@tonic-gate { 105*0Sstevel@tonic-gate uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 106*0Sstevel@tonic-gate uint64_t stat = fh_p->fh_stat; 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate if (stat) 109*0Sstevel@tonic-gate LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu ue stat\n", offset, 110*0Sstevel@tonic-gate stat); 111*0Sstevel@tonic-gate return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 112*0Sstevel@tonic-gate } 113*0Sstevel@tonic-gate 114*0Sstevel@tonic-gate int 115*0Sstevel@tonic-gate px_tlu_ce_intr(dev_info_t *dip, px_fh_t *fh_p) 116*0Sstevel@tonic-gate { 117*0Sstevel@tonic-gate uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 118*0Sstevel@tonic-gate uint64_t stat = fh_p->fh_stat; 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate if (stat) 121*0Sstevel@tonic-gate LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu ce stat\n", offset, 122*0Sstevel@tonic-gate stat); 123*0Sstevel@tonic-gate return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 124*0Sstevel@tonic-gate } 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate int 127*0Sstevel@tonic-gate px_tlu_oe_intr(dev_info_t *dip, px_fh_t *fh_p) 128*0Sstevel@tonic-gate { 129*0Sstevel@tonic-gate uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 130*0Sstevel@tonic-gate uint64_t stat = fh_p->fh_stat; 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate if (stat) 133*0Sstevel@tonic-gate LOG(DBG_ERR_INTR, dip, "[%x]=%16llx tlu other stat\n", offset, 134*0Sstevel@tonic-gate stat); 135*0Sstevel@tonic-gate return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 136*0Sstevel@tonic-gate } 137*0Sstevel@tonic-gate 138*0Sstevel@tonic-gate int 139*0Sstevel@tonic-gate px_lpu_intr(dev_info_t *dip, px_fh_t *fh_p) 140*0Sstevel@tonic-gate { 141*0Sstevel@tonic-gate uint32_t offset = px_fhd_tbl[fh_p->fh_err_id].fhd_st; 142*0Sstevel@tonic-gate uint64_t stat = fh_p->fh_stat; 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate if (stat) 145*0Sstevel@tonic-gate LOG(DBG_ERR_INTR, dip, "[%x]=%16llx lpu stat\n", offset, stat); 146*0Sstevel@tonic-gate return (stat ? DDI_INTR_CLAIMED : DDI_INTR_UNCLAIMED); 147*0Sstevel@tonic-gate } 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate int 150*0Sstevel@tonic-gate px_pec_attach(px_t *px_p) 151*0Sstevel@tonic-gate { 152*0Sstevel@tonic-gate px_pec_t *pec_p; 153*0Sstevel@tonic-gate int i, len; 154*0Sstevel@tonic-gate int nrange = px_p->px_ranges_length / sizeof (px_ranges_t); 155*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 156*0Sstevel@tonic-gate px_ranges_t *rangep = px_p->px_ranges_p; 157*0Sstevel@tonic-gate int ret; 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate /* 160*0Sstevel@tonic-gate * Allocate a state structure for the PEC and cross-link it 161*0Sstevel@tonic-gate * to its per px node state structure. 162*0Sstevel@tonic-gate */ 163*0Sstevel@tonic-gate pec_p = kmem_zalloc(sizeof (px_pec_t), KM_SLEEP); 164*0Sstevel@tonic-gate px_p->px_pec_p = pec_p; 165*0Sstevel@tonic-gate pec_p->pec_px_p = px_p; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate len = snprintf(pec_p->pec_nameinst_str, 168*0Sstevel@tonic-gate sizeof (pec_p->pec_nameinst_str), 169*0Sstevel@tonic-gate "%s%d", NAMEINST(dip)); 170*0Sstevel@tonic-gate pec_p->pec_nameaddr_str = pec_p->pec_nameinst_str + ++len; 171*0Sstevel@tonic-gate (void) snprintf(pec_p->pec_nameaddr_str, 172*0Sstevel@tonic-gate sizeof (pec_p->pec_nameinst_str) - len, 173*0Sstevel@tonic-gate "%s@%s", NAMEADDR(dip)); 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate /* 176*0Sstevel@tonic-gate * Add interrupt handlers to process correctable/fatal/non fatal 177*0Sstevel@tonic-gate * PCIE messages. 178*0Sstevel@tonic-gate */ 179*0Sstevel@tonic-gate if ((ret = px_pec_msg_add_intr(px_p)) != DDI_SUCCESS) { 180*0Sstevel@tonic-gate px_pec_msg_rem_intr(px_p); 181*0Sstevel@tonic-gate return (ret); 182*0Sstevel@tonic-gate } 183*0Sstevel@tonic-gate 184*0Sstevel@tonic-gate /* 185*0Sstevel@tonic-gate * Get this pec's mem32 and mem64 segments to determine whether 186*0Sstevel@tonic-gate * a dma object originates from ths pec. i.e. dev to dev dma 187*0Sstevel@tonic-gate */ 188*0Sstevel@tonic-gate for (i = 0; i < nrange; i++, rangep++) { 189*0Sstevel@tonic-gate uint64_t rng_addr, rng_size, *pfnbp, *pfnlp; 190*0Sstevel@tonic-gate uint32_t rng_type = rangep->child_high & PCI_ADDR_MASK; 191*0Sstevel@tonic-gate 192*0Sstevel@tonic-gate switch (rng_type) { 193*0Sstevel@tonic-gate case PCI_ADDR_MEM32: 194*0Sstevel@tonic-gate pfnbp = &pec_p->pec_base32_pfn; 195*0Sstevel@tonic-gate pfnlp = &pec_p->pec_last32_pfn; 196*0Sstevel@tonic-gate break; 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate case PCI_ADDR_MEM64: 199*0Sstevel@tonic-gate pfnbp = &pec_p->pec_base64_pfn; 200*0Sstevel@tonic-gate pfnlp = &pec_p->pec_last64_pfn; 201*0Sstevel@tonic-gate break; 202*0Sstevel@tonic-gate 203*0Sstevel@tonic-gate case PCI_ADDR_CONFIG: 204*0Sstevel@tonic-gate case PCI_ADDR_IO: 205*0Sstevel@tonic-gate default: 206*0Sstevel@tonic-gate continue; 207*0Sstevel@tonic-gate } 208*0Sstevel@tonic-gate rng_addr = (uint64_t)(rangep->parent_high & 209*0Sstevel@tonic-gate px_ranges_phi_mask) << 32; 210*0Sstevel@tonic-gate rng_addr |= (uint64_t)rangep->parent_low; 211*0Sstevel@tonic-gate rng_size = (uint64_t)rangep->size_high << 32; 212*0Sstevel@tonic-gate rng_size |= (uint64_t)rangep->size_low; 213*0Sstevel@tonic-gate 214*0Sstevel@tonic-gate *pfnbp = mmu_btop(rng_addr); 215*0Sstevel@tonic-gate *pfnlp = mmu_btop(rng_addr + rng_size); 216*0Sstevel@tonic-gate } 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate /* 219*0Sstevel@tonic-gate * configure ILU. 220*0Sstevel@tonic-gate */ 221*0Sstevel@tonic-gate px_ilu_attach(pec_p); 222*0Sstevel@tonic-gate 223*0Sstevel@tonic-gate /* 224*0Sstevel@tonic-gate * configure TLU. 225*0Sstevel@tonic-gate */ 226*0Sstevel@tonic-gate px_tlu_attach(pec_p); 227*0Sstevel@tonic-gate 228*0Sstevel@tonic-gate /* 229*0Sstevel@tonic-gate * configure LPU 230*0Sstevel@tonic-gate */ 231*0Sstevel@tonic-gate px_lpu_attach(pec_p); 232*0Sstevel@tonic-gate 233*0Sstevel@tonic-gate /* 234*0Sstevel@tonic-gate * Register a function to disable pec error interrupts during a panic. 235*0Sstevel@tonic-gate * do in px_attach. bus_func_register(BF_TYPE_ERRDIS, 236*0Sstevel@tonic-gate * (busfunc_t)pec_disable_pci_errors, pec_p); 237*0Sstevel@tonic-gate */ 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate mutex_init(&pec_p->pec_pokefault_mutex, NULL, MUTEX_DRIVER, 0); 240*0Sstevel@tonic-gate 241*0Sstevel@tonic-gate return (DDI_SUCCESS); 242*0Sstevel@tonic-gate } 243*0Sstevel@tonic-gate 244*0Sstevel@tonic-gate uint_t 245*0Sstevel@tonic-gate pec_disable_px_errors(px_pec_t *pec_p) 246*0Sstevel@tonic-gate { 247*0Sstevel@tonic-gate px_t *px_p = pec_p->pec_px_p; 248*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 249*0Sstevel@tonic-gate 250*0Sstevel@tonic-gate /* 251*0Sstevel@tonic-gate * Disable error interrupts via the interrupt mapping register. 252*0Sstevel@tonic-gate */ 253*0Sstevel@tonic-gate px_ib_intr_disable(ib_p, px_p->px_inos[PX_INTR_PEC], IB_INTR_NOWAIT); 254*0Sstevel@tonic-gate return (BF_NONE); 255*0Sstevel@tonic-gate } 256*0Sstevel@tonic-gate 257*0Sstevel@tonic-gate void 258*0Sstevel@tonic-gate px_pec_detach(px_t *px_p) 259*0Sstevel@tonic-gate { 260*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 261*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 262*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 263*0Sstevel@tonic-gate devino_t ino = px_p->px_inos[PX_INTR_PEC]; 264*0Sstevel@tonic-gate 265*0Sstevel@tonic-gate /* 266*0Sstevel@tonic-gate * Free the pokefault mutex. 267*0Sstevel@tonic-gate */ 268*0Sstevel@tonic-gate DBG(DBG_DETACH, dip, "px_pec_detach:\n"); 269*0Sstevel@tonic-gate mutex_destroy(&pec_p->pec_pokefault_mutex); 270*0Sstevel@tonic-gate 271*0Sstevel@tonic-gate /* 272*0Sstevel@tonic-gate * Remove the pci error interrupt handler. 273*0Sstevel@tonic-gate */ 274*0Sstevel@tonic-gate px_ib_intr_disable(ib_p, ino, IB_INTR_WAIT); 275*0Sstevel@tonic-gate ddi_remove_intr(dip, 0, NULL); 276*0Sstevel@tonic-gate 277*0Sstevel@tonic-gate /* 278*0Sstevel@tonic-gate * Remove the error disable function. 279*0Sstevel@tonic-gate */ 280*0Sstevel@tonic-gate bus_func_unregister(BF_TYPE_ERRDIS, 281*0Sstevel@tonic-gate (busfunc_t)pec_disable_px_errors, pec_p); 282*0Sstevel@tonic-gate 283*0Sstevel@tonic-gate /* 284*0Sstevel@tonic-gate * Remove interrupt handlers to process correctable/fatal/non fatal 285*0Sstevel@tonic-gate * PCIE messages. 286*0Sstevel@tonic-gate */ 287*0Sstevel@tonic-gate px_pec_msg_rem_intr(px_p); 288*0Sstevel@tonic-gate 289*0Sstevel@tonic-gate /* 290*0Sstevel@tonic-gate * Free the pec state structure. 291*0Sstevel@tonic-gate */ 292*0Sstevel@tonic-gate kmem_free(pec_p, sizeof (px_pec_t)); 293*0Sstevel@tonic-gate px_p->px_pec_p = NULL; 294*0Sstevel@tonic-gate } 295*0Sstevel@tonic-gate 296*0Sstevel@tonic-gate /* 297*0Sstevel@tonic-gate * pec_msg_add_intr: 298*0Sstevel@tonic-gate * 299*0Sstevel@tonic-gate * Add interrupt handlers to process correctable/fatal/non fatal 300*0Sstevel@tonic-gate * PCIE messages. 301*0Sstevel@tonic-gate */ 302*0Sstevel@tonic-gate static int 303*0Sstevel@tonic-gate px_pec_msg_add_intr(px_t *px_p) 304*0Sstevel@tonic-gate { 305*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 306*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 307*0Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 308*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 309*0Sstevel@tonic-gate 310*0Sstevel@tonic-gate DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_add_intr\n"); 311*0Sstevel@tonic-gate 312*0Sstevel@tonic-gate /* Initilize handle */ 313*0Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 314*0Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 315*0Sstevel@tonic-gate hdl.ih_dip = dip; 316*0Sstevel@tonic-gate hdl.ih_inum = 0; 317*0Sstevel@tonic-gate hdl.ih_pri = PX_ERR_PIL; 318*0Sstevel@tonic-gate 319*0Sstevel@tonic-gate /* Add correctable error message handler */ 320*0Sstevel@tonic-gate hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_corr_msg_intr; 321*0Sstevel@tonic-gate hdl.ih_cb_arg1 = px_p; 322*0Sstevel@tonic-gate hdl.ih_cb_arg2 = NULL; 323*0Sstevel@tonic-gate 324*0Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, dip, &hdl, 325*0Sstevel@tonic-gate MSG_REC, (msgcode_t)PCIE_CORR_MSG, 326*0Sstevel@tonic-gate &pec_p->pec_corr_msg_msiq_id)) != DDI_SUCCESS) { 327*0Sstevel@tonic-gate DBG(DBG_MSG, px_p->px_dip, 328*0Sstevel@tonic-gate "PCIE_CORR_MSG registration failed\n"); 329*0Sstevel@tonic-gate return (DDI_FAILURE); 330*0Sstevel@tonic-gate } 331*0Sstevel@tonic-gate 332*0Sstevel@tonic-gate px_lib_msg_setmsiq(dip, PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 333*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_VALID); 334*0Sstevel@tonic-gate 335*0Sstevel@tonic-gate /* Add non-fatal error message handler */ 336*0Sstevel@tonic-gate hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_non_fatal_msg_intr; 337*0Sstevel@tonic-gate hdl.ih_cb_arg1 = px_p; 338*0Sstevel@tonic-gate hdl.ih_cb_arg2 = NULL; 339*0Sstevel@tonic-gate 340*0Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, dip, &hdl, 341*0Sstevel@tonic-gate MSG_REC, (msgcode_t)PCIE_NONFATAL_MSG, 342*0Sstevel@tonic-gate &pec_p->pec_non_fatal_msg_msiq_id)) != DDI_SUCCESS) { 343*0Sstevel@tonic-gate DBG(DBG_MSG, px_p->px_dip, 344*0Sstevel@tonic-gate "PCIE_NONFATAL_MSG registration failed\n"); 345*0Sstevel@tonic-gate return (DDI_FAILURE); 346*0Sstevel@tonic-gate } 347*0Sstevel@tonic-gate 348*0Sstevel@tonic-gate px_lib_msg_setmsiq(dip, PCIE_NONFATAL_MSG, 349*0Sstevel@tonic-gate pec_p->pec_non_fatal_msg_msiq_id); 350*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, PCIE_MSG_VALID); 351*0Sstevel@tonic-gate 352*0Sstevel@tonic-gate /* Add fatal error message handler */ 353*0Sstevel@tonic-gate hdl.ih_cb_func = (ddi_intr_handler_t *)px_pec_fatal_msg_intr; 354*0Sstevel@tonic-gate hdl.ih_cb_arg1 = px_p; 355*0Sstevel@tonic-gate hdl.ih_cb_arg2 = NULL; 356*0Sstevel@tonic-gate 357*0Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, dip, &hdl, 358*0Sstevel@tonic-gate MSG_REC, (msgcode_t)PCIE_FATAL_MSG, 359*0Sstevel@tonic-gate &pec_p->pec_fatal_msg_msiq_id)) != DDI_SUCCESS) { 360*0Sstevel@tonic-gate DBG(DBG_MSG, px_p->px_dip, 361*0Sstevel@tonic-gate "PCIE_FATAL_MSG registration failed\n"); 362*0Sstevel@tonic-gate return (DDI_FAILURE); 363*0Sstevel@tonic-gate } 364*0Sstevel@tonic-gate 365*0Sstevel@tonic-gate px_lib_msg_setmsiq(dip, PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 366*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_VALID); 367*0Sstevel@tonic-gate 368*0Sstevel@tonic-gate return (ret); 369*0Sstevel@tonic-gate } 370*0Sstevel@tonic-gate 371*0Sstevel@tonic-gate /* 372*0Sstevel@tonic-gate * px_pec_msg_rem_intr: 373*0Sstevel@tonic-gate * 374*0Sstevel@tonic-gate * Remove interrupt handlers to process correctable/fatal/non fatal 375*0Sstevel@tonic-gate * PCIE messages. For now, all these PCIe messages are mapped to 376*0Sstevel@tonic-gate * same MSIQ. 377*0Sstevel@tonic-gate */ 378*0Sstevel@tonic-gate static void 379*0Sstevel@tonic-gate px_pec_msg_rem_intr(px_t *px_p) 380*0Sstevel@tonic-gate { 381*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 382*0Sstevel@tonic-gate px_pec_t *pec_p = px_p->px_pec_p; 383*0Sstevel@tonic-gate ddi_intr_handle_impl_t hdl; 384*0Sstevel@tonic-gate 385*0Sstevel@tonic-gate DBG(DBG_MSG, px_p->px_dip, "px_pec_msg_rem_intr: dip 0x%p\n", dip); 386*0Sstevel@tonic-gate 387*0Sstevel@tonic-gate /* Initilize handle */ 388*0Sstevel@tonic-gate hdl.ih_ver = DDI_INTR_VERSION; 389*0Sstevel@tonic-gate hdl.ih_state = DDI_IHDL_STATE_ALLOC; 390*0Sstevel@tonic-gate hdl.ih_dip = dip; 391*0Sstevel@tonic-gate hdl.ih_inum = 0; 392*0Sstevel@tonic-gate 393*0Sstevel@tonic-gate if (pec_p->pec_corr_msg_msiq_id >= 0) { 394*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_CORR_MSG, PCIE_MSG_INVALID); 395*0Sstevel@tonic-gate 396*0Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 397*0Sstevel@tonic-gate PCIE_CORR_MSG, pec_p->pec_corr_msg_msiq_id); 398*0Sstevel@tonic-gate pec_p->pec_corr_msg_msiq_id = -1; 399*0Sstevel@tonic-gate } 400*0Sstevel@tonic-gate 401*0Sstevel@tonic-gate if (pec_p->pec_non_fatal_msg_msiq_id >= 0) { 402*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_NONFATAL_MSG, 403*0Sstevel@tonic-gate PCIE_MSG_INVALID); 404*0Sstevel@tonic-gate 405*0Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 406*0Sstevel@tonic-gate PCIE_NONFATAL_MSG, pec_p->pec_non_fatal_msg_msiq_id); 407*0Sstevel@tonic-gate 408*0Sstevel@tonic-gate pec_p->pec_non_fatal_msg_msiq_id = -1; 409*0Sstevel@tonic-gate } 410*0Sstevel@tonic-gate 411*0Sstevel@tonic-gate if (pec_p->pec_fatal_msg_msiq_id >= 0) { 412*0Sstevel@tonic-gate px_lib_msg_setvalid(dip, PCIE_FATAL_MSG, PCIE_MSG_INVALID); 413*0Sstevel@tonic-gate 414*0Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, dip, &hdl, MSG_REC, 415*0Sstevel@tonic-gate PCIE_FATAL_MSG, pec_p->pec_fatal_msg_msiq_id); 416*0Sstevel@tonic-gate 417*0Sstevel@tonic-gate pec_p->pec_fatal_msg_msiq_id = -1; 418*0Sstevel@tonic-gate } 419*0Sstevel@tonic-gate } 420*0Sstevel@tonic-gate 421*0Sstevel@tonic-gate /*ARGSUSED*/ 422*0Sstevel@tonic-gate uint_t 423*0Sstevel@tonic-gate px_pec_corr_msg_intr(caddr_t arg) 424*0Sstevel@tonic-gate { 425*0Sstevel@tonic-gate px_t *px_p = (px_t *)arg; 426*0Sstevel@tonic-gate uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 427*0Sstevel@tonic-gate 428*0Sstevel@tonic-gate DBG(DBG_MSG_INTR, px_p->px_dip, 429*0Sstevel@tonic-gate "px_pec_corr_msg_intr: requester id 0x%x\n", rid); 430*0Sstevel@tonic-gate 431*0Sstevel@tonic-gate px_p->px_pec_p->pec_msiq_rec_p = NULL; 432*0Sstevel@tonic-gate 433*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 434*0Sstevel@tonic-gate } 435*0Sstevel@tonic-gate 436*0Sstevel@tonic-gate /*ARGSUSED*/ 437*0Sstevel@tonic-gate uint_t 438*0Sstevel@tonic-gate px_pec_non_fatal_msg_intr(caddr_t arg) 439*0Sstevel@tonic-gate { 440*0Sstevel@tonic-gate px_t *px_p = (px_t *)arg; 441*0Sstevel@tonic-gate uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 442*0Sstevel@tonic-gate 443*0Sstevel@tonic-gate DBG(DBG_MSG_INTR, px_p->px_dip, 444*0Sstevel@tonic-gate "px_pec_non_fatal_msg_intr: requester id 0x%x\n", rid); 445*0Sstevel@tonic-gate 446*0Sstevel@tonic-gate px_p->px_pec_p->pec_msiq_rec_p = NULL; 447*0Sstevel@tonic-gate 448*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 449*0Sstevel@tonic-gate } 450*0Sstevel@tonic-gate 451*0Sstevel@tonic-gate /*ARGSUSED*/ 452*0Sstevel@tonic-gate uint_t 453*0Sstevel@tonic-gate px_pec_fatal_msg_intr(caddr_t arg) 454*0Sstevel@tonic-gate { 455*0Sstevel@tonic-gate px_t *px_p = (px_t *)arg; 456*0Sstevel@tonic-gate uint64_t rid = px_p->px_pec_p->pec_msiq_rec_p->msiq_rec_rid; 457*0Sstevel@tonic-gate 458*0Sstevel@tonic-gate DBG(DBG_MSG_INTR, px_p->px_dip, 459*0Sstevel@tonic-gate "px_pec_fatal_msg_intr: requester id 0x%x\n", rid); 460*0Sstevel@tonic-gate 461*0Sstevel@tonic-gate px_p->px_pec_p->pec_msiq_rec_p = NULL; 462*0Sstevel@tonic-gate 463*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 464*0Sstevel@tonic-gate } 465