1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PX_IOAPI_H 28*0Sstevel@tonic-gate #define _SYS_PX_IOAPI_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #ifndef _ASM 37*0Sstevel@tonic-gate 38*0Sstevel@tonic-gate /* 39*0Sstevel@tonic-gate * SUN4V IO Data Definitions 40*0Sstevel@tonic-gate * 41*0Sstevel@tonic-gate * cpuid - A unique opaque value which represents a target cpu. 42*0Sstevel@tonic-gate * 43*0Sstevel@tonic-gate * devhandle - Device handle. The device handle uniquely 44*0Sstevel@tonic-gate * identifies a SUN4V device. It consists of the 45*0Sstevel@tonic-gate * the lower 28-bits of the hi-cell of the first 46*0Sstevel@tonic-gate * entry of the SUN4V device's "reg" property as defined 47*0Sstevel@tonic-gate * by the SUN4V Bus Binding to Open Firmware. 48*0Sstevel@tonic-gate * 49*0Sstevel@tonic-gate * devino - Device Interrupt Number. An unsigned integer representing 50*0Sstevel@tonic-gate * an interrupt within a specific device. 51*0Sstevel@tonic-gate * 52*0Sstevel@tonic-gate * sysino - System Interrupt Number. A 64-bit unsigned integer 53*0Sstevel@tonic-gate * representing a unique interrupt within a "system". 54*0Sstevel@tonic-gate * 55*0Sstevel@tonic-gate * intr_state - A flag representing the interrupt state for a 56*0Sstevel@tonic-gate * a given sysino. The state values are defined as: 57*0Sstevel@tonic-gate * 58*0Sstevel@tonic-gate * INTR_IDLE 0 59*0Sstevel@tonic-gate * INTR_RECEIVED 1 60*0Sstevel@tonic-gate * INTR_DELIVERED 2 61*0Sstevel@tonic-gate * 62*0Sstevel@tonic-gate * intr_valid_state - A flag representing the 'valid' state for 63*0Sstevel@tonic-gate * a given sysino. The state values are defined as: 64*0Sstevel@tonic-gate * 65*0Sstevel@tonic-gate * INTR_NOTVALID 0 sysino not enabled 66*0Sstevel@tonic-gate * INTR_VALID 1 sysino enabled 67*0Sstevel@tonic-gate */ 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate typedef uint64_t devhandle_t; 70*0Sstevel@tonic-gate 71*0Sstevel@tonic-gate typedef uint32_t cpuid_t; 72*0Sstevel@tonic-gate typedef uint32_t devino_t; 73*0Sstevel@tonic-gate typedef uint64_t sysino_t; 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate typedef enum intr_state { 76*0Sstevel@tonic-gate INTR_IDLE_STATE = (uint32_t)0, 77*0Sstevel@tonic-gate INTR_RECEIVED_STATE = (uint32_t)1, 78*0Sstevel@tonic-gate INTR_DELIVERED_STATE = (uint32_t)2 79*0Sstevel@tonic-gate } intr_state_t; 80*0Sstevel@tonic-gate 81*0Sstevel@tonic-gate typedef enum intr_valid_state { 82*0Sstevel@tonic-gate INTR_NOTVALID = (uint32_t)0, 83*0Sstevel@tonic-gate INTR_VALID = (uint32_t)1 84*0Sstevel@tonic-gate } intr_valid_state_t; 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate /* 87*0Sstevel@tonic-gate * PCI IO Data Definitions 88*0Sstevel@tonic-gate * 89*0Sstevel@tonic-gate * tsbnum - TSB Number. Identifies which io-tsb is used. 90*0Sstevel@tonic-gate * For this version of the spec, tsbnum must be zero. 91*0Sstevel@tonic-gate * 92*0Sstevel@tonic-gate * tsbindex - TSB Index. Identifies which entry in the tsb is 93*0Sstevel@tonic-gate * is used. The first entry is zero. 94*0Sstevel@tonic-gate * 95*0Sstevel@tonic-gate * tsbid - A 64-bit aligned data structure which contains 96*0Sstevel@tonic-gate * a tsbnum and a tsbindex. 97*0Sstevel@tonic-gate * bits 63:32 contain the tsbnum. 98*0Sstevel@tonic-gate * bits 31:00 contain the tsbindex. 99*0Sstevel@tonic-gate * 100*0Sstevel@tonic-gate * io_attributes - IO Attributes for iommu mappings. 101*0Sstevel@tonic-gate * Attributes for iommu mappings. One or more of the 102*0Sstevel@tonic-gate * following attribute bits stored in a 64-bit unsigned int. 103*0Sstevel@tonic-gate * 104*0Sstevel@tonic-gate * PCI_MAP_ATTR_READ 0x01 - xfr direction is from memory 105*0Sstevel@tonic-gate * PCI_MAP_ATTR_WRITE 0x02 - xfr direction is to memory 106*0Sstevel@tonic-gate * 107*0Sstevel@tonic-gate * Bits 63:2 are unused and must be set to zero for this 108*0Sstevel@tonic-gate * version of the specification. 109*0Sstevel@tonic-gate * 110*0Sstevel@tonic-gate * Note: For compatibility with future versions of this 111*0Sstevel@tonic-gate * specification, the caller must set 63:2 to zero. 112*0Sstevel@tonic-gate * The implementation shall ignore bits 63:2 113*0Sstevel@tonic-gate * 114*0Sstevel@tonic-gate * r_addr - 64-bit Real Address. 115*0Sstevel@tonic-gate * 116*0Sstevel@tonic-gate * io_addr - 64-bit IO Address. 117*0Sstevel@tonic-gate * 118*0Sstevel@tonic-gate * pci_device - PCI device address. A PCI device address 119*0Sstevel@tonic-gate * identifies a specific device on a specific PCI 120*0Sstevel@tonic-gate * bus segment. A PCI device address is a 32-bit unsigned 121*0Sstevel@tonic-gate * integer with the following format: 122*0Sstevel@tonic-gate * 123*0Sstevel@tonic-gate * 00000000.bbbbbbbb.dddddfff.00000000 124*0Sstevel@tonic-gate * 125*0Sstevel@tonic-gate * Where: 126*0Sstevel@tonic-gate * 127*0Sstevel@tonic-gate * bbbbbbbb is the 8-bit pci bus number 128*0Sstevel@tonic-gate * ddddd is the 5-bit pci device number 129*0Sstevel@tonic-gate * fff is the 3-bit pci function number 130*0Sstevel@tonic-gate * 131*0Sstevel@tonic-gate * 00000000 is the 8-bit literal zero. 132*0Sstevel@tonic-gate * 133*0Sstevel@tonic-gate * pci_config_offset - PCI Configuration Space offset. 134*0Sstevel@tonic-gate * 135*0Sstevel@tonic-gate * For conventional PCI, an unsigned integer in the range 136*0Sstevel@tonic-gate * 0 .. 255 representing the offset of the field in pci config 137*0Sstevel@tonic-gate * space. 138*0Sstevel@tonic-gate * 139*0Sstevel@tonic-gate * For PCI implementations with extended configuration space, 140*0Sstevel@tonic-gate * an unsigned integer in the range 0 .. 4095, representing 141*0Sstevel@tonic-gate * the offset of the field in configuration space. Conventional 142*0Sstevel@tonic-gate * PCI config space is offset 0 .. 255. Extended config space 143*0Sstevel@tonic-gate * is offset 256 .. 4095 144*0Sstevel@tonic-gate * 145*0Sstevel@tonic-gate * Note: For pci config space accesses, the offset must be 'size' 146*0Sstevel@tonic-gate * aligned. 147*0Sstevel@tonic-gate * 148*0Sstevel@tonic-gate * error_flag - Error flag 149*0Sstevel@tonic-gate * 150*0Sstevel@tonic-gate * A return value specifies if the action succeeded 151*0Sstevel@tonic-gate * or failed, where: 152*0Sstevel@tonic-gate * 153*0Sstevel@tonic-gate * 0 - No error occurred while performing the service. 154*0Sstevel@tonic-gate * non-zero - Error occurred while performing the service. 155*0Sstevel@tonic-gate * 156*0Sstevel@tonic-gate * io_sync_direction - "direction" definition for pci_dma_sync 157*0Sstevel@tonic-gate * 158*0Sstevel@tonic-gate * A value specifying the direction for a memory/io sync 159*0Sstevel@tonic-gate * operation, The direction value is a flag, one or both 160*0Sstevel@tonic-gate * directions may be specified by the caller. 161*0Sstevel@tonic-gate * 162*0Sstevel@tonic-gate * 0x01 - For device (device read from memory) 163*0Sstevel@tonic-gate * 0x02 - For cpu (device write to memory) 164*0Sstevel@tonic-gate * 165*0Sstevel@tonic-gate * io_page_list - A list of io_page_addresses. An io_page_address 166*0Sstevel@tonic-gate * is an r_addr. 167*0Sstevel@tonic-gate * 168*0Sstevel@tonic-gate * io_page_list_p - A pointer to an io_page_list. 169*0Sstevel@tonic-gate */ 170*0Sstevel@tonic-gate typedef uint32_t tsbnum_t; 171*0Sstevel@tonic-gate typedef uint32_t tsbindex_t; 172*0Sstevel@tonic-gate typedef uint64_t tsbid_t; 173*0Sstevel@tonic-gate typedef uint64_t r_addr_t; 174*0Sstevel@tonic-gate typedef uint64_t io_addr_t; 175*0Sstevel@tonic-gate typedef uint64_t io_page_list_t; 176*0Sstevel@tonic-gate typedef uint32_t pages_t; 177*0Sstevel@tonic-gate typedef uint32_t error_flag_t; 178*0Sstevel@tonic-gate 179*0Sstevel@tonic-gate typedef uint32_t pci_config_offset_t; 180*0Sstevel@tonic-gate typedef uint64_t pci_device_t; 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate #define PCI_TSB_INDEX 0 183*0Sstevel@tonic-gate #define PCI_TSB_INDEX_MASK 0xFFFFFFFF 184*0Sstevel@tonic-gate #define PCI_TSB_NUM 32 185*0Sstevel@tonic-gate #define PCI_TSB_NUM_MASK 0xFFFFFFFF 186*0Sstevel@tonic-gate 187*0Sstevel@tonic-gate #define PCI_TSBID(tsbnum, tsbindex) \ 188*0Sstevel@tonic-gate ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 189*0Sstevel@tonic-gate (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 190*0Sstevel@tonic-gate 191*0Sstevel@tonic-gate #define PCI_TSBID_TO_TSBNUM(tsbid) \ 192*0Sstevel@tonic-gate ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 193*0Sstevel@tonic-gate 194*0Sstevel@tonic-gate #define PCI_TSBID_TO_TSBINDEX(tsbid) \ 195*0Sstevel@tonic-gate ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate typedef enum io_attributes { 198*0Sstevel@tonic-gate PCI_MAP_ATTR_READ = (uint32_t)0x01, 199*0Sstevel@tonic-gate PCI_MAP_ATTR_WRITE = (uint32_t)0x02 200*0Sstevel@tonic-gate } io_attributes_t; 201*0Sstevel@tonic-gate 202*0Sstevel@tonic-gate typedef enum io_sync_direction { 203*0Sstevel@tonic-gate IO_SYNC_DEVICE = (uint32_t)0x01, 204*0Sstevel@tonic-gate IO_SYNC_CPU = (uint32_t)0x02 205*0Sstevel@tonic-gate } io_sync_direction_t; 206*0Sstevel@tonic-gate 207*0Sstevel@tonic-gate typedef enum pci_config_size { 208*0Sstevel@tonic-gate PCI_CFG_SIZE_BYTE = 0, 209*0Sstevel@tonic-gate PCI_CFG_SIZE_WORD, 210*0Sstevel@tonic-gate PCI_CFG_SIZE_DWORD 211*0Sstevel@tonic-gate } pci_config_size_t; 212*0Sstevel@tonic-gate 213*0Sstevel@tonic-gate typedef union pci_cfg_data { 214*0Sstevel@tonic-gate uint8_t b; 215*0Sstevel@tonic-gate uint16_t w; 216*0Sstevel@tonic-gate uint32_t dw; 217*0Sstevel@tonic-gate uint64_t qw; 218*0Sstevel@tonic-gate } pci_cfg_data_t; 219*0Sstevel@tonic-gate 220*0Sstevel@tonic-gate /* 221*0Sstevel@tonic-gate * MSI Definitions 222*0Sstevel@tonic-gate * 223*0Sstevel@tonic-gate * MSI - Message Signaled Interrupt 224*0Sstevel@tonic-gate * 225*0Sstevel@tonic-gate * Message Signaled Interrupt as defined in the PCI Local Bus 226*0Sstevel@tonic-gate * Specification and the PCI Express Base Specification. 227*0Sstevel@tonic-gate * A device signals an interrupt via MSI using a posted 228*0Sstevel@tonic-gate * write cycle to an address specified by system software 229*0Sstevel@tonic-gate * using a data value specified by system software. 230*0Sstevel@tonic-gate * The MSI capability data structure contains fields for 231*0Sstevel@tonic-gate * the PCI address and data values the device uses when 232*0Sstevel@tonic-gate * sending an MSI message on the bus. MSI-X is an extended 233*0Sstevel@tonic-gate * form of MSI, but uses the same mechanism for signaling 234*0Sstevel@tonic-gate * the interrupt as MSI. For the purposes of this document, 235*0Sstevel@tonic-gate * the term "MSI" refers to MSI or MSI-X. 236*0Sstevel@tonic-gate * 237*0Sstevel@tonic-gate * Root complexes that support MSI define an address range 238*0Sstevel@tonic-gate * and set of data values that can be used to signal MSIs. 239*0Sstevel@tonic-gate * 240*0Sstevel@tonic-gate * SUN4V/pci requirements for MSI: 241*0Sstevel@tonic-gate * 242*0Sstevel@tonic-gate * The root complex defines two address ranges. One in 243*0Sstevel@tonic-gate * the 32-bit pci memory space and one in the 64-bit 244*0Sstevel@tonic-gate * pci memory address space used as the target of a posted 245*0Sstevel@tonic-gate * write to signal an MSI. 246*0Sstevel@tonic-gate * 247*0Sstevel@tonic-gate * The root complex treats any write to these address 248*0Sstevel@tonic-gate * ranges as signaling an MSI, however, only the data 249*0Sstevel@tonic-gate * value used in the posted write signals the MSI. 250*0Sstevel@tonic-gate * 251*0Sstevel@tonic-gate * 252*0Sstevel@tonic-gate * MSI EQ - MSI Event Queue 253*0Sstevel@tonic-gate * 254*0Sstevel@tonic-gate * The MSI Event Queue is a page-aligned main memory data 255*0Sstevel@tonic-gate * structure used to store MSI data records. 256*0Sstevel@tonic-gate * 257*0Sstevel@tonic-gate * Each root port supports several MSI EQs, and each EQ has a 258*0Sstevel@tonic-gate * system interrupt associated with it, and can be targeted 259*0Sstevel@tonic-gate * (individually) to any cpu. The number of MSI EQs supported 260*0Sstevel@tonic-gate * by a root complex is described by a property defined in [3]. 261*0Sstevel@tonic-gate * Each MSI EQ must be large enough to contain all possible MSI 262*0Sstevel@tonic-gate * data records generated by any one PCI root port. The number 263*0Sstevel@tonic-gate * of entries in each MSI EQ is described by a property defined 264*0Sstevel@tonic-gate * in [3]. 265*0Sstevel@tonic-gate * 266*0Sstevel@tonic-gate * Each MSI EQ is compliant with the definition of interrupt 267*0Sstevel@tonic-gate * queues described in [5], however, instead of accessing the 268*0Sstevel@tonic-gate * queue head/tail registers via ASI-based registers, an API 269*0Sstevel@tonic-gate * is provided to access the head/tail registers. 270*0Sstevel@tonic-gate * 271*0Sstevel@tonic-gate * The SUN4V/pci compliant root complex has the ability to 272*0Sstevel@tonic-gate * generate a system interrupt when the MSI EQ is non-empty. 273*0Sstevel@tonic-gate * 274*0Sstevel@tonic-gate * MSI/Message/INTx Data Record format 275*0Sstevel@tonic-gate * 276*0Sstevel@tonic-gate * Each data record consists of 64 bytes of data, aligned 277*0Sstevel@tonic-gate * on a 64-byte boundary. 278*0Sstevel@tonic-gate * 279*0Sstevel@tonic-gate * The data record is defined as follows: 280*0Sstevel@tonic-gate * 281*0Sstevel@tonic-gate * 282*0Sstevel@tonic-gate * 6666555555555544444444443333333333222222222211111111110000000000 283*0Sstevel@tonic-gate * 3210987654321098765432109876543210987654321098765432109876543210 284*0Sstevel@tonic-gate * 285*0Sstevel@tonic-gate * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 286*0Sstevel@tonic-gate * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 287*0Sstevel@tonic-gate * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 288*0Sstevel@tonic-gate * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 289*0Sstevel@tonic-gate * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 290*0Sstevel@tonic-gate * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 291*0Sstevel@tonic-gate * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 292*0Sstevel@tonic-gate * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 293*0Sstevel@tonic-gate * 294*0Sstevel@tonic-gate * Where, 295*0Sstevel@tonic-gate * 296*0Sstevel@tonic-gate * xx..xx are unused bits and must be ignored by sw. 297*0Sstevel@tonic-gate * 298*0Sstevel@tonic-gate * VV..VV is the version number of this data record 299*0Sstevel@tonic-gate * 300*0Sstevel@tonic-gate * For this release of the spec, the version number 301*0Sstevel@tonic-gate * field must be zero. 302*0Sstevel@tonic-gate * 303*0Sstevel@tonic-gate * TTTTTTTT is the data record type: 304*0Sstevel@tonic-gate * 305*0Sstevel@tonic-gate * Upper 4 bits are reserved, and must be zero 306*0Sstevel@tonic-gate * 307*0Sstevel@tonic-gate * 0000 - Not an MSI data record - reserved for sw use. 308*0Sstevel@tonic-gate * 0001 - MSG 309*0Sstevel@tonic-gate * 0010 - MSI32 310*0Sstevel@tonic-gate * 0011 - MSI64 311*0Sstevel@tonic-gate * 0010 - Reserved 312*0Sstevel@tonic-gate * ... 313*0Sstevel@tonic-gate * 0111 - Reserved 314*0Sstevel@tonic-gate * 1000 - INTx 315*0Sstevel@tonic-gate * 1001 - Reserved 316*0Sstevel@tonic-gate * ... 317*0Sstevel@tonic-gate * 1110 - Reserved 318*0Sstevel@tonic-gate * 1111 - Not an MSI data record - reserved for sw use. 319*0Sstevel@tonic-gate * 320*0Sstevel@tonic-gate * All other encodings are reserved. 321*0Sstevel@tonic-gate * 322*0Sstevel@tonic-gate * II..II is the sysino for INTx (sw defined value), 323*0Sstevel@tonic-gate * otherwise zero. 324*0Sstevel@tonic-gate * 325*0Sstevel@tonic-gate * SS..SS is the message timestamp if available. 326*0Sstevel@tonic-gate * If supported by the implementation, a non-zero 327*0Sstevel@tonic-gate * value in this field is a copy of the %stick register 328*0Sstevel@tonic-gate * at the time the message is created. 329*0Sstevel@tonic-gate * 330*0Sstevel@tonic-gate * If unsupported, this field will contain zero. 331*0Sstevel@tonic-gate * 332*0Sstevel@tonic-gate * RR..RR is the requester ID of the device that initiated the MSI/MSG 333*0Sstevel@tonic-gate * and has the following format: 334*0Sstevel@tonic-gate * 335*0Sstevel@tonic-gate * bbbbbbbb.dddddfff 336*0Sstevel@tonic-gate * 337*0Sstevel@tonic-gate * Where bb..bb is the bus number, 338*0Sstevel@tonic-gate * dd..dd is the device number 339*0Sstevel@tonic-gate * and fff is the function number. 340*0Sstevel@tonic-gate * 341*0Sstevel@tonic-gate * Note that for PCI devices or any message where 342*0Sstevel@tonic-gate * the requester is unknown, this may be zero, 343*0Sstevel@tonic-gate * or the device-id of an intermediate bridge. 344*0Sstevel@tonic-gate * 345*0Sstevel@tonic-gate * For intx messages, this field should be ignored. 346*0Sstevel@tonic-gate * 347*0Sstevel@tonic-gate * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 348*0Sstevel@tonic-gate * (for data record type MSG or INTx, this field is ignored) 349*0Sstevel@tonic-gate * 350*0Sstevel@tonic-gate * DD..DD is the MSI/MSG data or INTx number 351*0Sstevel@tonic-gate * 352*0Sstevel@tonic-gate * For MSI-X, bits 31..0 contain the data from the MSI packet 353*0Sstevel@tonic-gate * which is the msi-number. bits 63..32 shall be zero. 354*0Sstevel@tonic-gate * 355*0Sstevel@tonic-gate * For MSI, bits 15..0 contain the data from the MSI message 356*0Sstevel@tonic-gate * which is the msi-number. bits 63..16 shall be zero 357*0Sstevel@tonic-gate * 358*0Sstevel@tonic-gate * For MSG data, the message code and message routing code 359*0Sstevel@tonic-gate * are encoded as follows: 360*0Sstevel@tonic-gate * 361*0Sstevel@tonic-gate * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 362*0Sstevel@tonic-gate * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 363*0Sstevel@tonic-gate * 364*0Sstevel@tonic-gate * Where, 365*0Sstevel@tonic-gate * 366*0Sstevel@tonic-gate * GG..GG is the target-id of the message in the 367*0Sstevel@tonic-gate * following form: 368*0Sstevel@tonic-gate * 369*0Sstevel@tonic-gate * bbbbbbbb.dddddfff 370*0Sstevel@tonic-gate * 371*0Sstevel@tonic-gate * where bb..bb is the target bus number. 372*0Sstevel@tonic-gate * ddddd is the target deviceid 373*0Sstevel@tonic-gate * fff is the target function number. 374*0Sstevel@tonic-gate * 375*0Sstevel@tonic-gate * CCC is the message routing code as defined by [4] 376*0Sstevel@tonic-gate * 377*0Sstevel@tonic-gate * MM..MM is the message code as defined by [4] 378*0Sstevel@tonic-gate * 379*0Sstevel@tonic-gate * For INTx data, bits 63:2 must be zero and 380*0Sstevel@tonic-gate * the low order 2 bits are defined as follows: 381*0Sstevel@tonic-gate * 382*0Sstevel@tonic-gate * 00 - INTA 383*0Sstevel@tonic-gate * 01 - INTB 384*0Sstevel@tonic-gate * 10 - INTC 385*0Sstevel@tonic-gate * 11 - INTD 386*0Sstevel@tonic-gate * 387*0Sstevel@tonic-gate * cpuid - A unique opaque value which represents a target cpu. 388*0Sstevel@tonic-gate * 389*0Sstevel@tonic-gate * devhandle - Device handle. The device handle uniquely identifies a 390*0Sstevel@tonic-gate * SUN4V device. It consists of the the lower 28-bits of the hi-cell 391*0Sstevel@tonic-gate * of the first entry of the SUN4V device's "reg" property as defined 392*0Sstevel@tonic-gate * by the SUN4V Bus Binding to Open Firmware. 393*0Sstevel@tonic-gate * 394*0Sstevel@tonic-gate * msinum - A value defining which MSI is being used. 395*0Sstevel@tonic-gate * 396*0Sstevel@tonic-gate * msiqhead - The index value of the current head index for a given 397*0Sstevel@tonic-gate * MSI-EQ. 398*0Sstevel@tonic-gate * 399*0Sstevel@tonic-gate * msiqtail - The index value of the current tail index for a given 400*0Sstevel@tonic-gate * MSI-EQ. 401*0Sstevel@tonic-gate * 402*0Sstevel@tonic-gate * msitype - Type specifier for MSI32 or MSI64 403*0Sstevel@tonic-gate * 0 - type is MSI32 404*0Sstevel@tonic-gate * 1 - type is MSI64 405*0Sstevel@tonic-gate * 406*0Sstevel@tonic-gate * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 407*0Sstevel@tonic-gate * which MSI EQ within the device is being used. 408*0Sstevel@tonic-gate * 409*0Sstevel@tonic-gate * msiqstate - An unsigned integer containing one of the 410*0Sstevel@tonic-gate * following values: 411*0Sstevel@tonic-gate * 412*0Sstevel@tonic-gate * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 413*0Sstevel@tonic-gate * PCI_MSIQSTATE_ERROR 1 # error state 414*0Sstevel@tonic-gate * 415*0Sstevel@tonic-gate * msiqvalid - An unsigned integer containing one of the 416*0Sstevel@tonic-gate * following values: 417*0Sstevel@tonic-gate * 418*0Sstevel@tonic-gate * PCI_MSIQ_INVALID 0 # disabled/invalid 419*0Sstevel@tonic-gate * PCI_MSIQ_VALID 1 # enabled/valid 420*0Sstevel@tonic-gate * 421*0Sstevel@tonic-gate * msistate - An unsigned integer containing one of the following 422*0Sstevel@tonic-gate * values: 423*0Sstevel@tonic-gate * 424*0Sstevel@tonic-gate * PCI_MSISTATE_IDLE 0 # idle/not enabled 425*0Sstevel@tonic-gate * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 426*0Sstevel@tonic-gate * 427*0Sstevel@tonic-gate * msivalid - An unsigned integer containing one of the 428*0Sstevel@tonic-gate * following values: 429*0Sstevel@tonic-gate * 430*0Sstevel@tonic-gate * PCI_MSI_INVALID 0 # disabled/invalid 431*0Sstevel@tonic-gate * PCI_MSI_VALID 1 # enabled/valid 432*0Sstevel@tonic-gate * 433*0Sstevel@tonic-gate * msgtype - A value defining which MSG type is being used. An unsigned 434*0Sstevel@tonic-gate * integer containing one of the following values: 435*0Sstevel@tonic-gate * (as per PCIe spec 1.0a) 436*0Sstevel@tonic-gate * 437*0Sstevel@tonic-gate * PCIE_PME_MSG 0x18 PME message 438*0Sstevel@tonic-gate * PCIE_PME_ACK_MSG 0x1b PME ACK message 439*0Sstevel@tonic-gate * PCIE_CORR_MSG 0x30 Correctable message 440*0Sstevel@tonic-gate * PCIE_NONFATAL_MSG 0x31 Non fatal message 441*0Sstevel@tonic-gate * PCIE_FATAL_MSG 0x33 Fatal message 442*0Sstevel@tonic-gate */ 443*0Sstevel@tonic-gate 444*0Sstevel@tonic-gate typedef uint32_t msinum_t; 445*0Sstevel@tonic-gate typedef uint32_t msiqid_t; 446*0Sstevel@tonic-gate typedef uint32_t msgcode_t; 447*0Sstevel@tonic-gate typedef uint64_t msiqhead_t; 448*0Sstevel@tonic-gate typedef uint64_t msiqtail_t; 449*0Sstevel@tonic-gate 450*0Sstevel@tonic-gate /* MSIQ state */ 451*0Sstevel@tonic-gate typedef enum pci_msiq_state { 452*0Sstevel@tonic-gate PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 453*0Sstevel@tonic-gate PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 454*0Sstevel@tonic-gate } pci_msiq_state_t; 455*0Sstevel@tonic-gate 456*0Sstevel@tonic-gate /* MSIQ valid */ 457*0Sstevel@tonic-gate typedef enum pci_msiq_valid_state { 458*0Sstevel@tonic-gate PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 459*0Sstevel@tonic-gate PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 460*0Sstevel@tonic-gate } pci_msiq_valid_state_t; 461*0Sstevel@tonic-gate 462*0Sstevel@tonic-gate /* MSIQ Record data structure */ 463*0Sstevel@tonic-gate typedef struct msiq_rec { 464*0Sstevel@tonic-gate uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 465*0Sstevel@tonic-gate msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 466*0Sstevel@tonic-gate msiq_rec_type : 8; /* DW 0 - 07:00 */ 467*0Sstevel@tonic-gate uint64_t msiq_rec_intx; /* DW 1 */ 468*0Sstevel@tonic-gate uint64_t msiq_rec_rsvd1; /* DW 2 */ 469*0Sstevel@tonic-gate uint64_t msiq_rec_timestamp; /* DW 3 */ 470*0Sstevel@tonic-gate uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 471*0Sstevel@tonic-gate msiq_rec_rid : 16; /* DW 4 - 15:00 */ 472*0Sstevel@tonic-gate uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 473*0Sstevel@tonic-gate union { 474*0Sstevel@tonic-gate struct { 475*0Sstevel@tonic-gate uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 476*0Sstevel@tonic-gate msix_data : 32; /* DW 6 - 31:00 */ 477*0Sstevel@tonic-gate } msix; 478*0Sstevel@tonic-gate struct { 479*0Sstevel@tonic-gate uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 480*0Sstevel@tonic-gate msi_data: 16; /* DW 6 - 15:00 */ 481*0Sstevel@tonic-gate } msi; 482*0Sstevel@tonic-gate struct { 483*0Sstevel@tonic-gate uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 484*0Sstevel@tonic-gate msg_targ: 8, /* DW 6 - 39:32 */ 485*0Sstevel@tonic-gate msg_rsvd1: 13, /* DW 6 - 31:19 */ 486*0Sstevel@tonic-gate msg_route: 3, /* DW 6 - 18:16 */ 487*0Sstevel@tonic-gate msg_rsvd2: 8, /* DW 6 - 15:08 */ 488*0Sstevel@tonic-gate msg_code: 8; /* DW 6 - 07:00 */ 489*0Sstevel@tonic-gate } msg; 490*0Sstevel@tonic-gate } msiq_rec_data; 491*0Sstevel@tonic-gate uint64_t msiq_rec_rsvd3; /* DW 7 */ 492*0Sstevel@tonic-gate } msiq_rec_t; 493*0Sstevel@tonic-gate 494*0Sstevel@tonic-gate /* MSIQ Record type */ 495*0Sstevel@tonic-gate typedef enum msiq_rec_type { 496*0Sstevel@tonic-gate MSG_REC = (uint32_t)1, /* PCIe message record */ 497*0Sstevel@tonic-gate MSI32_REC = (uint32_t)2, /* MSI32 record */ 498*0Sstevel@tonic-gate MSI64_REC = (uint32_t)3, /* MSI64 record */ 499*0Sstevel@tonic-gate INTX_REC = (uint32_t)8 /* INTx record */ 500*0Sstevel@tonic-gate } msiq_rec_type_t; 501*0Sstevel@tonic-gate 502*0Sstevel@tonic-gate /* MSIQ Record type */ 503*0Sstevel@tonic-gate typedef enum msi_type { 504*0Sstevel@tonic-gate MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 505*0Sstevel@tonic-gate MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 506*0Sstevel@tonic-gate } msi_type_t; 507*0Sstevel@tonic-gate 508*0Sstevel@tonic-gate /* MSI state */ 509*0Sstevel@tonic-gate typedef enum pci_msi_state { 510*0Sstevel@tonic-gate PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 511*0Sstevel@tonic-gate PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 512*0Sstevel@tonic-gate } pci_msi_state_t; 513*0Sstevel@tonic-gate 514*0Sstevel@tonic-gate /* MSI valid */ 515*0Sstevel@tonic-gate typedef enum pci_msi_valid_state { 516*0Sstevel@tonic-gate PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 517*0Sstevel@tonic-gate PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 518*0Sstevel@tonic-gate } pci_msi_valid_state_t; 519*0Sstevel@tonic-gate 520*0Sstevel@tonic-gate /* MSG valid */ 521*0Sstevel@tonic-gate typedef enum pcie_msg_valid_state { 522*0Sstevel@tonic-gate PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 523*0Sstevel@tonic-gate PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 524*0Sstevel@tonic-gate } pcie_msg_valid_state_t; 525*0Sstevel@tonic-gate 526*0Sstevel@tonic-gate /* PCIe MSG types */ 527*0Sstevel@tonic-gate typedef enum pcie_msg_type { 528*0Sstevel@tonic-gate PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 529*0Sstevel@tonic-gate PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 530*0Sstevel@tonic-gate PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 531*0Sstevel@tonic-gate PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 532*0Sstevel@tonic-gate PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 533*0Sstevel@tonic-gate } pcie_msg_type_t; 534*0Sstevel@tonic-gate 535*0Sstevel@tonic-gate #endif /* _ASM */ 536*0Sstevel@tonic-gate 537*0Sstevel@tonic-gate #ifdef __cplusplus 538*0Sstevel@tonic-gate } 539*0Sstevel@tonic-gate #endif 540*0Sstevel@tonic-gate 541*0Sstevel@tonic-gate #endif /* _SYS_PX_IOAPI_H */ 542