1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * PX nexus interrupt handling: 31*0Sstevel@tonic-gate * PX device interrupt handler wrapper 32*0Sstevel@tonic-gate * PIL lookup routine 33*0Sstevel@tonic-gate * PX device interrupt related initchild code 34*0Sstevel@tonic-gate */ 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #include <sys/types.h> 37*0Sstevel@tonic-gate #include <sys/kmem.h> 38*0Sstevel@tonic-gate #include <sys/async.h> 39*0Sstevel@tonic-gate #include <sys/spl.h> 40*0Sstevel@tonic-gate #include <sys/sunddi.h> 41*0Sstevel@tonic-gate #include <sys/machsystm.h> /* e_ddi_nodeid_to_dip() */ 42*0Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 43*0Sstevel@tonic-gate #include <sys/sdt.h> 44*0Sstevel@tonic-gate #include <sys/atomic.h> 45*0Sstevel@tonic-gate #include "px_obj.h" 46*0Sstevel@tonic-gate 47*0Sstevel@tonic-gate /* 48*0Sstevel@tonic-gate * interrupt jabber: 49*0Sstevel@tonic-gate * 50*0Sstevel@tonic-gate * When an interrupt line is jabbering, every time the state machine for the 51*0Sstevel@tonic-gate * associated ino is idled, a new mondo will be sent and the ino will go into 52*0Sstevel@tonic-gate * the pending state again. The mondo will cause a new call to 53*0Sstevel@tonic-gate * px_intr_wrapper() which normally idles the ino's state machine which would 54*0Sstevel@tonic-gate * precipitate another trip round the loop. 55*0Sstevel@tonic-gate * 56*0Sstevel@tonic-gate * The loop can be broken by preventing the ino's state machine from being 57*0Sstevel@tonic-gate * idled when an interrupt line is jabbering. See the comment at the 58*0Sstevel@tonic-gate * beginning of px_intr_wrapper() explaining how the 'interrupt jabber 59*0Sstevel@tonic-gate * protection' code does this. 60*0Sstevel@tonic-gate */ 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate /*LINTLIBRARY*/ 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate /* 66*0Sstevel@tonic-gate * If the unclaimed interrupt count has reached the limit set by 67*0Sstevel@tonic-gate * pci_unclaimed_intr_max within the time limit, then all interrupts 68*0Sstevel@tonic-gate * on this ino is blocked by not idling the interrupt state machine. 69*0Sstevel@tonic-gate */ 70*0Sstevel@tonic-gate static int 71*0Sstevel@tonic-gate px_spurintr(px_ib_ino_info_t *ino_p) 72*0Sstevel@tonic-gate { 73*0Sstevel@tonic-gate px_ih_t *ih_p = ino_p->ino_ih_start; 74*0Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 75*0Sstevel@tonic-gate char *err_fmt_str; 76*0Sstevel@tonic-gate int i; 77*0Sstevel@tonic-gate 78*0Sstevel@tonic-gate if (ino_p->ino_unclaimed > px_unclaimed_intr_max) 79*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 80*0Sstevel@tonic-gate 81*0Sstevel@tonic-gate if (!ino_p->ino_unclaimed) 82*0Sstevel@tonic-gate ino_p->ino_spurintr_begin = ddi_get_lbolt(); 83*0Sstevel@tonic-gate 84*0Sstevel@tonic-gate ino_p->ino_unclaimed++; 85*0Sstevel@tonic-gate 86*0Sstevel@tonic-gate if (ino_p->ino_unclaimed <= px_unclaimed_intr_max) 87*0Sstevel@tonic-gate goto clear; 88*0Sstevel@tonic-gate 89*0Sstevel@tonic-gate if (drv_hztousec(ddi_get_lbolt() - ino_p->ino_spurintr_begin) 90*0Sstevel@tonic-gate > px_spurintr_duration) { 91*0Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 92*0Sstevel@tonic-gate goto clear; 93*0Sstevel@tonic-gate } 94*0Sstevel@tonic-gate err_fmt_str = "%s%d: ino 0x%x blocked"; 95*0Sstevel@tonic-gate goto warn; 96*0Sstevel@tonic-gate clear: 97*0Sstevel@tonic-gate /* Clear the pending state */ 98*0Sstevel@tonic-gate if (px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 99*0Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 100*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 101*0Sstevel@tonic-gate 102*0Sstevel@tonic-gate err_fmt_str = "!%s%d: spurious interrupt from ino 0x%x"; 103*0Sstevel@tonic-gate warn: 104*0Sstevel@tonic-gate cmn_err(CE_WARN, err_fmt_str, NAMEINST(px_p->px_dip), ino_p->ino_ino); 105*0Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) 106*0Sstevel@tonic-gate cmn_err(CE_CONT, "!%s-%d#%x ", NAMEINST(ih_p->ih_dip), 107*0Sstevel@tonic-gate ih_p->ih_inum); 108*0Sstevel@tonic-gate cmn_err(CE_CONT, "!\n"); 109*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 110*0Sstevel@tonic-gate } 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate extern uint64_t intr_get_time(void); 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate /* 116*0Sstevel@tonic-gate * px_intx_intr (legacy or intx interrupt handler) 117*0Sstevel@tonic-gate * 118*0Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 119*0Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 120*0Sstevel@tonic-gate * examines the return codes. 121*0Sstevel@tonic-gate * 122*0Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 123*0Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 124*0Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 125*0Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 126*0Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 127*0Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 128*0Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 129*0Sstevel@tonic-gate * handler is subsequently added or removed. 130*0Sstevel@tonic-gate * 131*0Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 132*0Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 133*0Sstevel@tonic-gate */ 134*0Sstevel@tonic-gate uint_t 135*0Sstevel@tonic-gate px_intx_intr(caddr_t arg) 136*0Sstevel@tonic-gate { 137*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 138*0Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 139*0Sstevel@tonic-gate px_ih_t *ih_p = ino_p->ino_ih_start; 140*0Sstevel@tonic-gate uint_t result = 0, r; 141*0Sstevel@tonic-gate int i; 142*0Sstevel@tonic-gate 143*0Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 144*0Sstevel@tonic-gate "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n", 145*0Sstevel@tonic-gate ino_p->ino_ino, ino_p->ino_sysino, ino_p->ino_pil, 146*0Sstevel@tonic-gate ino_p->ino_ih_size, ino_p->ino_ih_head); 147*0Sstevel@tonic-gate 148*0Sstevel@tonic-gate for (i = 0; i < ino_p->ino_ih_size; i++, ih_p = ih_p->ih_next) { 149*0Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 150*0Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 151*0Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 152*0Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate if (ih_p->ih_intr_state == PX_INTR_STATE_DISABLE) { 155*0Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, 156*0Sstevel@tonic-gate "px_intx_intr: %s%d interrupt %d is disabled\n", 157*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 158*0Sstevel@tonic-gate ino_p->ino_ino); 159*0Sstevel@tonic-gate 160*0Sstevel@tonic-gate continue; 161*0Sstevel@tonic-gate } 162*0Sstevel@tonic-gate 163*0Sstevel@tonic-gate DBG(DBG_INTX_INTR, px_p->px_dip, "px_intx_intr:" 164*0Sstevel@tonic-gate "ino=%x handler=%p arg1 =%p arg2 = %p\n", 165*0Sstevel@tonic-gate ino_p->ino_ino, handler, arg1, arg2); 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 168*0Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 169*0Sstevel@tonic-gate 170*0Sstevel@tonic-gate r = (*handler)(arg1, arg2); 171*0Sstevel@tonic-gate 172*0Sstevel@tonic-gate /* 173*0Sstevel@tonic-gate * Account for time used by this interrupt. Protect against 174*0Sstevel@tonic-gate * conflicting writes to ih_ticks from ib_intr_dist_all() by 175*0Sstevel@tonic-gate * using atomic ops. 176*0Sstevel@tonic-gate */ 177*0Sstevel@tonic-gate 178*0Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 179*0Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 180*0Sstevel@tonic-gate 181*0Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 182*0Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, r); 183*0Sstevel@tonic-gate 184*0Sstevel@tonic-gate result += r; 185*0Sstevel@tonic-gate 186*0Sstevel@tonic-gate if (px_check_all_handlers) 187*0Sstevel@tonic-gate continue; 188*0Sstevel@tonic-gate if (result) 189*0Sstevel@tonic-gate break; 190*0Sstevel@tonic-gate } 191*0Sstevel@tonic-gate 192*0Sstevel@tonic-gate if (!result && px_unclaimed_intr_block) 193*0Sstevel@tonic-gate return (px_spurintr(ino_p)); 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate ino_p->ino_unclaimed = 0; 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate /* Clear the pending state */ 198*0Sstevel@tonic-gate if (px_lib_intr_setstate(ino_p->ino_ib_p->ib_px_p->px_dip, 199*0Sstevel@tonic-gate ino_p->ino_sysino, INTR_IDLE_STATE) != DDI_SUCCESS) 200*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 201*0Sstevel@tonic-gate 202*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 203*0Sstevel@tonic-gate } 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate /* 206*0Sstevel@tonic-gate * px_msiq_intr (MSI/MSIX/MSG interrupt handler) 207*0Sstevel@tonic-gate * 208*0Sstevel@tonic-gate * This routine is used as wrapper around interrupt handlers installed by child 209*0Sstevel@tonic-gate * device drivers. This routine invokes the driver interrupt handlers and 210*0Sstevel@tonic-gate * examines the return codes. 211*0Sstevel@tonic-gate * 212*0Sstevel@tonic-gate * There is a count of unclaimed interrupts kept on a per-ino basis. If at 213*0Sstevel@tonic-gate * least one handler claims the interrupt then the counter is halved and the 214*0Sstevel@tonic-gate * interrupt state machine is idled. If no handler claims the interrupt then 215*0Sstevel@tonic-gate * the counter is incremented by one and the state machine is idled. 216*0Sstevel@tonic-gate * If the count ever reaches the limit value set by pci_unclaimed_intr_max 217*0Sstevel@tonic-gate * then the interrupt state machine is not idled thus preventing any further 218*0Sstevel@tonic-gate * interrupts on that ino. The state machine will only be idled again if a 219*0Sstevel@tonic-gate * handler is subsequently added or removed. 220*0Sstevel@tonic-gate * 221*0Sstevel@tonic-gate * return value: DDI_INTR_CLAIMED if any handlers claimed the interrupt, 222*0Sstevel@tonic-gate * DDI_INTR_UNCLAIMED otherwise. 223*0Sstevel@tonic-gate */ 224*0Sstevel@tonic-gate uint_t 225*0Sstevel@tonic-gate px_msiq_intr(caddr_t arg) 226*0Sstevel@tonic-gate { 227*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p = (px_ib_ino_info_t *)arg; 228*0Sstevel@tonic-gate px_t *px_p = ino_p->ino_ib_p->ib_px_p; 229*0Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 230*0Sstevel@tonic-gate px_msiq_t *msiq_p = ino_p->ino_msiq_p; 231*0Sstevel@tonic-gate dev_info_t *dip = px_p->px_dip; 232*0Sstevel@tonic-gate msiq_rec_t msiq_rec, *msiq_rec_p = &msiq_rec; 233*0Sstevel@tonic-gate msiqhead_t curr_msiq_rec_cnt, new_msiq_rec_cnt; 234*0Sstevel@tonic-gate msgcode_t msg_code; 235*0Sstevel@tonic-gate px_ih_t *ih_p; 236*0Sstevel@tonic-gate int ret; 237*0Sstevel@tonic-gate 238*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x " 239*0Sstevel@tonic-gate "ih_size=%x ih_lst=%x\n", msiq_p->msiq_id, ino_p->ino_ino, 240*0Sstevel@tonic-gate ino_p->ino_pil, ino_p->ino_ih_size, ino_p->ino_ih_head); 241*0Sstevel@tonic-gate 242*0Sstevel@tonic-gate /* Read current MSIQ head index */ 243*0Sstevel@tonic-gate px_lib_msiq_gethead(dip, msiq_p->msiq_id, &curr_msiq_rec_cnt); 244*0Sstevel@tonic-gate msiq_p->msiq_curr = (uint64_t)((caddr_t)msiq_p->msiq_base + 245*0Sstevel@tonic-gate curr_msiq_rec_cnt * sizeof (msiq_rec_t)); 246*0Sstevel@tonic-gate new_msiq_rec_cnt = curr_msiq_rec_cnt; 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate /* Read next MSIQ record */ 249*0Sstevel@tonic-gate px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 250*0Sstevel@tonic-gate 251*0Sstevel@tonic-gate /* 252*0Sstevel@tonic-gate * Process current MSIQ record as long as request id 253*0Sstevel@tonic-gate * field is non-zero. 254*0Sstevel@tonic-gate */ 255*0Sstevel@tonic-gate while (msiq_rec_p->msiq_rec_rid) { 256*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSIQ RECORD, " 257*0Sstevel@tonic-gate "msiq_rec_type 0x%llx msiq_rec_rid 0x%llx\n", 258*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_type, msiq_rec_p->msiq_rec_rid); 259*0Sstevel@tonic-gate 260*0Sstevel@tonic-gate /* Get the pointer next EQ record */ 261*0Sstevel@tonic-gate msiq_p->msiq_curr = (uint64_t) 262*0Sstevel@tonic-gate ((caddr_t)msiq_p->msiq_curr + sizeof (msiq_rec_t)); 263*0Sstevel@tonic-gate 264*0Sstevel@tonic-gate /* Check for overflow condition */ 265*0Sstevel@tonic-gate if (msiq_p->msiq_curr >= (uint64_t)((caddr_t)msiq_p->msiq_base + 266*0Sstevel@tonic-gate msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t))) 267*0Sstevel@tonic-gate msiq_p->msiq_curr = msiq_p->msiq_base; 268*0Sstevel@tonic-gate 269*0Sstevel@tonic-gate /* Check MSIQ record type */ 270*0Sstevel@tonic-gate switch (msiq_rec_p->msiq_rec_type) { 271*0Sstevel@tonic-gate case MSG_REC: 272*0Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msg.msg_code; 273*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: PCIE MSG " 274*0Sstevel@tonic-gate "record, msg type 0x%x\n", msg_code); 275*0Sstevel@tonic-gate break; 276*0Sstevel@tonic-gate case MSI32_REC: 277*0Sstevel@tonic-gate case MSI64_REC: 278*0Sstevel@tonic-gate msg_code = msiq_rec_p->msiq_rec_data.msi.msi_data; 279*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: MSI record, " 280*0Sstevel@tonic-gate "msi 0x%x\n", msg_code); 281*0Sstevel@tonic-gate 282*0Sstevel@tonic-gate /* Clear MSI state */ 283*0Sstevel@tonic-gate px_lib_msi_setstate(dip, (msinum_t)msg_code, 284*0Sstevel@tonic-gate PCI_MSI_STATE_IDLE); 285*0Sstevel@tonic-gate break; 286*0Sstevel@tonic-gate default: 287*0Sstevel@tonic-gate msg_code = 0; 288*0Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: px_msiq_intr: 0x%x MSIQ " 289*0Sstevel@tonic-gate "record type is not supported", 290*0Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), 291*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_type); 292*0Sstevel@tonic-gate goto next_rec; 293*0Sstevel@tonic-gate } 294*0Sstevel@tonic-gate 295*0Sstevel@tonic-gate ih_p = ino_p->ino_ih_start; 296*0Sstevel@tonic-gate 297*0Sstevel@tonic-gate /* 298*0Sstevel@tonic-gate * Scan through px_ih_t linked list, searching for the 299*0Sstevel@tonic-gate * right px_ih_t, matching MSIQ record data. 300*0Sstevel@tonic-gate */ 301*0Sstevel@tonic-gate while ((ih_p) && (ih_p->ih_msg_code != msg_code) && 302*0Sstevel@tonic-gate (ih_p->ih_rec_type != msiq_rec_p->msiq_rec_type)) 303*0Sstevel@tonic-gate ih_p = ih_p->ih_next; 304*0Sstevel@tonic-gate 305*0Sstevel@tonic-gate if ((ih_p->ih_msg_code == msg_code) && 306*0Sstevel@tonic-gate (ih_p->ih_rec_type == msiq_rec_p->msiq_rec_type)) { 307*0Sstevel@tonic-gate dev_info_t *dip = ih_p->ih_dip; 308*0Sstevel@tonic-gate uint_t (*handler)() = ih_p->ih_handler; 309*0Sstevel@tonic-gate caddr_t arg1 = ih_p->ih_handler_arg1; 310*0Sstevel@tonic-gate caddr_t arg2 = ih_p->ih_handler_arg2; 311*0Sstevel@tonic-gate 312*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: ino=%x data=%x " 313*0Sstevel@tonic-gate "handler=%p arg1 =%p arg2=%p\n", ino_p->ino_ino, 314*0Sstevel@tonic-gate msg_code, handler, arg1, arg2); 315*0Sstevel@tonic-gate 316*0Sstevel@tonic-gate DTRACE_PROBE4(interrupt__start, dev_info_t, dip, 317*0Sstevel@tonic-gate void *, handler, caddr_t, arg1, caddr_t, arg2); 318*0Sstevel@tonic-gate 319*0Sstevel@tonic-gate if (msiq_rec_p->msiq_rec_type == MSG_REC) 320*0Sstevel@tonic-gate px_p->px_pec_p->pec_msiq_rec_p = msiq_rec_p; 321*0Sstevel@tonic-gate 322*0Sstevel@tonic-gate ret = (*handler)(arg1, arg2); 323*0Sstevel@tonic-gate 324*0Sstevel@tonic-gate /* 325*0Sstevel@tonic-gate * Account for time used by this interrupt. Protect 326*0Sstevel@tonic-gate * against conflicting writes to ih_ticks from 327*0Sstevel@tonic-gate * ib_intr_dist_all() by using atomic ops. 328*0Sstevel@tonic-gate */ 329*0Sstevel@tonic-gate 330*0Sstevel@tonic-gate if (ino_p->ino_pil <= LOCK_LEVEL) 331*0Sstevel@tonic-gate atomic_add_64(&ih_p->ih_ticks, intr_get_time()); 332*0Sstevel@tonic-gate 333*0Sstevel@tonic-gate DTRACE_PROBE4(interrupt__complete, dev_info_t, dip, 334*0Sstevel@tonic-gate void *, handler, caddr_t, arg1, int, ret); 335*0Sstevel@tonic-gate } else { 336*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr:" 337*0Sstevel@tonic-gate "Not found matching MSIQ record\n"); 338*0Sstevel@tonic-gate 339*0Sstevel@tonic-gate /* px_spurintr(ino_p); */ 340*0Sstevel@tonic-gate ino_p->ino_unclaimed++; 341*0Sstevel@tonic-gate } 342*0Sstevel@tonic-gate 343*0Sstevel@tonic-gate next_rec: 344*0Sstevel@tonic-gate new_msiq_rec_cnt++; 345*0Sstevel@tonic-gate 346*0Sstevel@tonic-gate /* Zero out msiq_rec_rid field */ 347*0Sstevel@tonic-gate msiq_rec_p->msiq_rec_rid = 0; 348*0Sstevel@tonic-gate 349*0Sstevel@tonic-gate /* Read next MSIQ record */ 350*0Sstevel@tonic-gate px_lib_get_msiq_rec(dip, msiq_p, msiq_rec_p); 351*0Sstevel@tonic-gate } 352*0Sstevel@tonic-gate 353*0Sstevel@tonic-gate DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: No of MSIQ recs processed %x\n", 354*0Sstevel@tonic-gate (new_msiq_rec_cnt - curr_msiq_rec_cnt)); 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate /* Update MSIQ head index with no of MSIQ records processed */ 357*0Sstevel@tonic-gate if (new_msiq_rec_cnt > curr_msiq_rec_cnt) { 358*0Sstevel@tonic-gate if (new_msiq_rec_cnt >= msiq_state_p->msiq_rec_cnt) 359*0Sstevel@tonic-gate new_msiq_rec_cnt -= msiq_state_p->msiq_rec_cnt; 360*0Sstevel@tonic-gate 361*0Sstevel@tonic-gate px_lib_msiq_sethead(dip, msiq_p->msiq_id, new_msiq_rec_cnt); 362*0Sstevel@tonic-gate } 363*0Sstevel@tonic-gate 364*0Sstevel@tonic-gate /* Clear the pending state */ 365*0Sstevel@tonic-gate if (px_lib_intr_setstate(dip, ino_p->ino_sysino, 366*0Sstevel@tonic-gate INTR_IDLE_STATE) != DDI_SUCCESS) 367*0Sstevel@tonic-gate return (DDI_INTR_UNCLAIMED); 368*0Sstevel@tonic-gate 369*0Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 370*0Sstevel@tonic-gate } 371*0Sstevel@tonic-gate 372*0Sstevel@tonic-gate dev_info_t * 373*0Sstevel@tonic-gate px_get_my_childs_dip(dev_info_t *dip, dev_info_t *rdip) 374*0Sstevel@tonic-gate { 375*0Sstevel@tonic-gate dev_info_t *cdip = rdip; 376*0Sstevel@tonic-gate 377*0Sstevel@tonic-gate for (; ddi_get_parent(cdip) != dip; cdip = ddi_get_parent(cdip)) 378*0Sstevel@tonic-gate ; 379*0Sstevel@tonic-gate 380*0Sstevel@tonic-gate return (cdip); 381*0Sstevel@tonic-gate } 382*0Sstevel@tonic-gate 383*0Sstevel@tonic-gate /* Default class to pil value mapping */ 384*0Sstevel@tonic-gate px_class_val_t px_default_pil [] = { 385*0Sstevel@tonic-gate {0x000000, 0xff0000, 0x1}, /* Class code for pre-2.0 devices */ 386*0Sstevel@tonic-gate {0x010000, 0xff0000, 0x4}, /* Mass Storage Controller */ 387*0Sstevel@tonic-gate {0x020000, 0xff0000, 0x6}, /* Network Controller */ 388*0Sstevel@tonic-gate {0x030000, 0xff0000, 0x9}, /* Display Controller */ 389*0Sstevel@tonic-gate {0x040000, 0xff0000, 0x9}, /* Multimedia Controller */ 390*0Sstevel@tonic-gate {0x050000, 0xff0000, 0xb}, /* Memory Controller */ 391*0Sstevel@tonic-gate {0x060000, 0xff0000, 0xb}, /* Bridge Controller */ 392*0Sstevel@tonic-gate {0x0c0000, 0xffff00, 0x9}, /* Serial Bus, FireWire (IEEE 1394) */ 393*0Sstevel@tonic-gate {0x0c0100, 0xffff00, 0x4}, /* Serial Bus, ACCESS.bus */ 394*0Sstevel@tonic-gate {0x0c0200, 0xffff00, 0x4}, /* Serial Bus, SSA */ 395*0Sstevel@tonic-gate {0x0c0300, 0xffff00, 0x9}, /* Serial Bus Universal Serial Bus */ 396*0Sstevel@tonic-gate {0x0c0400, 0xffff00, 0x6}, /* Serial Bus, Fibre Channel */ 397*0Sstevel@tonic-gate {0x0c0600, 0xffff00, 0x6} /* Serial Bus, Infiniband */ 398*0Sstevel@tonic-gate }; 399*0Sstevel@tonic-gate 400*0Sstevel@tonic-gate /* 401*0Sstevel@tonic-gate * Default class to intr_weight value mapping (% of CPU). A driver.conf 402*0Sstevel@tonic-gate * entry on or above the pci node like 403*0Sstevel@tonic-gate * 404*0Sstevel@tonic-gate * pci-class-intr-weights= 0x020000, 0xff0000, 30; 405*0Sstevel@tonic-gate * 406*0Sstevel@tonic-gate * can be used to augment or override entries in the default table below. 407*0Sstevel@tonic-gate * 408*0Sstevel@tonic-gate * NB: The values below give NICs preference on redistribution, and provide 409*0Sstevel@tonic-gate * NICs some isolation from other interrupt sources. We need better interfaces 410*0Sstevel@tonic-gate * that allow the NIC driver to identify a specific NIC instance as high 411*0Sstevel@tonic-gate * bandwidth, and thus deserving of separation from other low bandwidth 412*0Sstevel@tonic-gate * NICs additional isolation from other interrupt sources. 413*0Sstevel@tonic-gate * 414*0Sstevel@tonic-gate * NB: We treat Infiniband like a NIC. 415*0Sstevel@tonic-gate */ 416*0Sstevel@tonic-gate px_class_val_t px_default_intr_weight [] = { 417*0Sstevel@tonic-gate {0x020000, 0xff0000, 35}, /* Network Controller */ 418*0Sstevel@tonic-gate {0x010000, 0xff0000, 10}, /* Mass Storage Controller */ 419*0Sstevel@tonic-gate {0x0c0400, 0xffff00, 10}, /* Serial Bus, Fibre Channel */ 420*0Sstevel@tonic-gate {0x0c0600, 0xffff00, 50} /* Serial Bus, Infiniband */ 421*0Sstevel@tonic-gate }; 422*0Sstevel@tonic-gate 423*0Sstevel@tonic-gate static uint32_t 424*0Sstevel@tonic-gate px_match_class_val(uint32_t key, px_class_val_t *rec_p, int nrec, 425*0Sstevel@tonic-gate uint32_t default_val) 426*0Sstevel@tonic-gate { 427*0Sstevel@tonic-gate int i; 428*0Sstevel@tonic-gate 429*0Sstevel@tonic-gate for (i = 0; i < nrec; rec_p++, i++) { 430*0Sstevel@tonic-gate if ((rec_p->class_code & rec_p->class_mask) == 431*0Sstevel@tonic-gate (key & rec_p->class_mask)) 432*0Sstevel@tonic-gate return (rec_p->class_val); 433*0Sstevel@tonic-gate } 434*0Sstevel@tonic-gate 435*0Sstevel@tonic-gate return (default_val); 436*0Sstevel@tonic-gate } 437*0Sstevel@tonic-gate 438*0Sstevel@tonic-gate /* 439*0Sstevel@tonic-gate * px_class_to_val 440*0Sstevel@tonic-gate * 441*0Sstevel@tonic-gate * Return the configuration value, based on class code and sub class code, 442*0Sstevel@tonic-gate * from the specified property based or default px_class_val_t table. 443*0Sstevel@tonic-gate */ 444*0Sstevel@tonic-gate uint32_t 445*0Sstevel@tonic-gate px_class_to_val(dev_info_t *rdip, char *property_name, px_class_val_t *rec_p, 446*0Sstevel@tonic-gate int nrec, uint32_t default_val) 447*0Sstevel@tonic-gate { 448*0Sstevel@tonic-gate int property_len; 449*0Sstevel@tonic-gate uint32_t class_code; 450*0Sstevel@tonic-gate px_class_val_t *conf; 451*0Sstevel@tonic-gate uint32_t val = default_val; 452*0Sstevel@tonic-gate 453*0Sstevel@tonic-gate /* 454*0Sstevel@tonic-gate * Use the "class-code" property to get the base and sub class 455*0Sstevel@tonic-gate * codes for the requesting device. 456*0Sstevel@tonic-gate */ 457*0Sstevel@tonic-gate class_code = (uint32_t)ddi_prop_get_int(DDI_DEV_T_ANY, rdip, 458*0Sstevel@tonic-gate DDI_PROP_DONTPASS, "class-code", -1); 459*0Sstevel@tonic-gate 460*0Sstevel@tonic-gate if (class_code == -1) 461*0Sstevel@tonic-gate return (val); 462*0Sstevel@tonic-gate 463*0Sstevel@tonic-gate /* look up the val from the default table */ 464*0Sstevel@tonic-gate val = px_match_class_val(class_code, rec_p, nrec, val); 465*0Sstevel@tonic-gate 466*0Sstevel@tonic-gate /* see if there is a more specific property specified value */ 467*0Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, DDI_PROP_NOTPROM, 468*0Sstevel@tonic-gate property_name, (caddr_t)&conf, &property_len)) 469*0Sstevel@tonic-gate return (val); 470*0Sstevel@tonic-gate 471*0Sstevel@tonic-gate if ((property_len % sizeof (px_class_val_t)) == 0) 472*0Sstevel@tonic-gate val = px_match_class_val(class_code, conf, 473*0Sstevel@tonic-gate property_len / sizeof (px_class_val_t), val); 474*0Sstevel@tonic-gate kmem_free(conf, property_len); 475*0Sstevel@tonic-gate return (val); 476*0Sstevel@tonic-gate } 477*0Sstevel@tonic-gate 478*0Sstevel@tonic-gate 479*0Sstevel@tonic-gate /* px_class_to_pil: return the pil for a given device. */ 480*0Sstevel@tonic-gate uint32_t 481*0Sstevel@tonic-gate px_class_to_pil(dev_info_t *rdip) 482*0Sstevel@tonic-gate { 483*0Sstevel@tonic-gate uint32_t pil; 484*0Sstevel@tonic-gate 485*0Sstevel@tonic-gate /* default pil is 0 (uninitialized) */ 486*0Sstevel@tonic-gate pil = px_class_to_val(rdip, 487*0Sstevel@tonic-gate "pci-class-priorities", px_default_pil, 488*0Sstevel@tonic-gate sizeof (px_default_pil) / sizeof (px_class_val_t), 0); 489*0Sstevel@tonic-gate 490*0Sstevel@tonic-gate /* range check the result */ 491*0Sstevel@tonic-gate if (pil >= 0xf) 492*0Sstevel@tonic-gate pil = 0; 493*0Sstevel@tonic-gate 494*0Sstevel@tonic-gate return (pil); 495*0Sstevel@tonic-gate } 496*0Sstevel@tonic-gate 497*0Sstevel@tonic-gate 498*0Sstevel@tonic-gate /* px_class_to_intr_weight: return the intr_weight for a given device. */ 499*0Sstevel@tonic-gate static int32_t 500*0Sstevel@tonic-gate px_class_to_intr_weight(dev_info_t *rdip) 501*0Sstevel@tonic-gate { 502*0Sstevel@tonic-gate int32_t intr_weight; 503*0Sstevel@tonic-gate 504*0Sstevel@tonic-gate /* default weight is 0% */ 505*0Sstevel@tonic-gate intr_weight = px_class_to_val(rdip, 506*0Sstevel@tonic-gate "pci-class-intr-weights", px_default_intr_weight, 507*0Sstevel@tonic-gate sizeof (px_default_intr_weight) / sizeof (px_class_val_t), 0); 508*0Sstevel@tonic-gate 509*0Sstevel@tonic-gate /* range check the result */ 510*0Sstevel@tonic-gate if (intr_weight < 0) 511*0Sstevel@tonic-gate intr_weight = 0; 512*0Sstevel@tonic-gate if (intr_weight > 1000) 513*0Sstevel@tonic-gate intr_weight = 1000; 514*0Sstevel@tonic-gate 515*0Sstevel@tonic-gate return (intr_weight); 516*0Sstevel@tonic-gate } 517*0Sstevel@tonic-gate 518*0Sstevel@tonic-gate 519*0Sstevel@tonic-gate /* ARGSUSED */ 520*0Sstevel@tonic-gate int 521*0Sstevel@tonic-gate px_intx_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 522*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 523*0Sstevel@tonic-gate { 524*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 525*0Sstevel@tonic-gate ddi_ispec_t *ip = (ddi_ispec_t *)hdlp->ih_private; 526*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 527*0Sstevel@tonic-gate 528*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: dip=%x rdip=%x intr_op=%x " 529*0Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 530*0Sstevel@tonic-gate 531*0Sstevel@tonic-gate switch (intr_op) { 532*0Sstevel@tonic-gate case DDI_INTROP_GETCAP: 533*0Sstevel@tonic-gate ret = pci_intx_get_cap(rdip, (int *)result); 534*0Sstevel@tonic-gate break; 535*0Sstevel@tonic-gate case DDI_INTROP_SETCAP: 536*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_intx_ops: SetCap is not supported\n"); 537*0Sstevel@tonic-gate ret = DDI_ENOTSUP; 538*0Sstevel@tonic-gate break; 539*0Sstevel@tonic-gate case DDI_INTROP_ALLOC: 540*0Sstevel@tonic-gate *(int *)result = hdlp->ih_scratch1; 541*0Sstevel@tonic-gate break; 542*0Sstevel@tonic-gate case DDI_INTROP_FREE: 543*0Sstevel@tonic-gate break; 544*0Sstevel@tonic-gate case DDI_INTROP_GETPRI: 545*0Sstevel@tonic-gate *(int *)result = ip->is_pil ? 546*0Sstevel@tonic-gate ip->is_pil : px_class_to_pil(rdip); 547*0Sstevel@tonic-gate break; 548*0Sstevel@tonic-gate case DDI_INTROP_SETPRI: 549*0Sstevel@tonic-gate ip->is_pil = (*(int *)result); 550*0Sstevel@tonic-gate break; 551*0Sstevel@tonic-gate case DDI_INTROP_ADDISR: 552*0Sstevel@tonic-gate hdlp->ih_vector = *ip->is_intr; 553*0Sstevel@tonic-gate 554*0Sstevel@tonic-gate ret = px_add_intx_intr(dip, rdip, hdlp); 555*0Sstevel@tonic-gate break; 556*0Sstevel@tonic-gate case DDI_INTROP_REMISR: 557*0Sstevel@tonic-gate hdlp->ih_vector = *ip->is_intr; 558*0Sstevel@tonic-gate 559*0Sstevel@tonic-gate ret = px_rem_intx_intr(dip, rdip, hdlp); 560*0Sstevel@tonic-gate break; 561*0Sstevel@tonic-gate case DDI_INTROP_ENABLE: 562*0Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 563*0Sstevel@tonic-gate *ip->is_intr, PX_INTR_STATE_ENABLE); 564*0Sstevel@tonic-gate break; 565*0Sstevel@tonic-gate case DDI_INTROP_DISABLE: 566*0Sstevel@tonic-gate ret = px_ib_update_intr_state(px_p, rdip, hdlp->ih_inum, 567*0Sstevel@tonic-gate *ip->is_intr, PX_INTR_STATE_DISABLE); 568*0Sstevel@tonic-gate break; 569*0Sstevel@tonic-gate case DDI_INTROP_SETMASK: 570*0Sstevel@tonic-gate ret = pci_intx_set_mask(rdip); 571*0Sstevel@tonic-gate break; 572*0Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 573*0Sstevel@tonic-gate ret = pci_intx_clr_mask(rdip); 574*0Sstevel@tonic-gate break; 575*0Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 576*0Sstevel@tonic-gate ret = pci_intx_get_pending(rdip, (int *)result); 577*0Sstevel@tonic-gate break; 578*0Sstevel@tonic-gate case DDI_INTROP_NINTRS: 579*0Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 580*0Sstevel@tonic-gate *(int *)result = i_ddi_get_nintrs(rdip); 581*0Sstevel@tonic-gate break; 582*0Sstevel@tonic-gate case DDI_INTROP_SUPPORTED_TYPES: 583*0Sstevel@tonic-gate *(int *)result = DDI_INTR_TYPE_FIXED; 584*0Sstevel@tonic-gate break; 585*0Sstevel@tonic-gate default: 586*0Sstevel@tonic-gate ret = DDI_ENOTSUP; 587*0Sstevel@tonic-gate break; 588*0Sstevel@tonic-gate } 589*0Sstevel@tonic-gate 590*0Sstevel@tonic-gate return (ret); 591*0Sstevel@tonic-gate } 592*0Sstevel@tonic-gate 593*0Sstevel@tonic-gate /* ARGSUSED */ 594*0Sstevel@tonic-gate int 595*0Sstevel@tonic-gate px_msix_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 596*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, void *result) 597*0Sstevel@tonic-gate { 598*0Sstevel@tonic-gate px_t *px_p = DIP_TO_STATE(dip); 599*0Sstevel@tonic-gate px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 600*0Sstevel@tonic-gate msinum_t msi_num; 601*0Sstevel@tonic-gate msiqid_t msiq_id; 602*0Sstevel@tonic-gate uint_t nintrs; 603*0Sstevel@tonic-gate int i, ret = DDI_SUCCESS; 604*0Sstevel@tonic-gate 605*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: dip=%x rdip=%x intr_op=%x " 606*0Sstevel@tonic-gate "handle=%p\n", dip, rdip, intr_op, hdlp); 607*0Sstevel@tonic-gate 608*0Sstevel@tonic-gate switch (intr_op) { 609*0Sstevel@tonic-gate case DDI_INTROP_GETCAP: 610*0Sstevel@tonic-gate ret = pci_msi_get_cap(rdip, hdlp->ih_type, (int *)result); 611*0Sstevel@tonic-gate break; 612*0Sstevel@tonic-gate case DDI_INTROP_SETCAP: 613*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: SetCap is not supported\n"); 614*0Sstevel@tonic-gate ret = DDI_ENOTSUP; 615*0Sstevel@tonic-gate break; 616*0Sstevel@tonic-gate case DDI_INTROP_ALLOC: 617*0Sstevel@tonic-gate /* 618*0Sstevel@tonic-gate * We need to restrict this allocation in future 619*0Sstevel@tonic-gate * based on Resource Management policies. 620*0Sstevel@tonic-gate */ 621*0Sstevel@tonic-gate if ((ret = px_msi_alloc(px_p, rdip, hdlp->ih_inum, 622*0Sstevel@tonic-gate hdlp->ih_scratch1, hdlp->ih_scratch2, &msi_num, 623*0Sstevel@tonic-gate (int *)result)) != DDI_SUCCESS) { 624*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: MSI allocation " 625*0Sstevel@tonic-gate "failed, rdip 0x%p inum 0x%x count 0x%x\n", 626*0Sstevel@tonic-gate rdip, hdlp->ih_inum, hdlp->ih_scratch1); 627*0Sstevel@tonic-gate 628*0Sstevel@tonic-gate return (ret); 629*0Sstevel@tonic-gate } 630*0Sstevel@tonic-gate 631*0Sstevel@tonic-gate break; 632*0Sstevel@tonic-gate case DDI_INTROP_FREE: 633*0Sstevel@tonic-gate (void) pci_msi_disable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 634*0Sstevel@tonic-gate (void) pci_msi_unconfigure(rdip, hdlp->ih_type, hdlp->ih_inum); 635*0Sstevel@tonic-gate (void) px_msi_free(px_p, rdip, hdlp->ih_inum, 636*0Sstevel@tonic-gate hdlp->ih_scratch1); 637*0Sstevel@tonic-gate break; 638*0Sstevel@tonic-gate case DDI_INTROP_GETPRI: 639*0Sstevel@tonic-gate *(int *)result = hdlp->ih_pri ? 640*0Sstevel@tonic-gate hdlp->ih_pri : px_class_to_pil(rdip); 641*0Sstevel@tonic-gate break; 642*0Sstevel@tonic-gate case DDI_INTROP_SETPRI: 643*0Sstevel@tonic-gate break; 644*0Sstevel@tonic-gate case DDI_INTROP_ADDISR: 645*0Sstevel@tonic-gate if ((ret = px_msi_get_msinum(px_p, hdlp->ih_dip, 646*0Sstevel@tonic-gate hdlp->ih_inum, &msi_num)) != DDI_SUCCESS) 647*0Sstevel@tonic-gate return (ret); 648*0Sstevel@tonic-gate 649*0Sstevel@tonic-gate if ((ret = px_add_msiq_intr(dip, rdip, hdlp, 650*0Sstevel@tonic-gate MSI32_REC, msi_num, &msiq_id)) != DDI_SUCCESS) { 651*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: Add MSI handler " 652*0Sstevel@tonic-gate "failed, rdip 0x%p msi 0x%x\n", rdip, msi_num); 653*0Sstevel@tonic-gate return (ret); 654*0Sstevel@tonic-gate } 655*0Sstevel@tonic-gate 656*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: msiq used 0x%x\n", msiq_id); 657*0Sstevel@tonic-gate 658*0Sstevel@tonic-gate if ((ret = px_lib_msi_setmsiq(dip, msi_num, 659*0Sstevel@tonic-gate msiq_id, MSI32_TYPE)) != DDI_SUCCESS) { 660*0Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 661*0Sstevel@tonic-gate hdlp, MSI32_REC, msi_num, msiq_id); 662*0Sstevel@tonic-gate return (ret); 663*0Sstevel@tonic-gate } 664*0Sstevel@tonic-gate 665*0Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 666*0Sstevel@tonic-gate PCI_MSI_STATE_IDLE)) != DDI_SUCCESS) { 667*0Sstevel@tonic-gate (void) px_rem_msiq_intr(dip, rdip, 668*0Sstevel@tonic-gate hdlp, MSI32_REC, msi_num, msiq_id); 669*0Sstevel@tonic-gate return (ret); 670*0Sstevel@tonic-gate } 671*0Sstevel@tonic-gate 672*0Sstevel@tonic-gate hdlp->ih_vector = msi_num; 673*0Sstevel@tonic-gate break; 674*0Sstevel@tonic-gate case DDI_INTROP_DUPVEC: 675*0Sstevel@tonic-gate DBG(DBG_INTROPS, dip, "px_msix_ops: DupIsr is not supported\n"); 676*0Sstevel@tonic-gate ret = DDI_ENOTSUP; 677*0Sstevel@tonic-gate break; 678*0Sstevel@tonic-gate case DDI_INTROP_REMISR: 679*0Sstevel@tonic-gate msi_num = hdlp->ih_vector; 680*0Sstevel@tonic-gate 681*0Sstevel@tonic-gate if ((ret = px_lib_msi_getmsiq(dip, msi_num, 682*0Sstevel@tonic-gate &msiq_id)) != DDI_SUCCESS) 683*0Sstevel@tonic-gate return (ret); 684*0Sstevel@tonic-gate 685*0Sstevel@tonic-gate if ((ret = px_lib_msi_setstate(dip, msi_num, 686*0Sstevel@tonic-gate PCI_MSI_STATE_DELIVERED)) != DDI_SUCCESS) 687*0Sstevel@tonic-gate return (ret); 688*0Sstevel@tonic-gate 689*0Sstevel@tonic-gate ret = px_rem_msiq_intr(dip, rdip, 690*0Sstevel@tonic-gate hdlp, MSI32_REC, msi_num, msiq_id); 691*0Sstevel@tonic-gate 692*0Sstevel@tonic-gate hdlp->ih_vector = 0; 693*0Sstevel@tonic-gate break; 694*0Sstevel@tonic-gate case DDI_INTROP_ENABLE: 695*0Sstevel@tonic-gate msi_num = hdlp->ih_vector; 696*0Sstevel@tonic-gate 697*0Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 698*0Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 699*0Sstevel@tonic-gate return (ret); 700*0Sstevel@tonic-gate 701*0Sstevel@tonic-gate if (pci_is_msi_enabled(rdip, hdlp->ih_type) != DDI_SUCCESS) { 702*0Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 703*0Sstevel@tonic-gate 704*0Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 705*0Sstevel@tonic-gate nintrs, hdlp->ih_inum, msi_state_p->msi_addr32, 706*0Sstevel@tonic-gate msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 707*0Sstevel@tonic-gate return (ret); 708*0Sstevel@tonic-gate 709*0Sstevel@tonic-gate if ((ret = pci_msi_enable_mode(rdip, hdlp->ih_type, 710*0Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 711*0Sstevel@tonic-gate return (ret); 712*0Sstevel@tonic-gate } 713*0Sstevel@tonic-gate 714*0Sstevel@tonic-gate ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 715*0Sstevel@tonic-gate 716*0Sstevel@tonic-gate break; 717*0Sstevel@tonic-gate case DDI_INTROP_DISABLE: 718*0Sstevel@tonic-gate msi_num = hdlp->ih_vector; 719*0Sstevel@tonic-gate 720*0Sstevel@tonic-gate if ((ret = pci_msi_set_mask(rdip, hdlp->ih_type, 721*0Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 722*0Sstevel@tonic-gate return (ret); 723*0Sstevel@tonic-gate 724*0Sstevel@tonic-gate ret = px_lib_msi_setvalid(dip, msi_num, PCI_MSI_INVALID); 725*0Sstevel@tonic-gate break; 726*0Sstevel@tonic-gate case DDI_INTROP_BLOCKENABLE: 727*0Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 728*0Sstevel@tonic-gate msi_num = hdlp->ih_vector; 729*0Sstevel@tonic-gate 730*0Sstevel@tonic-gate if ((ret = pci_msi_configure(rdip, hdlp->ih_type, 731*0Sstevel@tonic-gate nintrs, hdlp->ih_inum, msi_state_p->msi_addr32, 732*0Sstevel@tonic-gate msi_num & ~(nintrs - 1))) != DDI_SUCCESS) 733*0Sstevel@tonic-gate return (ret); 734*0Sstevel@tonic-gate 735*0Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 736*0Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 737*0Sstevel@tonic-gate PCI_MSI_VALID)) != DDI_SUCCESS) 738*0Sstevel@tonic-gate return (ret); 739*0Sstevel@tonic-gate } 740*0Sstevel@tonic-gate 741*0Sstevel@tonic-gate ret = pci_msi_enable_mode(rdip, hdlp->ih_type, hdlp->ih_inum); 742*0Sstevel@tonic-gate break; 743*0Sstevel@tonic-gate case DDI_INTROP_BLOCKDISABLE: 744*0Sstevel@tonic-gate nintrs = i_ddi_intr_get_current_nintrs(hdlp->ih_dip); 745*0Sstevel@tonic-gate msi_num = hdlp->ih_vector; 746*0Sstevel@tonic-gate 747*0Sstevel@tonic-gate if ((ret = pci_msi_disable_mode(rdip, hdlp->ih_type, 748*0Sstevel@tonic-gate hdlp->ih_inum)) != DDI_SUCCESS) 749*0Sstevel@tonic-gate return (ret); 750*0Sstevel@tonic-gate 751*0Sstevel@tonic-gate for (i = 0; i < nintrs; i++, msi_num++) { 752*0Sstevel@tonic-gate if ((ret = px_lib_msi_setvalid(dip, msi_num, 753*0Sstevel@tonic-gate PCI_MSI_INVALID)) != DDI_SUCCESS) 754*0Sstevel@tonic-gate return (ret); 755*0Sstevel@tonic-gate } 756*0Sstevel@tonic-gate 757*0Sstevel@tonic-gate break; 758*0Sstevel@tonic-gate case DDI_INTROP_SETMASK: 759*0Sstevel@tonic-gate ret = pci_msi_set_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 760*0Sstevel@tonic-gate break; 761*0Sstevel@tonic-gate case DDI_INTROP_CLRMASK: 762*0Sstevel@tonic-gate ret = pci_msi_clr_mask(rdip, hdlp->ih_type, hdlp->ih_inum); 763*0Sstevel@tonic-gate break; 764*0Sstevel@tonic-gate case DDI_INTROP_GETPENDING: 765*0Sstevel@tonic-gate ret = pci_msi_get_pending(rdip, hdlp->ih_type, 766*0Sstevel@tonic-gate hdlp->ih_inum, (int *)result); 767*0Sstevel@tonic-gate break; 768*0Sstevel@tonic-gate case DDI_INTROP_NINTRS: 769*0Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 770*0Sstevel@tonic-gate break; 771*0Sstevel@tonic-gate case DDI_INTROP_NAVAIL: 772*0Sstevel@tonic-gate /* XXX - a new interface may be needed */ 773*0Sstevel@tonic-gate ret = pci_msi_get_nintrs(rdip, hdlp->ih_type, (int *)result); 774*0Sstevel@tonic-gate break; 775*0Sstevel@tonic-gate case DDI_INTROP_SUPPORTED_TYPES: 776*0Sstevel@tonic-gate ret = pci_msi_get_supported_type(rdip, (int *)result); 777*0Sstevel@tonic-gate break; 778*0Sstevel@tonic-gate default: 779*0Sstevel@tonic-gate ret = DDI_ENOTSUP; 780*0Sstevel@tonic-gate break; 781*0Sstevel@tonic-gate } 782*0Sstevel@tonic-gate 783*0Sstevel@tonic-gate return (ret); 784*0Sstevel@tonic-gate } 785*0Sstevel@tonic-gate 786*0Sstevel@tonic-gate int 787*0Sstevel@tonic-gate px_add_intx_intr(dev_info_t *dip, dev_info_t *rdip, 788*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 789*0Sstevel@tonic-gate { 790*0Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 791*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 792*0Sstevel@tonic-gate devino_t ino; 793*0Sstevel@tonic-gate px_ih_t *ih_p; 794*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 795*0Sstevel@tonic-gate int32_t weight; 796*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 797*0Sstevel@tonic-gate 798*0Sstevel@tonic-gate ino = hdlp->ih_vector; 799*0Sstevel@tonic-gate 800*0Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: rdip=%s%d ino=%x " 801*0Sstevel@tonic-gate "handler=%x arg1=%x arg2=%x\n", ddi_driver_name(rdip), 802*0Sstevel@tonic-gate ddi_get_instance(rdip), ino, hdlp->ih_cb_func, 803*0Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 804*0Sstevel@tonic-gate 805*0Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, 806*0Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, 0, 0); 807*0Sstevel@tonic-gate 808*0Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 809*0Sstevel@tonic-gate 810*0Sstevel@tonic-gate if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 811*0Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 812*0Sstevel@tonic-gate if (px_ib_ino_locate_intr(ino_p, rdip, intr_index, 0, 0)) { 813*0Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: " 814*0Sstevel@tonic-gate "dup intr #%d\n", intr_index); 815*0Sstevel@tonic-gate 816*0Sstevel@tonic-gate ret = DDI_FAILURE; 817*0Sstevel@tonic-gate goto fail1; 818*0Sstevel@tonic-gate } 819*0Sstevel@tonic-gate 820*0Sstevel@tonic-gate /* Save mondo value in hdlp */ 821*0Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 822*0Sstevel@tonic-gate 823*0Sstevel@tonic-gate if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 824*0Sstevel@tonic-gate != DDI_SUCCESS) 825*0Sstevel@tonic-gate goto fail1; 826*0Sstevel@tonic-gate } else { 827*0Sstevel@tonic-gate ino_p = px_ib_new_ino(ib_p, ino, ih_p); 828*0Sstevel@tonic-gate 829*0Sstevel@tonic-gate if (hdlp->ih_pri == 0) 830*0Sstevel@tonic-gate hdlp->ih_pri = px_class_to_pil(rdip); 831*0Sstevel@tonic-gate 832*0Sstevel@tonic-gate /* Save mondo value in hdlp */ 833*0Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 834*0Sstevel@tonic-gate 835*0Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: pil=0x%x mondo=0x%x\n", 836*0Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 837*0Sstevel@tonic-gate 838*0Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 839*0Sstevel@tonic-gate (ddi_intr_handler_t *)px_intx_intr, (caddr_t)ino_p, NULL); 840*0Sstevel@tonic-gate 841*0Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 842*0Sstevel@tonic-gate 843*0Sstevel@tonic-gate /* 844*0Sstevel@tonic-gate * Restore original interrupt handler 845*0Sstevel@tonic-gate * and arguments in interrupt handle. 846*0Sstevel@tonic-gate */ 847*0Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 848*0Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 849*0Sstevel@tonic-gate 850*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) 851*0Sstevel@tonic-gate goto fail2; 852*0Sstevel@tonic-gate 853*0Sstevel@tonic-gate /* Save the pil for this ino */ 854*0Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 855*0Sstevel@tonic-gate 856*0Sstevel@tonic-gate /* select cpu, saving it for sharing and removal */ 857*0Sstevel@tonic-gate ino_p->ino_cpuid = intr_dist_cpuid(); 858*0Sstevel@tonic-gate 859*0Sstevel@tonic-gate /* Enable interrupt */ 860*0Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino); 861*0Sstevel@tonic-gate } 862*0Sstevel@tonic-gate 863*0Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 864*0Sstevel@tonic-gate weight = px_class_to_intr_weight(rdip); 865*0Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 866*0Sstevel@tonic-gate 867*0Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 868*0Sstevel@tonic-gate if (ih_p->ih_ksp) 869*0Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 870*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 871*0Sstevel@tonic-gate 872*0Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: done! Interrupt 0x%x pil=%x\n", 873*0Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 874*0Sstevel@tonic-gate 875*0Sstevel@tonic-gate return (ret); 876*0Sstevel@tonic-gate fail2: 877*0Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 878*0Sstevel@tonic-gate fail1: 879*0Sstevel@tonic-gate if (ih_p->ih_config_handle) 880*0Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 881*0Sstevel@tonic-gate 882*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 883*0Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 884*0Sstevel@tonic-gate 885*0Sstevel@tonic-gate DBG(DBG_A_INTX, dip, "px_add_intx_intr: Failed! Interrupt 0x%x " 886*0Sstevel@tonic-gate "pil=%x\n", ino_p->ino_sysino, hdlp->ih_pri); 887*0Sstevel@tonic-gate 888*0Sstevel@tonic-gate return (ret); 889*0Sstevel@tonic-gate } 890*0Sstevel@tonic-gate 891*0Sstevel@tonic-gate int 892*0Sstevel@tonic-gate px_rem_intx_intr(dev_info_t *dip, dev_info_t *rdip, 893*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp) 894*0Sstevel@tonic-gate { 895*0Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 896*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 897*0Sstevel@tonic-gate devino_t ino; 898*0Sstevel@tonic-gate cpuid_t curr_cpu; 899*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 900*0Sstevel@tonic-gate px_ih_t *ih_p; 901*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 902*0Sstevel@tonic-gate 903*0Sstevel@tonic-gate ino = hdlp->ih_vector; 904*0Sstevel@tonic-gate 905*0Sstevel@tonic-gate DBG(DBG_R_INTX, dip, "px_rem_intx_intr: rdip=%s%d ino=%x\n", 906*0Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), ino); 907*0Sstevel@tonic-gate 908*0Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 909*0Sstevel@tonic-gate 910*0Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 911*0Sstevel@tonic-gate ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 0, 0); 912*0Sstevel@tonic-gate 913*0Sstevel@tonic-gate /* Get the current cpu */ 914*0Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 915*0Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 916*0Sstevel@tonic-gate goto fail; 917*0Sstevel@tonic-gate 918*0Sstevel@tonic-gate if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 919*0Sstevel@tonic-gate goto fail; 920*0Sstevel@tonic-gate 921*0Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 922*0Sstevel@tonic-gate 923*0Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 924*0Sstevel@tonic-gate if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 925*0Sstevel@tonic-gate INTR_DELIVERED_STATE)) != DDI_SUCCESS) 926*0Sstevel@tonic-gate goto fail; 927*0Sstevel@tonic-gate 928*0Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 929*0Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 930*0Sstevel@tonic-gate 931*0Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 932*0Sstevel@tonic-gate kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 933*0Sstevel@tonic-gate } else { 934*0Sstevel@tonic-gate /* Re-enable interrupt only if mapping regsiter still shared */ 935*0Sstevel@tonic-gate if ((ret = px_lib_intr_settarget(px_p->px_dip, 936*0Sstevel@tonic-gate ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS) 937*0Sstevel@tonic-gate goto fail; 938*0Sstevel@tonic-gate 939*0Sstevel@tonic-gate ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino, 940*0Sstevel@tonic-gate INTR_VALID); 941*0Sstevel@tonic-gate } 942*0Sstevel@tonic-gate 943*0Sstevel@tonic-gate fail: 944*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 945*0Sstevel@tonic-gate return (ret); 946*0Sstevel@tonic-gate } 947*0Sstevel@tonic-gate 948*0Sstevel@tonic-gate int 949*0Sstevel@tonic-gate px_add_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 950*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 951*0Sstevel@tonic-gate msgcode_t msg_code, msiqid_t *msiq_id_p) 952*0Sstevel@tonic-gate { 953*0Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 954*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 955*0Sstevel@tonic-gate px_msiq_state_t *msiq_state_p = &ib_p->ib_msiq_state; 956*0Sstevel@tonic-gate devino_t ino; 957*0Sstevel@tonic-gate px_ih_t *ih_p; 958*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 959*0Sstevel@tonic-gate int32_t weight; 960*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 961*0Sstevel@tonic-gate 962*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: rdip=%s%d handler=%x " 963*0Sstevel@tonic-gate "arg1=%x arg2=%x\n", ddi_driver_name(rdip), ddi_get_instance(rdip), 964*0Sstevel@tonic-gate hdlp->ih_cb_func, hdlp->ih_cb_arg1, hdlp->ih_cb_arg2); 965*0Sstevel@tonic-gate 966*0Sstevel@tonic-gate if ((ret = px_msiq_alloc(px_p, rec_type, msiq_id_p)) != DDI_SUCCESS) { 967*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 968*0Sstevel@tonic-gate "msiq allocation failed\n"); 969*0Sstevel@tonic-gate return (ret); 970*0Sstevel@tonic-gate } 971*0Sstevel@tonic-gate 972*0Sstevel@tonic-gate ino = px_msiqid_to_devino(px_p, *msiq_id_p); 973*0Sstevel@tonic-gate 974*0Sstevel@tonic-gate ih_p = px_ib_alloc_ih(rdip, hdlp->ih_inum, hdlp->ih_cb_func, 975*0Sstevel@tonic-gate hdlp->ih_cb_arg1, hdlp->ih_cb_arg2, rec_type, msg_code); 976*0Sstevel@tonic-gate 977*0Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 978*0Sstevel@tonic-gate 979*0Sstevel@tonic-gate if (ino_p = px_ib_locate_ino(ib_p, ino)) { /* sharing ino */ 980*0Sstevel@tonic-gate uint32_t intr_index = hdlp->ih_inum; 981*0Sstevel@tonic-gate if (px_ib_ino_locate_intr(ino_p, rdip, 982*0Sstevel@tonic-gate intr_index, rec_type, msg_code)) { 983*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: " 984*0Sstevel@tonic-gate "dup intr #%d\n", intr_index); 985*0Sstevel@tonic-gate 986*0Sstevel@tonic-gate ret = DDI_FAILURE; 987*0Sstevel@tonic-gate goto fail1; 988*0Sstevel@tonic-gate } 989*0Sstevel@tonic-gate 990*0Sstevel@tonic-gate if ((ret = px_ib_ino_add_intr(px_p, ino_p, ih_p)) 991*0Sstevel@tonic-gate != DDI_SUCCESS) 992*0Sstevel@tonic-gate goto fail1; 993*0Sstevel@tonic-gate } else { 994*0Sstevel@tonic-gate ino_p = px_ib_new_ino(ib_p, ino, ih_p); 995*0Sstevel@tonic-gate 996*0Sstevel@tonic-gate ino_p->ino_msiq_p = msiq_state_p->msiq_p + 997*0Sstevel@tonic-gate (*msiq_id_p - msiq_state_p->msiq_1st_msiq_id); 998*0Sstevel@tonic-gate 999*0Sstevel@tonic-gate if (hdlp->ih_pri == 0) 1000*0Sstevel@tonic-gate hdlp->ih_pri = px_class_to_pil(rdip); 1001*0Sstevel@tonic-gate 1002*0Sstevel@tonic-gate /* Save mondo value in hdlp */ 1003*0Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 1004*0Sstevel@tonic-gate 1005*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: pil=0x%x mondo=0x%x\n", 1006*0Sstevel@tonic-gate hdlp->ih_pri, hdlp->ih_vector); 1007*0Sstevel@tonic-gate 1008*0Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, 1009*0Sstevel@tonic-gate (ddi_intr_handler_t *)px_msiq_intr, (caddr_t)ino_p, NULL); 1010*0Sstevel@tonic-gate 1011*0Sstevel@tonic-gate ret = i_ddi_add_ivintr(hdlp); 1012*0Sstevel@tonic-gate 1013*0Sstevel@tonic-gate /* 1014*0Sstevel@tonic-gate * Restore original interrupt handler 1015*0Sstevel@tonic-gate * and arguments in interrupt handle. 1016*0Sstevel@tonic-gate */ 1017*0Sstevel@tonic-gate DDI_INTR_ASSIGN_HDLR_N_ARGS(hdlp, ih_p->ih_handler, 1018*0Sstevel@tonic-gate ih_p->ih_handler_arg1, ih_p->ih_handler_arg2); 1019*0Sstevel@tonic-gate 1020*0Sstevel@tonic-gate if (ret != DDI_SUCCESS) 1021*0Sstevel@tonic-gate goto fail2; 1022*0Sstevel@tonic-gate 1023*0Sstevel@tonic-gate /* Save the pil for this ino */ 1024*0Sstevel@tonic-gate ino_p->ino_pil = hdlp->ih_pri; 1025*0Sstevel@tonic-gate 1026*0Sstevel@tonic-gate /* Enable MSIQ */ 1027*0Sstevel@tonic-gate px_lib_msiq_setstate(dip, *msiq_id_p, PCI_MSIQ_STATE_IDLE); 1028*0Sstevel@tonic-gate px_lib_msiq_setvalid(dip, *msiq_id_p, PCI_MSIQ_VALID); 1029*0Sstevel@tonic-gate 1030*0Sstevel@tonic-gate /* select cpu, saving it for sharing and removal */ 1031*0Sstevel@tonic-gate ino_p->ino_cpuid = intr_dist_cpuid(); 1032*0Sstevel@tonic-gate 1033*0Sstevel@tonic-gate /* Enable interrupt */ 1034*0Sstevel@tonic-gate px_ib_intr_enable(px_p, ino_p->ino_cpuid, ino_p->ino_ino); 1035*0Sstevel@tonic-gate } 1036*0Sstevel@tonic-gate 1037*0Sstevel@tonic-gate /* add weight to the cpu that we are already targeting */ 1038*0Sstevel@tonic-gate weight = px_class_to_intr_weight(rdip); 1039*0Sstevel@tonic-gate intr_dist_cpuid_add_device_weight(ino_p->ino_cpuid, rdip, weight); 1040*0Sstevel@tonic-gate 1041*0Sstevel@tonic-gate ih_p->ih_ino_p = ino_p; 1042*0Sstevel@tonic-gate if (ih_p->ih_ksp) 1043*0Sstevel@tonic-gate kstat_install(ih_p->ih_ksp); 1044*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 1045*0Sstevel@tonic-gate 1046*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: done! Interrupt 0x%x pil=%x\n", 1047*0Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 1048*0Sstevel@tonic-gate 1049*0Sstevel@tonic-gate return (ret); 1050*0Sstevel@tonic-gate fail2: 1051*0Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 1052*0Sstevel@tonic-gate fail1: 1053*0Sstevel@tonic-gate if (ih_p->ih_config_handle) 1054*0Sstevel@tonic-gate pci_config_teardown(&ih_p->ih_config_handle); 1055*0Sstevel@tonic-gate 1056*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 1057*0Sstevel@tonic-gate kmem_free(ih_p, sizeof (px_ih_t)); 1058*0Sstevel@tonic-gate 1059*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_add_msiq_intr: Failed! Interrupt 0x%x pil=%x\n", 1060*0Sstevel@tonic-gate ino_p->ino_sysino, hdlp->ih_pri); 1061*0Sstevel@tonic-gate 1062*0Sstevel@tonic-gate return (ret); 1063*0Sstevel@tonic-gate } 1064*0Sstevel@tonic-gate 1065*0Sstevel@tonic-gate int 1066*0Sstevel@tonic-gate px_rem_msiq_intr(dev_info_t *dip, dev_info_t *rdip, 1067*0Sstevel@tonic-gate ddi_intr_handle_impl_t *hdlp, msiq_rec_type_t rec_type, 1068*0Sstevel@tonic-gate msgcode_t msg_code, msiqid_t msiq_id) 1069*0Sstevel@tonic-gate { 1070*0Sstevel@tonic-gate px_t *px_p = INST_TO_STATE(ddi_get_instance(dip)); 1071*0Sstevel@tonic-gate px_ib_t *ib_p = px_p->px_ib_p; 1072*0Sstevel@tonic-gate devino_t ino = px_msiqid_to_devino(px_p, msiq_id); 1073*0Sstevel@tonic-gate cpuid_t curr_cpu; 1074*0Sstevel@tonic-gate px_ib_ino_info_t *ino_p; 1075*0Sstevel@tonic-gate px_ih_t *ih_p; 1076*0Sstevel@tonic-gate int ret = DDI_SUCCESS; 1077*0Sstevel@tonic-gate 1078*0Sstevel@tonic-gate DBG(DBG_MSIQ, dip, "px_rem_msiq_intr: rdip=%s%d msiq_id=%x ino=%x\n", 1079*0Sstevel@tonic-gate ddi_driver_name(rdip), ddi_get_instance(rdip), msiq_id, ino); 1080*0Sstevel@tonic-gate 1081*0Sstevel@tonic-gate mutex_enter(&ib_p->ib_ino_lst_mutex); 1082*0Sstevel@tonic-gate 1083*0Sstevel@tonic-gate ino_p = px_ib_locate_ino(ib_p, ino); 1084*0Sstevel@tonic-gate ih_p = px_ib_ino_locate_intr(ino_p, rdip, hdlp->ih_inum, 1085*0Sstevel@tonic-gate rec_type, msg_code); 1086*0Sstevel@tonic-gate 1087*0Sstevel@tonic-gate /* Get the current cpu */ 1088*0Sstevel@tonic-gate if ((ret = px_lib_intr_gettarget(px_p->px_dip, ino_p->ino_sysino, 1089*0Sstevel@tonic-gate &curr_cpu)) != DDI_SUCCESS) 1090*0Sstevel@tonic-gate goto fail; 1091*0Sstevel@tonic-gate 1092*0Sstevel@tonic-gate if ((ret = px_ib_ino_rem_intr(px_p, ino_p, ih_p)) != DDI_SUCCESS) 1093*0Sstevel@tonic-gate goto fail; 1094*0Sstevel@tonic-gate 1095*0Sstevel@tonic-gate intr_dist_cpuid_rem_device_weight(ino_p->ino_cpuid, rdip); 1096*0Sstevel@tonic-gate 1097*0Sstevel@tonic-gate if (ino_p->ino_ih_size == 0) { 1098*0Sstevel@tonic-gate if ((ret = px_lib_intr_setstate(px_p->px_dip, ino_p->ino_sysino, 1099*0Sstevel@tonic-gate INTR_DELIVERED_STATE)) != DDI_SUCCESS) 1100*0Sstevel@tonic-gate goto fail; 1101*0Sstevel@tonic-gate 1102*0Sstevel@tonic-gate px_lib_msiq_setvalid(dip, px_devino_to_msiqid(px_p, ino), 1103*0Sstevel@tonic-gate PCI_MSIQ_INVALID); 1104*0Sstevel@tonic-gate 1105*0Sstevel@tonic-gate hdlp->ih_vector = ino_p->ino_sysino; 1106*0Sstevel@tonic-gate i_ddi_rem_ivintr(hdlp); 1107*0Sstevel@tonic-gate 1108*0Sstevel@tonic-gate px_ib_delete_ino(ib_p, ino_p); 1109*0Sstevel@tonic-gate 1110*0Sstevel@tonic-gate (void) px_msiq_free(px_p, msiq_id); 1111*0Sstevel@tonic-gate kmem_free(ino_p, sizeof (px_ib_ino_info_t)); 1112*0Sstevel@tonic-gate } else { 1113*0Sstevel@tonic-gate /* Re-enable interrupt only if mapping regsiter still shared */ 1114*0Sstevel@tonic-gate if ((ret = px_lib_intr_settarget(px_p->px_dip, 1115*0Sstevel@tonic-gate ino_p->ino_sysino, curr_cpu)) != DDI_SUCCESS) 1116*0Sstevel@tonic-gate goto fail; 1117*0Sstevel@tonic-gate 1118*0Sstevel@tonic-gate ret = px_lib_intr_setvalid(px_p->px_dip, ino_p->ino_sysino, 1119*0Sstevel@tonic-gate INTR_VALID); 1120*0Sstevel@tonic-gate } 1121*0Sstevel@tonic-gate 1122*0Sstevel@tonic-gate fail: 1123*0Sstevel@tonic-gate mutex_exit(&ib_p->ib_ino_lst_mutex); 1124*0Sstevel@tonic-gate return (ret); 1125*0Sstevel@tonic-gate } 1126