xref: /onnv-gate/usr/src/uts/sun/sys/scsi/adapters/fasreg.h (revision 0:68f95e015346)
1*0Sstevel@tonic-gate /*
2*0Sstevel@tonic-gate  * CDDL HEADER START
3*0Sstevel@tonic-gate  *
4*0Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
5*0Sstevel@tonic-gate  * Common Development and Distribution License, Version 1.0 only
6*0Sstevel@tonic-gate  * (the "License").  You may not use this file except in compliance
7*0Sstevel@tonic-gate  * with the License.
8*0Sstevel@tonic-gate  *
9*0Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*0Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
11*0Sstevel@tonic-gate  * See the License for the specific language governing permissions
12*0Sstevel@tonic-gate  * and limitations under the License.
13*0Sstevel@tonic-gate  *
14*0Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
15*0Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*0Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
17*0Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
18*0Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
19*0Sstevel@tonic-gate  *
20*0Sstevel@tonic-gate  * CDDL HEADER END
21*0Sstevel@tonic-gate  */
22*0Sstevel@tonic-gate /*
23*0Sstevel@tonic-gate  * Copyright (c) 1996-1998 by Sun Microsystems, Inc.
24*0Sstevel@tonic-gate  * All rights reserved.
25*0Sstevel@tonic-gate  */
26*0Sstevel@tonic-gate 
27*0Sstevel@tonic-gate #ifndef	_SYS_SCSI_ADAPTERS_FASREG_H
28*0Sstevel@tonic-gate #define	_SYS_SCSI_ADAPTERS_FASREG_H
29*0Sstevel@tonic-gate 
30*0Sstevel@tonic-gate #pragma ident	"%Z%%M%	%I%	%E% SMI"
31*0Sstevel@tonic-gate 
32*0Sstevel@tonic-gate #include <sys/note.h>
33*0Sstevel@tonic-gate 
34*0Sstevel@tonic-gate #ifdef	__cplusplus
35*0Sstevel@tonic-gate extern "C" {
36*0Sstevel@tonic-gate #endif
37*0Sstevel@tonic-gate 
38*0Sstevel@tonic-gate /*
39*0Sstevel@tonic-gate  * FAS register	definitions.
40*0Sstevel@tonic-gate  */
41*0Sstevel@tonic-gate 
42*0Sstevel@tonic-gate /*
43*0Sstevel@tonic-gate  * All current Sun implementations use the following layout.
44*0Sstevel@tonic-gate  * That	is, the	FAS registers are always byte-wide, but	are
45*0Sstevel@tonic-gate  * accessed longwords apart. Notice also that the byte-ordering
46*0Sstevel@tonic-gate  * is big-endian.
47*0Sstevel@tonic-gate  */
48*0Sstevel@tonic-gate 
49*0Sstevel@tonic-gate struct fasreg {
50*0Sstevel@tonic-gate 	uint8_t	fas_xcnt_lo;		/* RW: transfer	counter	(low byte) */
51*0Sstevel@tonic-gate 					uint8_t _pad1, _pad2, _pad3;
52*0Sstevel@tonic-gate 
53*0Sstevel@tonic-gate 	uint8_t	fas_xcnt_mid;		/* RW: transfer	counter	(mid byte) */
54*0Sstevel@tonic-gate 					uint8_t _pad5, _pad6, _pad7;
55*0Sstevel@tonic-gate 
56*0Sstevel@tonic-gate 	uint8_t	fas_fifo_data;		/* RW: fifo data buffer	*/
57*0Sstevel@tonic-gate 					uint8_t _pad9, _pad10, _pad11;
58*0Sstevel@tonic-gate 
59*0Sstevel@tonic-gate 	uint8_t	fas_cmd;		/* RW: command register	*/
60*0Sstevel@tonic-gate 					uint8_t _pad13, _pad14, _pad15;
61*0Sstevel@tonic-gate 
62*0Sstevel@tonic-gate 	uint8_t	fas_stat;		/* R: status register */
63*0Sstevel@tonic-gate #define	fas_busid	fas_stat	/* W: bus id for sel/resel */
64*0Sstevel@tonic-gate 					uint8_t _pad17, _pad18, _pad19;
65*0Sstevel@tonic-gate 
66*0Sstevel@tonic-gate 
67*0Sstevel@tonic-gate 	uint8_t	fas_intr;		/* R: interrupt	status register	*/
68*0Sstevel@tonic-gate #define	fas_timeout	fas_intr	/* W: sel/resel	timeout	*/
69*0Sstevel@tonic-gate 					uint8_t _pad21, _pad22, _pad23;
70*0Sstevel@tonic-gate 
71*0Sstevel@tonic-gate 
72*0Sstevel@tonic-gate 	uint8_t	fas_step;		/* R: sequence step register */
73*0Sstevel@tonic-gate #define	fas_sync_period	fas_step	/* W: synchronous period */
74*0Sstevel@tonic-gate 					uint8_t _pad25, _pad26, _pad27;
75*0Sstevel@tonic-gate 
76*0Sstevel@tonic-gate 
77*0Sstevel@tonic-gate 	uint8_t	fas_fifo_flag;		/* R: fifo flag	register */
78*0Sstevel@tonic-gate #define	fas_sync_offset	fas_fifo_flag	/* W: synchronous offset */
79*0Sstevel@tonic-gate 					uint8_t _pad29, _pad30, _pad31;
80*0Sstevel@tonic-gate 
81*0Sstevel@tonic-gate 
82*0Sstevel@tonic-gate 	uint8_t	fas_conf;		/* RW: configuration register */
83*0Sstevel@tonic-gate 					uint8_t _pad33, _pad34, _pad35;
84*0Sstevel@tonic-gate 
85*0Sstevel@tonic-gate 
86*0Sstevel@tonic-gate 	uint8_t	fas_clock_conv;		/* W: clock conversion register	*/
87*0Sstevel@tonic-gate 					uint8_t _pad37, _pad38, _pad39;
88*0Sstevel@tonic-gate #define	fas_stat2	fas_clock_conv
89*0Sstevel@tonic-gate 
90*0Sstevel@tonic-gate 
91*0Sstevel@tonic-gate 	uint8_t	fas_test;		/* RW: test register */
92*0Sstevel@tonic-gate 					uint8_t _pad41, _pad42, _pad43;
93*0Sstevel@tonic-gate #define	fas_conf4	fas_test
94*0Sstevel@tonic-gate 
95*0Sstevel@tonic-gate 
96*0Sstevel@tonic-gate 	uint8_t	fas_conf2;		/* FAS-II configuration	register */
97*0Sstevel@tonic-gate 					uint8_t _pad45, _pad46, _pad47;
98*0Sstevel@tonic-gate 
99*0Sstevel@tonic-gate 
100*0Sstevel@tonic-gate 	uint8_t	fas_conf3;		/* FAS-III configuration register */
101*0Sstevel@tonic-gate 					uint8_t _pad49, _pad50, _pad51;
102*0Sstevel@tonic-gate 					uint8_t _pad_reserved[4];
103*0Sstevel@tonic-gate 
104*0Sstevel@tonic-gate 	uint8_t	fas_recmd_lo;		/* RW: fifo recmd counter lo */
105*0Sstevel@tonic-gate #define	fas_id_code fas_recmd_lo	/* R: part-unique id code */
106*0Sstevel@tonic-gate 					uint8_t _pad52, _pad53, _pad54;
107*0Sstevel@tonic-gate 
108*0Sstevel@tonic-gate 	uint8_t	fas_recmd_hi;		/* RW: fifo recmd counter lo */
109*0Sstevel@tonic-gate 					uint8_t _pad55, _pad56, _pad57;
110*0Sstevel@tonic-gate };
111*0Sstevel@tonic-gate 
112*0Sstevel@tonic-gate 
113*0Sstevel@tonic-gate /*
114*0Sstevel@tonic-gate  * FAS command register	definitions
115*0Sstevel@tonic-gate  */
116*0Sstevel@tonic-gate 
117*0Sstevel@tonic-gate /*
118*0Sstevel@tonic-gate  * These commands may be used at any time with the FAS chip.
119*0Sstevel@tonic-gate  * None	generate an interrupt, per se, although	if you have
120*0Sstevel@tonic-gate  * enabled detection of	SCSI reset in setting the configuration
121*0Sstevel@tonic-gate  * register, a CMD_RESET_SCSI will generate an interrupt.
122*0Sstevel@tonic-gate  * Therefore, it is recommended	that if	you use	the CMD_RESET_SCSI
123*0Sstevel@tonic-gate  * command, you	at least temporarily disable recognition of
124*0Sstevel@tonic-gate  * SCSI	reset in the configuration register.
125*0Sstevel@tonic-gate  */
126*0Sstevel@tonic-gate #define	CMD_NOP		0x0
127*0Sstevel@tonic-gate #define	CMD_FLUSH	0x1
128*0Sstevel@tonic-gate #define	CMD_RESET_FAS	0x2
129*0Sstevel@tonic-gate #define	CMD_RESET_SCSI	0x3
130*0Sstevel@tonic-gate 
131*0Sstevel@tonic-gate /*
132*0Sstevel@tonic-gate  * These commands will only work if the	FAS is in the
133*0Sstevel@tonic-gate  * 'disconnected' state:
134*0Sstevel@tonic-gate  */
135*0Sstevel@tonic-gate #define	CMD_RESEL_SEQ	0x40
136*0Sstevel@tonic-gate #define	CMD_SEL_NOATN	0x41
137*0Sstevel@tonic-gate #define	CMD_SEL_ATN	0x42
138*0Sstevel@tonic-gate #define	CMD_SEL_STOP	0x43
139*0Sstevel@tonic-gate #define	CMD_EN_RESEL	0x44	/* (no interrupt generated) */
140*0Sstevel@tonic-gate #define	CMD_DIS_RESEL	0x45
141*0Sstevel@tonic-gate #define	CMD_SEL_ATN3	0x46
142*0Sstevel@tonic-gate 
143*0Sstevel@tonic-gate /*
144*0Sstevel@tonic-gate  * These commands will only work if the	FAS is connected as
145*0Sstevel@tonic-gate  * an initiator	to a target:
146*0Sstevel@tonic-gate  */
147*0Sstevel@tonic-gate #define	CMD_TRAN_INFO	0x10
148*0Sstevel@tonic-gate #define	CMD_COMP_SEQ	0x11
149*0Sstevel@tonic-gate #define	CMD_MSG_ACPT	0x12
150*0Sstevel@tonic-gate #define	CMD_TRAN_PAD	0x18
151*0Sstevel@tonic-gate #define	CMD_SET_ATN	0x1a	/* (no interrupt generated) */
152*0Sstevel@tonic-gate #define	CMD_CLR_ATN	0x1b	/* (no interrupt generated) */
153*0Sstevel@tonic-gate 
154*0Sstevel@tonic-gate /*
155*0Sstevel@tonic-gate  * These commands will only work if the	FAS is connected as
156*0Sstevel@tonic-gate  * a target to an initiator:
157*0Sstevel@tonic-gate  */
158*0Sstevel@tonic-gate #define	CMD_DISCONNECT	0x27	/* (no interrupt generated) */
159*0Sstevel@tonic-gate 
160*0Sstevel@tonic-gate /*
161*0Sstevel@tonic-gate  * DMA enable bit
162*0Sstevel@tonic-gate  */
163*0Sstevel@tonic-gate #define	CMD_DMA		0x80
164*0Sstevel@tonic-gate 
165*0Sstevel@tonic-gate /*
166*0Sstevel@tonic-gate  * FAS fifo register definitions (read only)
167*0Sstevel@tonic-gate  */
168*0Sstevel@tonic-gate #define	FIFOSIZE		16
169*0Sstevel@tonic-gate #define	MAX_FIFO_FLAG		(FIFOSIZE-1)
170*0Sstevel@tonic-gate #define	FAS_FIFO_ONZ		0x20
171*0Sstevel@tonic-gate #define	FIFO_CNT_MASK		0x1f
172*0Sstevel@tonic-gate 
173*0Sstevel@tonic-gate /*
174*0Sstevel@tonic-gate  * FAS status register definitions (read only)
175*0Sstevel@tonic-gate  */
176*0Sstevel@tonic-gate #define	FAS_STAT_IPEND	0x80	/* interrupt pending */
177*0Sstevel@tonic-gate #define	FAS_STAT_GERR	0x40	/* gross error */
178*0Sstevel@tonic-gate #define	FAS_STAT_PERR	0x20	/* parity error	*/
179*0Sstevel@tonic-gate #define	FAS_STAT_XZERO	0x10	/* transfer counter zero */
180*0Sstevel@tonic-gate #define	FAS_STAT_XCMP	0x8	/* transfer completed (target mode only) */
181*0Sstevel@tonic-gate #define	FAS_STAT_MSG	0x4	/* scsi	phase bit: MSG */
182*0Sstevel@tonic-gate #define	FAS_STAT_CD	0x2	/* scsi	phase bit: CD */
183*0Sstevel@tonic-gate #define	FAS_STAT_IO	0x1	/* scsi	phase bit: IO */
184*0Sstevel@tonic-gate 
185*0Sstevel@tonic-gate #define	FAS_STAT_BITS	\
186*0Sstevel@tonic-gate 	"\20\10IPND\07GERR\06PERR\05XZERO\04XCMP\03MSG\02CD\01IO"
187*0Sstevel@tonic-gate 
188*0Sstevel@tonic-gate /*
189*0Sstevel@tonic-gate  * settings of status to reflect different information transfer	phases
190*0Sstevel@tonic-gate  */
191*0Sstevel@tonic-gate #define	FAS_PHASE_MASK		(FAS_STAT_MSG |	FAS_STAT_CD | FAS_STAT_IO)
192*0Sstevel@tonic-gate #define	FAS_PHASE_DATA_OUT	0
193*0Sstevel@tonic-gate #define	FAS_PHASE_DATA_IN	(FAS_STAT_IO)
194*0Sstevel@tonic-gate #define	FAS_PHASE_COMMAND	(FAS_STAT_CD)
195*0Sstevel@tonic-gate #define	FAS_PHASE_STATUS	(FAS_STAT_CD | FAS_STAT_IO)
196*0Sstevel@tonic-gate #define	FAS_PHASE_MSG_OUT	(FAS_STAT_MSG |	FAS_STAT_CD)
197*0Sstevel@tonic-gate #define	FAS_PHASE_MSG_IN	(FAS_STAT_MSG |	FAS_STAT_CD | FAS_STAT_IO)
198*0Sstevel@tonic-gate 
199*0Sstevel@tonic-gate /*
200*0Sstevel@tonic-gate  * FAS interrupt status	register definitions (read only)
201*0Sstevel@tonic-gate  */
202*0Sstevel@tonic-gate 
203*0Sstevel@tonic-gate #define	FAS_INT_RESET	0x80	/* SCSI	reset detected */
204*0Sstevel@tonic-gate #define	FAS_INT_ILLEGAL	0x40	/* illegal cmd */
205*0Sstevel@tonic-gate #define	FAS_INT_DISCON	0x20	/* disconnect */
206*0Sstevel@tonic-gate #define	FAS_INT_BUS	0x10	/* bus service */
207*0Sstevel@tonic-gate #define	FAS_INT_FCMP	0x8	/* function completed */
208*0Sstevel@tonic-gate #define	FAS_INT_RESEL	0x4	/* reselected */
209*0Sstevel@tonic-gate #define	FAS_INT_SELATN	0x2	/* selected with ATN */
210*0Sstevel@tonic-gate #define	FAS_INT_SEL	0x1	/* selected without ATN	*/
211*0Sstevel@tonic-gate 
212*0Sstevel@tonic-gate #define	FAS_INT_BITS	\
213*0Sstevel@tonic-gate 	"\20\10RST\07ILL\06DISC\05BUS\04FCMP\03RESEL\02SATN\01SEL"
214*0Sstevel@tonic-gate 
215*0Sstevel@tonic-gate /*
216*0Sstevel@tonic-gate  * FAS step register- only the least significant 3 bits	are valid
217*0Sstevel@tonic-gate  */
218*0Sstevel@tonic-gate #define	FAS_STEP_MASK	0x7
219*0Sstevel@tonic-gate 
220*0Sstevel@tonic-gate #define	FAS_STEP_ARBSEL	0	/* Arbitration and select completed. */
221*0Sstevel@tonic-gate 				/* Not MESSAGE OUT phase. ATN* asserted. */
222*0Sstevel@tonic-gate 
223*0Sstevel@tonic-gate #define	FAS_STEP_SENTID	1	/* Sent	one message byte. ATN* asserted. */
224*0Sstevel@tonic-gate 				/* (SELECT AND STOP command only). */
225*0Sstevel@tonic-gate 
226*0Sstevel@tonic-gate #define	FAS_STEP_NOTCMD	2	/* For SELECT WITH ATN command:	*/
227*0Sstevel@tonic-gate 				/*	Sent one message byte. ATN* off. */
228*0Sstevel@tonic-gate 				/*	Not COMMAND phase. */
229*0Sstevel@tonic-gate 				/* For SELECT WITHOUT ATN command: */
230*0Sstevel@tonic-gate 				/*	Not COMMAND phase. */
231*0Sstevel@tonic-gate 				/* For SELECT WITH ATN3	command: */
232*0Sstevel@tonic-gate 				/*	Sent one to three message bytes. */
233*0Sstevel@tonic-gate 				/*	Stopped	due to unexpected phase	*/
234*0Sstevel@tonic-gate 				/*	change.	If third message byte */
235*0Sstevel@tonic-gate 				/*	not sent, ATN* asserted.  */
236*0Sstevel@tonic-gate 
237*0Sstevel@tonic-gate #define	FAS_STEP_PCMD	3	/* Not all of command bytes transferred	*/
238*0Sstevel@tonic-gate 				/* due to premature phase change. */
239*0Sstevel@tonic-gate 
240*0Sstevel@tonic-gate #define	FAS_STEP_DONE	4	/* Complete sequence. */
241*0Sstevel@tonic-gate 
242*0Sstevel@tonic-gate /*
243*0Sstevel@tonic-gate  * FAS configuration register definitions (read/write)
244*0Sstevel@tonic-gate  */
245*0Sstevel@tonic-gate #define	FAS_CONF_SLOWMODE	0x80	/* slow	cable mode */
246*0Sstevel@tonic-gate #define	FAS_CONF_DISRINT	0x40	/* disable reset int */
247*0Sstevel@tonic-gate #define	FAS_CONF_PARTEST	0x20	/* parity test mode */
248*0Sstevel@tonic-gate #define	FAS_CONF_PAREN		0x10	/* enable parity */
249*0Sstevel@tonic-gate #define	FAS_CONF_CHIPTEST	0x8	/* chip	test mode */
250*0Sstevel@tonic-gate #define	FAS_CONF_BUSID		0x7	/* last	3 bits to be host id */
251*0Sstevel@tonic-gate 
252*0Sstevel@tonic-gate #define	DEFAULT_HOSTID		7
253*0Sstevel@tonic-gate 
254*0Sstevel@tonic-gate /*
255*0Sstevel@tonic-gate  * FAS test register definitions (read/write)
256*0Sstevel@tonic-gate  */
257*0Sstevel@tonic-gate #define	FAS_TEST_TGT		0x1	/* target test mode */
258*0Sstevel@tonic-gate #define	FAS_TEST_INI		0x2	/* initiator test mode */
259*0Sstevel@tonic-gate #define	FAS_TEST_TRI		0x4	/* tristate test mode */
260*0Sstevel@tonic-gate 
261*0Sstevel@tonic-gate /*
262*0Sstevel@tonic-gate  * FAS configuration register #2 definitions (read/write)
263*0Sstevel@tonic-gate  */
264*0Sstevel@tonic-gate #define	FAS_CONF2_XL32		0x80
265*0Sstevel@tonic-gate #define	FAS_CONF2_MKDONE	0x40
266*0Sstevel@tonic-gate #define	FAS_CONF2_PAUSE_INTR_DISABLE 0x20
267*0Sstevel@tonic-gate #define	FAS_CONF2_FENABLE	0x10	/* Features Enable */
268*0Sstevel@tonic-gate #define	FAS_CONF2_SCSI2		0x8	/* SCSI-2 mode (target mode only) */
269*0Sstevel@tonic-gate #define	FAS_CONF2_TGT_BAD_PRTY_ABORT 0x4
270*0Sstevel@tonic-gate #define	FAS_CONF2_DMA_PRTY_ENABLE    0x1
271*0Sstevel@tonic-gate 
272*0Sstevel@tonic-gate /*
273*0Sstevel@tonic-gate  * FAS configuration #3	register definitions (read/write)
274*0Sstevel@tonic-gate  */
275*0Sstevel@tonic-gate #define	FAS_CONF3_ODDBYTE_AUTO	0x80	/* auto push an odd-byte to dma */
276*0Sstevel@tonic-gate #define	FAS_CONF3_WIDE		0x40	/* enables wide	*/
277*0Sstevel@tonic-gate #define	FAS_CONF3_IDBIT3	0x20	/* extends scsi	bus ID to 4 bits */
278*0Sstevel@tonic-gate #define	FAS_CONF3_IDRESCHK	0x10	/* ID message checking */
279*0Sstevel@tonic-gate #define	FAS_CONF3_QUENB		0x8	/* 3-byte msg support */
280*0Sstevel@tonic-gate #define	FAS_CONF3_CDB10		0x4	/* group 2 scsi-2 support */
281*0Sstevel@tonic-gate #define	FAS_CONF3_FASTSCSI	0x2	/* 10 MB/S fast	scsi mode */
282*0Sstevel@tonic-gate #define	FAS_CONF3_FASTCLK	0x1	/* fast	clock mode */
283*0Sstevel@tonic-gate 
284*0Sstevel@tonic-gate /*
285*0Sstevel@tonic-gate  * FAS configuration #4 register definitions
286*0Sstevel@tonic-gate  */
287*0Sstevel@tonic-gate #define	FAS_CONF4_PADMSGS	0x20
288*0Sstevel@tonic-gate 
289*0Sstevel@tonic-gate /*
290*0Sstevel@tonic-gate  * FAS part-unique id code definitions (read only)
291*0Sstevel@tonic-gate  */
292*0Sstevel@tonic-gate #define	FAS_REV_MASK		0x7	/* revision level mask */
293*0Sstevel@tonic-gate #define	FAS_FCODE_MASK		0xf8	/* revision family code	mask */
294*0Sstevel@tonic-gate 
295*0Sstevel@tonic-gate /*
296*0Sstevel@tonic-gate  * Macros to get/set an	integer	word into the 4 8-bit
297*0Sstevel@tonic-gate  * registers that constitute the FAS's counter register.
298*0Sstevel@tonic-gate  */
299*0Sstevel@tonic-gate #define	SET_FAS_COUNT(fasreg, val) {	\
300*0Sstevel@tonic-gate 	fas_reg_write(fas, &fasreg->fas_xcnt_lo, (uint8_t)val); \
301*0Sstevel@tonic-gate 	fas_reg_write(fas, &fasreg->fas_xcnt_mid, \
302*0Sstevel@tonic-gate 		(uint8_t)(val >>	8)); \
303*0Sstevel@tonic-gate 	fas_reg_write(fas, &fasreg->fas_recmd_lo, \
304*0Sstevel@tonic-gate 		((uint8_t)(val >> 16)));	\
305*0Sstevel@tonic-gate 	fas_reg_write(fas, &fasreg->fas_recmd_hi, 0); \
306*0Sstevel@tonic-gate }
307*0Sstevel@tonic-gate 
308*0Sstevel@tonic-gate /*
309*0Sstevel@tonic-gate  * to save time, read back 3 registers
310*0Sstevel@tonic-gate  */
311*0Sstevel@tonic-gate #define	GET_FAS_COUNT(fasreg, val) {	\
312*0Sstevel@tonic-gate 	uint8_t lo, mid, r_lo; \
313*0Sstevel@tonic-gate 	lo = fas_reg_read(fas, &fasreg->fas_xcnt_lo); \
314*0Sstevel@tonic-gate 	mid = fas_reg_read(fas,	&fasreg->fas_xcnt_mid);	\
315*0Sstevel@tonic-gate 	r_lo = fas_reg_read(fas, &fasreg->fas_recmd_lo); \
316*0Sstevel@tonic-gate 	(val) =	(uint32_t)(lo | (mid << 8) | ((r_lo) << 16)); \
317*0Sstevel@tonic-gate }
318*0Sstevel@tonic-gate 
319*0Sstevel@tonic-gate 
320*0Sstevel@tonic-gate 
321*0Sstevel@tonic-gate /*
322*0Sstevel@tonic-gate  * FAS Clock constants
323*0Sstevel@tonic-gate  */
324*0Sstevel@tonic-gate 
325*0Sstevel@tonic-gate /*
326*0Sstevel@tonic-gate  * The probe routine will select amongst these values
327*0Sstevel@tonic-gate  * and stuff it	into the tag f_clock_conv in the private host
328*0Sstevel@tonic-gate  * adapter structure (see below) (as well as the the register fas_clock_conv
329*0Sstevel@tonic-gate  * on the chip)
330*0Sstevel@tonic-gate  */
331*0Sstevel@tonic-gate #define	CLOCK_10MHZ		2
332*0Sstevel@tonic-gate #define	CLOCK_15MHZ		3
333*0Sstevel@tonic-gate #define	CLOCK_20MHZ		4
334*0Sstevel@tonic-gate #define	CLOCK_25MHZ		5
335*0Sstevel@tonic-gate #define	CLOCK_30MHZ		6
336*0Sstevel@tonic-gate #define	CLOCK_35MHZ		7
337*0Sstevel@tonic-gate #define	CLOCK_40MHZ		8	/* really 0 */
338*0Sstevel@tonic-gate #define	CLOCK_MASK		0x7
339*0Sstevel@tonic-gate 
340*0Sstevel@tonic-gate /*
341*0Sstevel@tonic-gate  * This	yields nanoseconds per input clock tick
342*0Sstevel@tonic-gate  */
343*0Sstevel@tonic-gate 
344*0Sstevel@tonic-gate #define	CLOCK_PERIOD(mhz)	(1000 *	MEG) / (mhz / 1000)
345*0Sstevel@tonic-gate #define	CONVERT_PERIOD(time)	((time) + 3) >> 2
346*0Sstevel@tonic-gate 
347*0Sstevel@tonic-gate /*
348*0Sstevel@tonic-gate  * Formula to compute the select/reselect timeout register value:
349*0Sstevel@tonic-gate  *
350*0Sstevel@tonic-gate  *	Time_unit = 7682 * CCF * Input_Clock_Period
351*0Sstevel@tonic-gate  *
352*0Sstevel@tonic-gate  * where Time_unit && Input_Clock_Period should	be in the same units.
353*0Sstevel@tonic-gate  * CCF = Clock Conversion Factor from CLOCK_XMHZ above.
354*0Sstevel@tonic-gate  * Desired_Timeout_Period = 250	ms.
355*0Sstevel@tonic-gate  *
356*0Sstevel@tonic-gate  */
357*0Sstevel@tonic-gate #define	FAS_CLOCK_DELAY	7682
358*0Sstevel@tonic-gate #define	FAS_CLOCK_TICK(fas)	\
359*0Sstevel@tonic-gate 	((uint_t)FAS_CLOCK_DELAY * (uint_t)(fas)->f_clock_conv * \
360*0Sstevel@tonic-gate 	(uint_t)(fas)->f_clock_cycle) / (uint_t)1000
361*0Sstevel@tonic-gate #define	FAS_SEL_TIMEOUT	(250 * MEG)
362*0Sstevel@tonic-gate #define	FAS_CLOCK_TIMEOUT(tick,	selection_timeout) \
363*0Sstevel@tonic-gate 	(((selection_timeout) *	MEG) + (tick) -	1) / (tick)
364*0Sstevel@tonic-gate 
365*0Sstevel@tonic-gate /*
366*0Sstevel@tonic-gate  * Max/Min number of clock cycles for synchronous period
367*0Sstevel@tonic-gate  */
368*0Sstevel@tonic-gate #define	MIN_SYNC_FAST(fas)	4
369*0Sstevel@tonic-gate #define	MIN_SYNC_SLOW(fas)	\
370*0Sstevel@tonic-gate 	(((fas)->e_fasconf & FAS_CONF_SLOWMODE) ? 6 : 5)
371*0Sstevel@tonic-gate #define	MIN_SYNC(fas)		(MIN_SYNC_FAST((fas)))
372*0Sstevel@tonic-gate #define	MAX_SYNC(fas)		35
373*0Sstevel@tonic-gate #define	SYNC_PERIOD_MASK	0x1F
374*0Sstevel@tonic-gate 
375*0Sstevel@tonic-gate /*
376*0Sstevel@tonic-gate  * Max/Min time	(in nanoseconds) between successive Req/Ack
377*0Sstevel@tonic-gate  */
378*0Sstevel@tonic-gate #define	MIN_SYNC_TIME(fas)	\
379*0Sstevel@tonic-gate 	((uint_t)MIN_SYNC((fas)) * (uint_t)((fas)->f_clock_cycle)) / \
380*0Sstevel@tonic-gate 	    (uint_t)1000
381*0Sstevel@tonic-gate #define	MAX_SYNC_TIME(fas)	\
382*0Sstevel@tonic-gate 	((uint_t)MAX_SYNC((fas)) * (uint_t)((fas)->f_clock_cycle)) / \
383*0Sstevel@tonic-gate 	    (uint_t)1000
384*0Sstevel@tonic-gate 
385*0Sstevel@tonic-gate /*
386*0Sstevel@tonic-gate  * Max/Min Period values (appropriate for SYNCHRONOUS message).
387*0Sstevel@tonic-gate  * We round up here to make sure that we are always slower
388*0Sstevel@tonic-gate  * (longer time	period).
389*0Sstevel@tonic-gate  */
390*0Sstevel@tonic-gate #define	MIN_SYNC_PERIOD(fas)	(CONVERT_PERIOD(MIN_SYNC_TIME((fas))))
391*0Sstevel@tonic-gate #define	MAX_SYNC_PERIOD(fas)	(CONVERT_PERIOD(MAX_SYNC_TIME((fas))))
392*0Sstevel@tonic-gate 
393*0Sstevel@tonic-gate /*
394*0Sstevel@tonic-gate  * According to	the Emulex application notes for this part,
395*0Sstevel@tonic-gate  * the ability to receive synchronous data is independent
396*0Sstevel@tonic-gate  * of the FAS chip's input clock rate, and is fixed at
397*0Sstevel@tonic-gate  * a maximum 5.6 mb/s (180 ns/byte).
398*0Sstevel@tonic-gate  *
399*0Sstevel@tonic-gate  * Therefore, we could tell targets that we can	*receive*
400*0Sstevel@tonic-gate  * synchronous data this fast.
401*0Sstevel@tonic-gate  * However, the	rest of	the transfer is	still at 5.0 MB/sec so to keep it
402*0Sstevel@tonic-gate  * simple, we negotiate	200 ns
403*0Sstevel@tonic-gate  * On a	c2,  a period of 45 and	50 result in the same register value (8) and
404*0Sstevel@tonic-gate  * consequently	5 MB/sec.
405*0Sstevel@tonic-gate  */
406*0Sstevel@tonic-gate #define	DEFAULT_SYNC_PERIOD		200		/* 5.0 MB/s */
407*0Sstevel@tonic-gate #define	DEFAULT_FASTSYNC_PERIOD		100		/* 10.0	MB/s */
408*0Sstevel@tonic-gate #define	FASTSCSI_THRESHOLD		50		/* 5.0 MB/s */
409*0Sstevel@tonic-gate 
410*0Sstevel@tonic-gate /*
411*0Sstevel@tonic-gate  * Short hand macro convert parameter in
412*0Sstevel@tonic-gate  * nanoseconds/byte into k-bytes/second.
413*0Sstevel@tonic-gate  */
414*0Sstevel@tonic-gate #define	FAS_SYNC_KBPS(ns)	((((1000 * MEG) / (ns)) + 999) / 1000)
415*0Sstevel@tonic-gate 
416*0Sstevel@tonic-gate /*
417*0Sstevel@tonic-gate  * Default Synchronous offset.
418*0Sstevel@tonic-gate  * (max	# of allowable outstanding REQ)
419*0Sstevel@tonic-gate  * IBS allows only 11 bytes offset
420*0Sstevel@tonic-gate  */
421*0Sstevel@tonic-gate #define	DEFAULT_OFFSET	15
422*0Sstevel@tonic-gate 
423*0Sstevel@tonic-gate /*
424*0Sstevel@tonic-gate  * Chip	type defines &&	macros
425*0Sstevel@tonic-gate  */
426*0Sstevel@tonic-gate #define	FAS366		0
427*0Sstevel@tonic-gate #define	FAST		5
428*0Sstevel@tonic-gate 
429*0Sstevel@tonic-gate /* status register #2 definitions (read	only) */
430*0Sstevel@tonic-gate #define	FAS_STAT2_SEQCNT   0x01	   /* Sequence counter bit 7-3 enabled */
431*0Sstevel@tonic-gate #define	FAS_STAT2_FLATCHED 0x02	   /* FIFO flags register latched */
432*0Sstevel@tonic-gate #define	FAS_STAT2_CLATCHED 0x04	   /* Xfer cntr	& recommand ctr	latched */
433*0Sstevel@tonic-gate #define	FAS_STAT2_CACTIVE  0x08	   /* Command register is active */
434*0Sstevel@tonic-gate #define	FAS_STAT2_SCSI16   0x10	   /* SCSI interface is	wide */
435*0Sstevel@tonic-gate #define	FAS_STAT2_ISHUTTLE 0x20	   /* FIFO Top register	contains 1 byte */
436*0Sstevel@tonic-gate #define	FAS_STAT2_OSHUTTLE 0x40	   /* next byte	from FIFO is MSB */
437*0Sstevel@tonic-gate #define	FAS_STAT2_EMPTY	   0x80	   /* FIFO is empty */
438*0Sstevel@tonic-gate 
439*0Sstevel@tonic-gate /*
440*0Sstevel@tonic-gate  * select/reselect bus id register
441*0Sstevel@tonic-gate  */
442*0Sstevel@tonic-gate #define	FAS_BUSID_ENCODID	0x10	/* encode reselection ID */
443*0Sstevel@tonic-gate #define	FAS_BUSID_32BIT_COUNTER	0x40	/* xfer	counter	is 32 bit */
444*0Sstevel@tonic-gate 
445*0Sstevel@tonic-gate #ifdef	__cplusplus
446*0Sstevel@tonic-gate }
447*0Sstevel@tonic-gate #endif
448*0Sstevel@tonic-gate 
449*0Sstevel@tonic-gate #endif	/* _SYS_SCSI_ADAPTERS_FASREG_H */
450