1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright (c) 1996, by Sun Microsystems, Inc. 24*0Sstevel@tonic-gate * All rights reserved. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_SCSI_ADAPTERS_FASDMA_H 28*0Sstevel@tonic-gate #define _SYS_SCSI_ADAPTERS_FASDMA_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate /* 33*0Sstevel@tonic-gate * SCSI Channel Engine (fas SCSI DVMA) definitions 34*0Sstevel@tonic-gate */ 35*0Sstevel@tonic-gate #include <sys/note.h> 36*0Sstevel@tonic-gate 37*0Sstevel@tonic-gate #ifdef __cplusplus 38*0Sstevel@tonic-gate extern "C" { 39*0Sstevel@tonic-gate #endif 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate /* 42*0Sstevel@tonic-gate * for historical reasons, we call the scsi channel engine 43*0Sstevel@tonic-gate * dma for now 44*0Sstevel@tonic-gate */ 45*0Sstevel@tonic-gate struct dma { 46*0Sstevel@tonic-gate uint32_t dma_csr; /* control/status register */ 47*0Sstevel@tonic-gate uint32_t dma_addr; /* dma address register */ 48*0Sstevel@tonic-gate uint32_t dma_count; /* count register */ 49*0Sstevel@tonic-gate uint32_t dma_test; /* test csr register */ 50*0Sstevel@tonic-gate }; 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate /* 54*0Sstevel@tonic-gate * dma_csr bits 55*0Sstevel@tonic-gate */ 56*0Sstevel@tonic-gate #define DMA_INTPEND 0x0001 /* (R) interrupt pending from fas or dma */ 57*0Sstevel@tonic-gate #define DMA_ERRPEND 0x0002 /* (R) error pending from dma */ 58*0Sstevel@tonic-gate #define DMA_DRAINING 0x0004 /* (R) if set, buffers aredraining to mem */ 59*0Sstevel@tonic-gate #define DMA_INTEN 0x0010 /* (RW) enable interrupts */ 60*0Sstevel@tonic-gate #define DMA_RESET 0x0080 /* (RW) invalidates the buffers, resets CE */ 61*0Sstevel@tonic-gate #define DMA_WRITE 0x0100 /* (RW) write to memory */ 62*0Sstevel@tonic-gate #define DMA_ENDVMA 0x0200 /* (RW) enable dvma */ 63*0Sstevel@tonic-gate #define DMA_REQPEND 0x0400 /* (R) do not assert reset when set! */ 64*0Sstevel@tonic-gate #define DMA_DMAREV 0x7800 /* (R) dma revision */ 65*0Sstevel@tonic-gate #define DMA_WIDE_EN 0x8000 /* (RW) enable wide SBus DVMA mode */ 66*0Sstevel@tonic-gate #define DMA_DSBL_DRAIN 0x00020000 /* (RW) disable draining on slave */ 67*0Sstevel@tonic-gate /* accesses */ 68*0Sstevel@tonic-gate #define DMA_BURSTS 0x000c0000 /* (RW) burst sizes */ 69*0Sstevel@tonic-gate #define DMA_TWO_CYCLE 0x00200000 /* (RW) 2 cycle dma access to 366 */ 70*0Sstevel@tonic-gate #define DMA_DSBL_PARITY 0x02000000 /* (RW) disables checking for parity */ 71*0Sstevel@tonic-gate #define DMA_PAUSE_FAS 0x04000000 /* (RW) pause fas */ 72*0Sstevel@tonic-gate #define DMA_RESET_FAS 0x08000000 /* (RW) hardware reset to fas */ 73*0Sstevel@tonic-gate #define DMA_DEV_ID 0xf0000000 /* (R) Device ID (0xb) */ 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate #define DMA_INT_MASK (DMA_INTPEND | DMA_ERRPEND) 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate #define DMA_BITS \ 78*0Sstevel@tonic-gate "\20\34RST\33PSE\31DSBLPAR\26TWOCYC\24BRST1\23BST0\ 79*0Sstevel@tonic-gate \22DSBLEDRN\20WIDE\13REQPEND\12ENBLE\11WR\10RST\05INTEN\ 80*0Sstevel@tonic-gate \03DRNING\02ERRPEND\01INTPND" 81*0Sstevel@tonic-gate 82*0Sstevel@tonic-gate #define DMAREV(dmap) (((dmap->dma_csr) & DMA_DMAREV) >> 11) 83*0Sstevel@tonic-gate 84*0Sstevel@tonic-gate /* 85*0Sstevel@tonic-gate * burst sizes for dma 86*0Sstevel@tonic-gate */ 87*0Sstevel@tonic-gate #define DMA_BURST16 0x00000000 88*0Sstevel@tonic-gate #define DMA_BURST32 0x00040000 89*0Sstevel@tonic-gate #define DMA_BURST64 0x000c0000 90*0Sstevel@tonic-gate #define DMA_CE_ID 0xb0000000 /* SCSI CE device ID */ 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate /* 93*0Sstevel@tonic-gate * burst sizes for dma attr 94*0Sstevel@tonic-gate */ 95*0Sstevel@tonic-gate #define BURST1 0x01 96*0Sstevel@tonic-gate #define BURST2 0x02 97*0Sstevel@tonic-gate #define BURST4 0x04 98*0Sstevel@tonic-gate #define BURST8 0x08 99*0Sstevel@tonic-gate #define BURST16 0x10 100*0Sstevel@tonic-gate #define BURST32 0x20 101*0Sstevel@tonic-gate #define BURST64 0x40 102*0Sstevel@tonic-gate #define BURSTSIZE_MASK 0x7f 103*0Sstevel@tonic-gate #define DEFAULT_BURSTSIZE \ 104*0Sstevel@tonic-gate BURST64|BURST32|BURST16|BURST8|BURST4|BURST2|BURST1 105*0Sstevel@tonic-gate 106*0Sstevel@tonic-gate #ifdef __cplusplus 107*0Sstevel@tonic-gate } 108*0Sstevel@tonic-gate #endif 109*0Sstevel@tonic-gate 110*0Sstevel@tonic-gate #endif /* _SYS_SCSI_ADAPTERS_FASDMA_H */ 111