1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* common code with bug fixes from original version in trap.c */ 30*0Sstevel@tonic-gate 31*0Sstevel@tonic-gate #include <sys/param.h> 32*0Sstevel@tonic-gate #include <sys/types.h> 33*0Sstevel@tonic-gate #include <sys/systm.h> 34*0Sstevel@tonic-gate #include <sys/archsystm.h> 35*0Sstevel@tonic-gate #include <sys/vmsystm.h> 36*0Sstevel@tonic-gate #include <sys/fpu/fpusystm.h> 37*0Sstevel@tonic-gate #include <sys/fpu/fpu_simulator.h> 38*0Sstevel@tonic-gate #include <sys/inline.h> 39*0Sstevel@tonic-gate #include <sys/debug.h> 40*0Sstevel@tonic-gate #include <sys/privregs.h> 41*0Sstevel@tonic-gate #include <sys/machpcb.h> 42*0Sstevel@tonic-gate #include <sys/simulate.h> 43*0Sstevel@tonic-gate #include <sys/proc.h> 44*0Sstevel@tonic-gate #include <sys/cmn_err.h> 45*0Sstevel@tonic-gate #include <sys/stack.h> 46*0Sstevel@tonic-gate #include <sys/watchpoint.h> 47*0Sstevel@tonic-gate #include <sys/trap.h> 48*0Sstevel@tonic-gate #include <sys/machtrap.h> 49*0Sstevel@tonic-gate #include <sys/mman.h> 50*0Sstevel@tonic-gate #include <sys/asi.h> 51*0Sstevel@tonic-gate #include <sys/copyops.h> 52*0Sstevel@tonic-gate #include <vm/as.h> 53*0Sstevel@tonic-gate #include <vm/page.h> 54*0Sstevel@tonic-gate #include <sys/model.h> 55*0Sstevel@tonic-gate #include <vm/seg_vn.h> 56*0Sstevel@tonic-gate 57*0Sstevel@tonic-gate #define IS_IBIT_SET(x) (x & 0x2000) 58*0Sstevel@tonic-gate #define IS_VIS1(op, op3)(op == 2 && op3 == 0x36) 59*0Sstevel@tonic-gate #define IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(op, op3, asi) \ 60*0Sstevel@tonic-gate (op == 3 && (op3 == IOP_V8_LDDFA || \ 61*0Sstevel@tonic-gate op3 == IOP_V8_STDFA) && asi > ASI_SNFL) 62*0Sstevel@tonic-gate 63*0Sstevel@tonic-gate static int aligndebug = 0; 64*0Sstevel@tonic-gate 65*0Sstevel@tonic-gate /* 66*0Sstevel@tonic-gate * For the sake of those who must be compatible with unaligned 67*0Sstevel@tonic-gate * architectures, users can link their programs to use a 68*0Sstevel@tonic-gate * corrective trap handler that will fix unaligned references 69*0Sstevel@tonic-gate * a special trap #6 (T_FIX_ALIGN) enables this 'feature'. 70*0Sstevel@tonic-gate * Returns 1 for success, 0 for failure. 71*0Sstevel@tonic-gate */ 72*0Sstevel@tonic-gate 73*0Sstevel@tonic-gate int 74*0Sstevel@tonic-gate do_unaligned(struct regs *rp, caddr_t *badaddr) 75*0Sstevel@tonic-gate { 76*0Sstevel@tonic-gate uint_t inst, op3, asi = 0; 77*0Sstevel@tonic-gate uint_t rd, rs1, rs2; 78*0Sstevel@tonic-gate int sz, nf = 0, ltlend = 0; 79*0Sstevel@tonic-gate int floatflg; 80*0Sstevel@tonic-gate int fsrflg; 81*0Sstevel@tonic-gate int immflg; 82*0Sstevel@tonic-gate int lddstdflg; 83*0Sstevel@tonic-gate caddr_t addr; 84*0Sstevel@tonic-gate uint64_t val; 85*0Sstevel@tonic-gate union { 86*0Sstevel@tonic-gate uint64_t l[2]; 87*0Sstevel@tonic-gate uint32_t i[4]; 88*0Sstevel@tonic-gate uint16_t s[8]; 89*0Sstevel@tonic-gate uint8_t c[16]; 90*0Sstevel@tonic-gate } data; 91*0Sstevel@tonic-gate 92*0Sstevel@tonic-gate ASSERT(USERMODE(rp->r_tstate)); 93*0Sstevel@tonic-gate inst = fetch_user_instr((caddr_t)rp->r_pc); 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate op3 = (inst >> 19) & 0x3f; 96*0Sstevel@tonic-gate rd = (inst >> 25) & 0x1f; 97*0Sstevel@tonic-gate rs1 = (inst >> 14) & 0x1f; 98*0Sstevel@tonic-gate rs2 = inst & 0x1f; 99*0Sstevel@tonic-gate floatflg = (inst >> 24) & 1; 100*0Sstevel@tonic-gate immflg = (inst >> 13) & 1; 101*0Sstevel@tonic-gate lddstdflg = fsrflg = 0; 102*0Sstevel@tonic-gate 103*0Sstevel@tonic-gate /* if not load or store do nothing */ 104*0Sstevel@tonic-gate if ((inst >> 30) != 3) 105*0Sstevel@tonic-gate return (0); 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate /* if ldstub or swap, do nothing */ 108*0Sstevel@tonic-gate if ((inst & 0xc1680000) == 0xc0680000) 109*0Sstevel@tonic-gate return (0); 110*0Sstevel@tonic-gate 111*0Sstevel@tonic-gate /* if cas/casx, do nothing */ 112*0Sstevel@tonic-gate if ((inst & 0xc1e00000) == 0xc1e00000) 113*0Sstevel@tonic-gate return (0); 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate if (floatflg) { 116*0Sstevel@tonic-gate switch ((inst >> 19) & 3) { /* map size bits to a number */ 117*0Sstevel@tonic-gate case 0: sz = 4; 118*0Sstevel@tonic-gate break; /* ldf{a}/stf{a} */ 119*0Sstevel@tonic-gate case 1: fsrflg = 1; 120*0Sstevel@tonic-gate if (rd == 0) 121*0Sstevel@tonic-gate sz = 4; /* ldfsr/stfsr */ 122*0Sstevel@tonic-gate else if (rd == 1) 123*0Sstevel@tonic-gate sz = 8; /* ldxfsr/stxfsr */ 124*0Sstevel@tonic-gate else 125*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 126*0Sstevel@tonic-gate break; 127*0Sstevel@tonic-gate case 2: sz = 16; 128*0Sstevel@tonic-gate break; /* ldqf{a}/stqf{a} */ 129*0Sstevel@tonic-gate case 3: sz = 8; 130*0Sstevel@tonic-gate break; /* lddf{a}/stdf{a} */ 131*0Sstevel@tonic-gate } 132*0Sstevel@tonic-gate /* 133*0Sstevel@tonic-gate * Fix to access extra double register encoding plus 134*0Sstevel@tonic-gate * compensate to access the correct fpu_dreg. 135*0Sstevel@tonic-gate */ 136*0Sstevel@tonic-gate if ((sz > 4) && (fsrflg == 0)) { 137*0Sstevel@tonic-gate if ((rd & 1) == 1) 138*0Sstevel@tonic-gate rd = (rd & 0x1e) | 0x20; 139*0Sstevel@tonic-gate rd = rd >> 1; 140*0Sstevel@tonic-gate if ((sz == 16) && ((rd & 0x1) != 0)) 141*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 142*0Sstevel@tonic-gate } 143*0Sstevel@tonic-gate } else { 144*0Sstevel@tonic-gate int sz_bits = (inst >> 19) & 0xf; 145*0Sstevel@tonic-gate switch (sz_bits) { /* map size bits to a number */ 146*0Sstevel@tonic-gate case 0: /* lduw{a} */ 147*0Sstevel@tonic-gate case 4: /* stw{a} */ 148*0Sstevel@tonic-gate case 8: /* ldsw{a} */ 149*0Sstevel@tonic-gate case 0xf: /* swap */ 150*0Sstevel@tonic-gate sz = 4; break; 151*0Sstevel@tonic-gate case 1: /* ldub{a} */ 152*0Sstevel@tonic-gate case 5: /* stb{a} */ 153*0Sstevel@tonic-gate case 9: /* ldsb{a} */ 154*0Sstevel@tonic-gate case 0xd: /* ldstub */ 155*0Sstevel@tonic-gate sz = 1; break; 156*0Sstevel@tonic-gate case 2: /* lduh{a} */ 157*0Sstevel@tonic-gate case 6: /* sth{a} */ 158*0Sstevel@tonic-gate case 0xa: /* ldsh{a} */ 159*0Sstevel@tonic-gate sz = 2; break; 160*0Sstevel@tonic-gate case 3: /* ldd{a} */ 161*0Sstevel@tonic-gate case 7: /* std{a} */ 162*0Sstevel@tonic-gate lddstdflg = 1; 163*0Sstevel@tonic-gate sz = 8; break; 164*0Sstevel@tonic-gate case 0xb: /* ldx{a} */ 165*0Sstevel@tonic-gate case 0xe: /* stx{a} */ 166*0Sstevel@tonic-gate sz = 8; break; 167*0Sstevel@tonic-gate } 168*0Sstevel@tonic-gate } 169*0Sstevel@tonic-gate 170*0Sstevel@tonic-gate 171*0Sstevel@tonic-gate /* only support primary and secondary asi's */ 172*0Sstevel@tonic-gate if ((op3 >> 4) & 1) { 173*0Sstevel@tonic-gate if (immflg) { 174*0Sstevel@tonic-gate asi = (uint_t)(rp->r_tstate >> TSTATE_ASI_SHIFT) & 175*0Sstevel@tonic-gate TSTATE_ASI_MASK; 176*0Sstevel@tonic-gate } else { 177*0Sstevel@tonic-gate asi = (inst >> 5) & 0xff; 178*0Sstevel@tonic-gate } 179*0Sstevel@tonic-gate switch (asi) { 180*0Sstevel@tonic-gate case ASI_P: 181*0Sstevel@tonic-gate case ASI_S: 182*0Sstevel@tonic-gate break; 183*0Sstevel@tonic-gate case ASI_PNF: 184*0Sstevel@tonic-gate case ASI_SNF: 185*0Sstevel@tonic-gate nf = 1; 186*0Sstevel@tonic-gate break; 187*0Sstevel@tonic-gate case ASI_PL: 188*0Sstevel@tonic-gate case ASI_SL: 189*0Sstevel@tonic-gate ltlend = 1; 190*0Sstevel@tonic-gate break; 191*0Sstevel@tonic-gate case ASI_PNFL: 192*0Sstevel@tonic-gate case ASI_SNFL: 193*0Sstevel@tonic-gate ltlend = 1; 194*0Sstevel@tonic-gate nf = 1; 195*0Sstevel@tonic-gate break; 196*0Sstevel@tonic-gate default: 197*0Sstevel@tonic-gate return (0); 198*0Sstevel@tonic-gate } 199*0Sstevel@tonic-gate /* 200*0Sstevel@tonic-gate * Non-faulting stores generate a data_access_exception trap, 201*0Sstevel@tonic-gate * according to the Spitfire manual, which should be signaled 202*0Sstevel@tonic-gate * as an illegal instruction trap, because it can't be fixed. 203*0Sstevel@tonic-gate */ 204*0Sstevel@tonic-gate if ((nf) && ((op3 == IOP_V8_STQFA) || (op3 == IOP_V8_STDFA))) 205*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 206*0Sstevel@tonic-gate } 207*0Sstevel@tonic-gate 208*0Sstevel@tonic-gate if (aligndebug) { 209*0Sstevel@tonic-gate printf("unaligned access at %p, instruction: 0x%x\n", 210*0Sstevel@tonic-gate (void *)rp->r_pc, inst); 211*0Sstevel@tonic-gate printf("type %s", (((inst >> 21) & 1) ? "st" : "ld")); 212*0Sstevel@tonic-gate if (((inst >> 21) & 1) == 0) 213*0Sstevel@tonic-gate printf(" %s", (((inst >> 22) & 1) ? "signed" : "unsigned")); 214*0Sstevel@tonic-gate printf(" asi 0x%x size %d immflg %d\n", asi, sz, immflg); 215*0Sstevel@tonic-gate printf("rd = %d, op3 = 0x%x, rs1 = %d, rs2 = %d, imm13=0x%x\n", 216*0Sstevel@tonic-gate rd, op3, rs1, rs2, (inst & 0x1fff)); 217*0Sstevel@tonic-gate } 218*0Sstevel@tonic-gate 219*0Sstevel@tonic-gate (void) flush_user_windows_to_stack(NULL); 220*0Sstevel@tonic-gate if (getreg(rp, rs1, &val, badaddr)) 221*0Sstevel@tonic-gate return (SIMU_FAULT); 222*0Sstevel@tonic-gate addr = (caddr_t)val; /* convert to 32/64 bit address */ 223*0Sstevel@tonic-gate if (aligndebug) 224*0Sstevel@tonic-gate printf("addr 1 = %p\n", (void *)addr); 225*0Sstevel@tonic-gate 226*0Sstevel@tonic-gate /* check immediate bit and use immediate field or reg (rs2) */ 227*0Sstevel@tonic-gate if (immflg) { 228*0Sstevel@tonic-gate int imm; 229*0Sstevel@tonic-gate imm = inst & 0x1fff; /* mask out immediate field */ 230*0Sstevel@tonic-gate imm <<= 19; /* sign extend it */ 231*0Sstevel@tonic-gate imm >>= 19; 232*0Sstevel@tonic-gate addr += imm; /* compute address */ 233*0Sstevel@tonic-gate } else { 234*0Sstevel@tonic-gate if (getreg(rp, rs2, &val, badaddr)) 235*0Sstevel@tonic-gate return (SIMU_FAULT); 236*0Sstevel@tonic-gate addr += val; 237*0Sstevel@tonic-gate } 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate /* 240*0Sstevel@tonic-gate * If this is a 32-bit program, chop the address accordingly. 241*0Sstevel@tonic-gate */ 242*0Sstevel@tonic-gate if (curproc->p_model == DATAMODEL_ILP32) 243*0Sstevel@tonic-gate addr = (caddr_t)(caddr32_t)addr; 244*0Sstevel@tonic-gate 245*0Sstevel@tonic-gate if (aligndebug) 246*0Sstevel@tonic-gate printf("addr 2 = %p\n", (void *)addr); 247*0Sstevel@tonic-gate 248*0Sstevel@tonic-gate if (addr >= curproc->p_as->a_userlimit) { 249*0Sstevel@tonic-gate *badaddr = addr; 250*0Sstevel@tonic-gate goto badret; 251*0Sstevel@tonic-gate } 252*0Sstevel@tonic-gate 253*0Sstevel@tonic-gate /* a single bit differentiates ld and st */ 254*0Sstevel@tonic-gate if ((inst >> 21) & 1) { /* store */ 255*0Sstevel@tonic-gate if (floatflg) { 256*0Sstevel@tonic-gate klwp_id_t lwp = ttolwp(curthread); 257*0Sstevel@tonic-gate kfpu_t *fp = lwptofpu(lwp); 258*0Sstevel@tonic-gate /* Ensure fp has been enabled */ 259*0Sstevel@tonic-gate if (fpu_exists) { 260*0Sstevel@tonic-gate if (!(_fp_read_fprs() & FPRS_FEF)) 261*0Sstevel@tonic-gate fp_enable(); 262*0Sstevel@tonic-gate } else { 263*0Sstevel@tonic-gate if (!fp->fpu_en) 264*0Sstevel@tonic-gate fp_enable(); 265*0Sstevel@tonic-gate } 266*0Sstevel@tonic-gate /* if fpu_exists read fpu reg */ 267*0Sstevel@tonic-gate if (fpu_exists) { 268*0Sstevel@tonic-gate if (fsrflg) { 269*0Sstevel@tonic-gate _fp_read_pfsr(&data.l[0]); 270*0Sstevel@tonic-gate } else { 271*0Sstevel@tonic-gate if (sz == 4) { 272*0Sstevel@tonic-gate data.i[0] = 0; 273*0Sstevel@tonic-gate _fp_read_pfreg( 274*0Sstevel@tonic-gate (unsigned *)&data.i[1], rd); 275*0Sstevel@tonic-gate } 276*0Sstevel@tonic-gate if (sz >= 8) 277*0Sstevel@tonic-gate _fp_read_pdreg( 278*0Sstevel@tonic-gate &data.l[0], rd); 279*0Sstevel@tonic-gate if (sz == 16) 280*0Sstevel@tonic-gate _fp_read_pdreg( 281*0Sstevel@tonic-gate &data.l[1], rd+1); 282*0Sstevel@tonic-gate } 283*0Sstevel@tonic-gate } else { 284*0Sstevel@tonic-gate if (fsrflg) { 285*0Sstevel@tonic-gate /* Clear reserved bits, set version=7 */ 286*0Sstevel@tonic-gate fp->fpu_fsr &= ~0x30301000; 287*0Sstevel@tonic-gate fp->fpu_fsr |= 0xE0000; 288*0Sstevel@tonic-gate data.l[0] = fp->fpu_fsr; 289*0Sstevel@tonic-gate } else { 290*0Sstevel@tonic-gate if (sz == 4) { 291*0Sstevel@tonic-gate data.i[0] = 0; 292*0Sstevel@tonic-gate data.i[1] = 293*0Sstevel@tonic-gate (unsigned)fp->fpu_fr.fpu_regs[rd]; 294*0Sstevel@tonic-gate } 295*0Sstevel@tonic-gate if (sz >= 8) 296*0Sstevel@tonic-gate data.l[0] = 297*0Sstevel@tonic-gate fp->fpu_fr.fpu_dregs[rd]; 298*0Sstevel@tonic-gate if (sz == 16) 299*0Sstevel@tonic-gate data.l[1] = 300*0Sstevel@tonic-gate fp->fpu_fr.fpu_dregs[rd+1]; 301*0Sstevel@tonic-gate } 302*0Sstevel@tonic-gate } 303*0Sstevel@tonic-gate } else { 304*0Sstevel@tonic-gate if (lddstdflg) { 305*0Sstevel@tonic-gate if (getreg(rp, rd, &data.l[0], badaddr)) 306*0Sstevel@tonic-gate return (SIMU_FAULT); 307*0Sstevel@tonic-gate if (getreg(rp, rd+1, &data.l[1], badaddr)) 308*0Sstevel@tonic-gate return (SIMU_FAULT); 309*0Sstevel@tonic-gate data.i[0] = data.i[1]; /* combine the data */ 310*0Sstevel@tonic-gate data.i[1] = data.i[3]; 311*0Sstevel@tonic-gate } else { 312*0Sstevel@tonic-gate if (getreg(rp, rd, &data.l[0], badaddr)) 313*0Sstevel@tonic-gate return (SIMU_FAULT); 314*0Sstevel@tonic-gate } 315*0Sstevel@tonic-gate } 316*0Sstevel@tonic-gate 317*0Sstevel@tonic-gate if (aligndebug) { 318*0Sstevel@tonic-gate if (sz == 16) { 319*0Sstevel@tonic-gate printf("data %x %x %x %x\n", 320*0Sstevel@tonic-gate data.i[0], data.i[1], data.i[2], data.c[3]); 321*0Sstevel@tonic-gate } else { 322*0Sstevel@tonic-gate printf("data %x %x %x %x %x %x %x %x\n", 323*0Sstevel@tonic-gate data.c[0], data.c[1], data.c[2], data.c[3], 324*0Sstevel@tonic-gate data.c[4], data.c[5], data.c[6], data.c[7]); 325*0Sstevel@tonic-gate } 326*0Sstevel@tonic-gate } 327*0Sstevel@tonic-gate 328*0Sstevel@tonic-gate if (ltlend) { 329*0Sstevel@tonic-gate if (sz == 1) { 330*0Sstevel@tonic-gate if (xcopyout_little(&data.c[7], addr, 331*0Sstevel@tonic-gate (size_t)sz) != 0) 332*0Sstevel@tonic-gate goto badret; 333*0Sstevel@tonic-gate } else if (sz == 2) { 334*0Sstevel@tonic-gate if (xcopyout_little(&data.s[3], addr, 335*0Sstevel@tonic-gate (size_t)sz) != 0) 336*0Sstevel@tonic-gate goto badret; 337*0Sstevel@tonic-gate } else if (sz == 4) { 338*0Sstevel@tonic-gate if (xcopyout_little(&data.i[1], addr, 339*0Sstevel@tonic-gate (size_t)sz) != 0) 340*0Sstevel@tonic-gate goto badret; 341*0Sstevel@tonic-gate } else { 342*0Sstevel@tonic-gate if (xcopyout_little(&data.l[0], addr, 343*0Sstevel@tonic-gate (size_t)sz) != 0) 344*0Sstevel@tonic-gate goto badret; 345*0Sstevel@tonic-gate } 346*0Sstevel@tonic-gate } else { 347*0Sstevel@tonic-gate if (sz == 1) { 348*0Sstevel@tonic-gate if (copyout(&data.c[7], addr, (size_t)sz) == -1) 349*0Sstevel@tonic-gate goto badret; 350*0Sstevel@tonic-gate } else if (sz == 2) { 351*0Sstevel@tonic-gate if (copyout(&data.s[3], addr, (size_t)sz) == -1) 352*0Sstevel@tonic-gate goto badret; 353*0Sstevel@tonic-gate } else if (sz == 4) { 354*0Sstevel@tonic-gate if (copyout(&data.i[1], addr, (size_t)sz) == -1) 355*0Sstevel@tonic-gate goto badret; 356*0Sstevel@tonic-gate } else { 357*0Sstevel@tonic-gate if (copyout(&data.l[0], addr, (size_t)sz) == -1) 358*0Sstevel@tonic-gate goto badret; 359*0Sstevel@tonic-gate } 360*0Sstevel@tonic-gate } 361*0Sstevel@tonic-gate } else { /* load */ 362*0Sstevel@tonic-gate if (sz == 1) { 363*0Sstevel@tonic-gate if (ltlend) { 364*0Sstevel@tonic-gate if (xcopyin_little(addr, &data.c[7], 365*0Sstevel@tonic-gate (size_t)sz) != 0) { 366*0Sstevel@tonic-gate if (nf) 367*0Sstevel@tonic-gate data.c[7] = 0; 368*0Sstevel@tonic-gate else 369*0Sstevel@tonic-gate goto badret; 370*0Sstevel@tonic-gate } 371*0Sstevel@tonic-gate } else { 372*0Sstevel@tonic-gate if (copyin(addr, &data.c[7], 373*0Sstevel@tonic-gate (size_t)sz) == -1) { 374*0Sstevel@tonic-gate if (nf) 375*0Sstevel@tonic-gate data.c[7] = 0; 376*0Sstevel@tonic-gate else 377*0Sstevel@tonic-gate goto badret; 378*0Sstevel@tonic-gate } 379*0Sstevel@tonic-gate } 380*0Sstevel@tonic-gate /* if signed and the sign bit is set extend it */ 381*0Sstevel@tonic-gate if (((inst >> 22) & 1) && ((data.c[7] >> 7) & 1)) { 382*0Sstevel@tonic-gate data.i[0] = (uint_t)-1; /* extend sign bit */ 383*0Sstevel@tonic-gate data.s[2] = (ushort_t)-1; 384*0Sstevel@tonic-gate data.c[6] = (uchar_t)-1; 385*0Sstevel@tonic-gate } else { 386*0Sstevel@tonic-gate data.i[0] = 0; /* clear upper 32+24 bits */ 387*0Sstevel@tonic-gate data.s[2] = 0; 388*0Sstevel@tonic-gate data.c[6] = 0; 389*0Sstevel@tonic-gate } 390*0Sstevel@tonic-gate } else if (sz == 2) { 391*0Sstevel@tonic-gate if (ltlend) { 392*0Sstevel@tonic-gate if (xcopyin_little(addr, &data.s[3], 393*0Sstevel@tonic-gate (size_t)sz) != 0) { 394*0Sstevel@tonic-gate if (nf) 395*0Sstevel@tonic-gate data.s[3] = 0; 396*0Sstevel@tonic-gate else 397*0Sstevel@tonic-gate goto badret; 398*0Sstevel@tonic-gate } 399*0Sstevel@tonic-gate } else { 400*0Sstevel@tonic-gate if (copyin(addr, &data.s[3], 401*0Sstevel@tonic-gate (size_t)sz) == -1) { 402*0Sstevel@tonic-gate if (nf) 403*0Sstevel@tonic-gate data.s[3] = 0; 404*0Sstevel@tonic-gate else 405*0Sstevel@tonic-gate goto badret; 406*0Sstevel@tonic-gate } 407*0Sstevel@tonic-gate } 408*0Sstevel@tonic-gate /* if signed and the sign bit is set extend it */ 409*0Sstevel@tonic-gate if (((inst >> 22) & 1) && ((data.s[3] >> 15) & 1)) { 410*0Sstevel@tonic-gate data.i[0] = (uint_t)-1; /* extend sign bit */ 411*0Sstevel@tonic-gate data.s[2] = (ushort_t)-1; 412*0Sstevel@tonic-gate } else { 413*0Sstevel@tonic-gate data.i[0] = 0; /* clear upper 32+16 bits */ 414*0Sstevel@tonic-gate data.s[2] = 0; 415*0Sstevel@tonic-gate } 416*0Sstevel@tonic-gate } else if (sz == 4) { 417*0Sstevel@tonic-gate if (ltlend) { 418*0Sstevel@tonic-gate if (xcopyin_little(addr, &data.i[1], 419*0Sstevel@tonic-gate (size_t)sz) != 0) { 420*0Sstevel@tonic-gate if (!nf) 421*0Sstevel@tonic-gate goto badret; 422*0Sstevel@tonic-gate data.i[1] = 0; 423*0Sstevel@tonic-gate } 424*0Sstevel@tonic-gate } else { 425*0Sstevel@tonic-gate if (copyin(addr, &data.i[1], 426*0Sstevel@tonic-gate (size_t)sz) == -1) { 427*0Sstevel@tonic-gate if (!nf) 428*0Sstevel@tonic-gate goto badret; 429*0Sstevel@tonic-gate data.i[1] = 0; 430*0Sstevel@tonic-gate } 431*0Sstevel@tonic-gate } 432*0Sstevel@tonic-gate /* if signed and the sign bit is set extend it */ 433*0Sstevel@tonic-gate if (((inst >> 22) & 1) && ((data.i[1] >> 31) & 1)) { 434*0Sstevel@tonic-gate data.i[0] = (uint_t)-1; /* extend sign bit */ 435*0Sstevel@tonic-gate } else { 436*0Sstevel@tonic-gate data.i[0] = 0; /* clear upper 32 bits */ 437*0Sstevel@tonic-gate } 438*0Sstevel@tonic-gate } else { 439*0Sstevel@tonic-gate if (ltlend) { 440*0Sstevel@tonic-gate if (xcopyin_little(addr, &data.l[0], 441*0Sstevel@tonic-gate (size_t)sz) != 0) { 442*0Sstevel@tonic-gate if (!nf) 443*0Sstevel@tonic-gate goto badret; 444*0Sstevel@tonic-gate data.l[0] = 0; 445*0Sstevel@tonic-gate } 446*0Sstevel@tonic-gate } else { 447*0Sstevel@tonic-gate if (copyin(addr, &data.l[0], 448*0Sstevel@tonic-gate (size_t)sz) == -1) { 449*0Sstevel@tonic-gate if (!nf) 450*0Sstevel@tonic-gate goto badret; 451*0Sstevel@tonic-gate data.l[0] = 0; 452*0Sstevel@tonic-gate } 453*0Sstevel@tonic-gate } 454*0Sstevel@tonic-gate } 455*0Sstevel@tonic-gate 456*0Sstevel@tonic-gate if (aligndebug) { 457*0Sstevel@tonic-gate if (sz == 16) { 458*0Sstevel@tonic-gate printf("data %x %x %x %x\n", 459*0Sstevel@tonic-gate data.i[0], data.i[1], data.i[2], data.c[3]); 460*0Sstevel@tonic-gate } else { 461*0Sstevel@tonic-gate printf("data %x %x %x %x %x %x %x %x\n", 462*0Sstevel@tonic-gate data.c[0], data.c[1], data.c[2], data.c[3], 463*0Sstevel@tonic-gate data.c[4], data.c[5], data.c[6], data.c[7]); 464*0Sstevel@tonic-gate } 465*0Sstevel@tonic-gate } 466*0Sstevel@tonic-gate 467*0Sstevel@tonic-gate if (floatflg) { /* if fpu_exists write fpu reg */ 468*0Sstevel@tonic-gate klwp_id_t lwp = ttolwp(curthread); 469*0Sstevel@tonic-gate kfpu_t *fp = lwptofpu(lwp); 470*0Sstevel@tonic-gate /* Ensure fp has been enabled */ 471*0Sstevel@tonic-gate if (fpu_exists) { 472*0Sstevel@tonic-gate if (!(_fp_read_fprs() & FPRS_FEF)) 473*0Sstevel@tonic-gate fp_enable(); 474*0Sstevel@tonic-gate } else { 475*0Sstevel@tonic-gate if (!fp->fpu_en) 476*0Sstevel@tonic-gate fp_enable(); 477*0Sstevel@tonic-gate } 478*0Sstevel@tonic-gate /* if fpu_exists read fpu reg */ 479*0Sstevel@tonic-gate if (fpu_exists) { 480*0Sstevel@tonic-gate if (fsrflg) { 481*0Sstevel@tonic-gate _fp_write_pfsr(&data.l[0]); 482*0Sstevel@tonic-gate } else { 483*0Sstevel@tonic-gate if (sz == 4) 484*0Sstevel@tonic-gate _fp_write_pfreg( 485*0Sstevel@tonic-gate (unsigned *)&data.i[1], rd); 486*0Sstevel@tonic-gate if (sz >= 8) 487*0Sstevel@tonic-gate _fp_write_pdreg( 488*0Sstevel@tonic-gate &data.l[0], rd); 489*0Sstevel@tonic-gate if (sz == 16) 490*0Sstevel@tonic-gate _fp_write_pdreg( 491*0Sstevel@tonic-gate &data.l[1], rd+1); 492*0Sstevel@tonic-gate } 493*0Sstevel@tonic-gate } else { 494*0Sstevel@tonic-gate if (fsrflg) { 495*0Sstevel@tonic-gate fp->fpu_fsr = data.l[0]; 496*0Sstevel@tonic-gate } else { 497*0Sstevel@tonic-gate if (sz == 4) 498*0Sstevel@tonic-gate fp->fpu_fr.fpu_regs[rd] = 499*0Sstevel@tonic-gate (unsigned)data.i[1]; 500*0Sstevel@tonic-gate if (sz >= 8) 501*0Sstevel@tonic-gate fp->fpu_fr.fpu_dregs[rd] = 502*0Sstevel@tonic-gate data.l[0]; 503*0Sstevel@tonic-gate if (sz == 16) 504*0Sstevel@tonic-gate fp->fpu_fr.fpu_dregs[rd+1] = 505*0Sstevel@tonic-gate data.l[1]; 506*0Sstevel@tonic-gate } 507*0Sstevel@tonic-gate } 508*0Sstevel@tonic-gate } else { 509*0Sstevel@tonic-gate if (lddstdflg) { /* split the data */ 510*0Sstevel@tonic-gate data.i[2] = 0; 511*0Sstevel@tonic-gate data.i[3] = data.i[1]; 512*0Sstevel@tonic-gate data.i[1] = data.i[0]; 513*0Sstevel@tonic-gate data.i[0] = 0; 514*0Sstevel@tonic-gate if (putreg(&data.l[0], rp, rd, badaddr) == -1) 515*0Sstevel@tonic-gate goto badret; 516*0Sstevel@tonic-gate if (putreg(&data.l[1], rp, rd+1, badaddr) == -1) 517*0Sstevel@tonic-gate goto badret; 518*0Sstevel@tonic-gate } else { 519*0Sstevel@tonic-gate if (putreg(&data.l[0], rp, rd, badaddr) == -1) 520*0Sstevel@tonic-gate goto badret; 521*0Sstevel@tonic-gate } 522*0Sstevel@tonic-gate } 523*0Sstevel@tonic-gate } 524*0Sstevel@tonic-gate return (SIMU_SUCCESS); 525*0Sstevel@tonic-gate badret: 526*0Sstevel@tonic-gate return (SIMU_FAULT); 527*0Sstevel@tonic-gate } 528*0Sstevel@tonic-gate 529*0Sstevel@tonic-gate /* 530*0Sstevel@tonic-gate * simulate popc 531*0Sstevel@tonic-gate */ 532*0Sstevel@tonic-gate static int 533*0Sstevel@tonic-gate simulate_popc(struct regs *rp, caddr_t *badaddr, uint_t inst) 534*0Sstevel@tonic-gate { 535*0Sstevel@tonic-gate uint_t rd, rs2, rs1; 536*0Sstevel@tonic-gate uint_t immflg; 537*0Sstevel@tonic-gate uint64_t val, cnt = 0; 538*0Sstevel@tonic-gate 539*0Sstevel@tonic-gate rd = (inst >> 25) & 0x1f; 540*0Sstevel@tonic-gate rs1 = (inst >> 14) & 0x1f; 541*0Sstevel@tonic-gate rs2 = inst & 0x1f; 542*0Sstevel@tonic-gate immflg = (inst >> 13) & 1; 543*0Sstevel@tonic-gate 544*0Sstevel@tonic-gate if (rs1 > 0) 545*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 546*0Sstevel@tonic-gate 547*0Sstevel@tonic-gate (void) flush_user_windows_to_stack(NULL); 548*0Sstevel@tonic-gate 549*0Sstevel@tonic-gate /* check immediate bit and use immediate field or reg (rs2) */ 550*0Sstevel@tonic-gate if (immflg) { 551*0Sstevel@tonic-gate int64_t imm; 552*0Sstevel@tonic-gate imm = inst & 0x1fff; /* mask out immediate field */ 553*0Sstevel@tonic-gate imm <<= 51; /* sign extend it */ 554*0Sstevel@tonic-gate imm >>= 51; 555*0Sstevel@tonic-gate if (imm != 0) { 556*0Sstevel@tonic-gate for (cnt = 0; imm != 0; imm &= imm-1) 557*0Sstevel@tonic-gate cnt++; 558*0Sstevel@tonic-gate } 559*0Sstevel@tonic-gate } else { 560*0Sstevel@tonic-gate if (getreg(rp, rs2, &val, badaddr)) 561*0Sstevel@tonic-gate return (SIMU_FAULT); 562*0Sstevel@tonic-gate if (val != 0) { 563*0Sstevel@tonic-gate for (cnt = 0; val != 0; val &= val-1) 564*0Sstevel@tonic-gate cnt++; 565*0Sstevel@tonic-gate } 566*0Sstevel@tonic-gate } 567*0Sstevel@tonic-gate 568*0Sstevel@tonic-gate if (putreg(&cnt, rp, rd, badaddr) == -1) 569*0Sstevel@tonic-gate return (SIMU_FAULT); 570*0Sstevel@tonic-gate 571*0Sstevel@tonic-gate return (SIMU_SUCCESS); 572*0Sstevel@tonic-gate } 573*0Sstevel@tonic-gate 574*0Sstevel@tonic-gate /* 575*0Sstevel@tonic-gate * simulate unimplemented instructions (popc, ldqf{a}, stqf{a}) 576*0Sstevel@tonic-gate */ 577*0Sstevel@tonic-gate int 578*0Sstevel@tonic-gate simulate_unimp(struct regs *rp, caddr_t *badaddr) 579*0Sstevel@tonic-gate { 580*0Sstevel@tonic-gate uint_t inst, optype, op3, asi; 581*0Sstevel@tonic-gate uint_t rs1, rd; 582*0Sstevel@tonic-gate uint_t ignor, i; 583*0Sstevel@tonic-gate machpcb_t *mpcb = lwptompcb(ttolwp(curthread)); 584*0Sstevel@tonic-gate int nomatch = 0; 585*0Sstevel@tonic-gate caddr_t addr = (caddr_t)rp->r_pc; 586*0Sstevel@tonic-gate struct as *as; 587*0Sstevel@tonic-gate caddr_t ka; 588*0Sstevel@tonic-gate pfn_t pfnum; 589*0Sstevel@tonic-gate page_t *pp; 590*0Sstevel@tonic-gate proc_t *p = ttoproc(curthread); 591*0Sstevel@tonic-gate struct seg *mapseg; 592*0Sstevel@tonic-gate struct segvn_data *svd; 593*0Sstevel@tonic-gate 594*0Sstevel@tonic-gate ASSERT(USERMODE(rp->r_tstate)); 595*0Sstevel@tonic-gate inst = fetch_user_instr(addr); 596*0Sstevel@tonic-gate if (inst == (uint_t)-1) { 597*0Sstevel@tonic-gate mpcb->mpcb_illexcaddr = addr; 598*0Sstevel@tonic-gate mpcb->mpcb_illexcinsn = (uint32_t)-1; 599*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 600*0Sstevel@tonic-gate } 601*0Sstevel@tonic-gate 602*0Sstevel@tonic-gate /* 603*0Sstevel@tonic-gate * When fixing dirty v8 instructions there's a race if two processors 604*0Sstevel@tonic-gate * are executing the dirty executable at the same time. If one 605*0Sstevel@tonic-gate * cleans the instruction as the other is executing it the second 606*0Sstevel@tonic-gate * processor will see a clean instruction when it comes through this 607*0Sstevel@tonic-gate * code and will return SIMU_ILLEGAL. To work around the race 608*0Sstevel@tonic-gate * this code will keep track of the last illegal instruction seen 609*0Sstevel@tonic-gate * by each lwp and will only take action if the illegal instruction 610*0Sstevel@tonic-gate * is repeatable. 611*0Sstevel@tonic-gate */ 612*0Sstevel@tonic-gate if (addr != mpcb->mpcb_illexcaddr || 613*0Sstevel@tonic-gate inst != mpcb->mpcb_illexcinsn) 614*0Sstevel@tonic-gate nomatch = 1; 615*0Sstevel@tonic-gate mpcb->mpcb_illexcaddr = addr; 616*0Sstevel@tonic-gate mpcb->mpcb_illexcinsn = inst; 617*0Sstevel@tonic-gate 618*0Sstevel@tonic-gate /* instruction fields */ 619*0Sstevel@tonic-gate i = (inst >> 13) & 0x1; 620*0Sstevel@tonic-gate rd = (inst >> 25) & 0x1f; 621*0Sstevel@tonic-gate optype = (inst >> 30) & 0x3; 622*0Sstevel@tonic-gate op3 = (inst >> 19) & 0x3f; 623*0Sstevel@tonic-gate ignor = (inst >> 5) & 0xff; 624*0Sstevel@tonic-gate if (IS_IBIT_SET(inst)) { 625*0Sstevel@tonic-gate asi = (uint32_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 626*0Sstevel@tonic-gate TSTATE_ASI_MASK); 627*0Sstevel@tonic-gate } else { 628*0Sstevel@tonic-gate asi = ignor; 629*0Sstevel@tonic-gate } 630*0Sstevel@tonic-gate 631*0Sstevel@tonic-gate if (IS_VIS1(optype, op3) || 632*0Sstevel@tonic-gate IS_PARTIAL_OR_SHORT_FLOAT_LD_ST(optype, op3, asi)) { 633*0Sstevel@tonic-gate klwp_t *lwp = ttolwp(curthread); 634*0Sstevel@tonic-gate kfpu_t *fp = lwptofpu(lwp); 635*0Sstevel@tonic-gate if (fpu_exists) { 636*0Sstevel@tonic-gate if (!(_fp_read_fprs() & FPRS_FEF)) 637*0Sstevel@tonic-gate fp_enable(); 638*0Sstevel@tonic-gate _fp_read_pfsr(&fp->fpu_fsr); 639*0Sstevel@tonic-gate } else { 640*0Sstevel@tonic-gate if (!fp->fpu_en) 641*0Sstevel@tonic-gate fp_enable(); 642*0Sstevel@tonic-gate } 643*0Sstevel@tonic-gate fp_precise(rp); 644*0Sstevel@tonic-gate return (SIMU_RETRY); 645*0Sstevel@tonic-gate } 646*0Sstevel@tonic-gate 647*0Sstevel@tonic-gate if (optype == 2 && op3 == IOP_V8_POPC) { 648*0Sstevel@tonic-gate return (simulate_popc(rp, badaddr, inst)); 649*0Sstevel@tonic-gate } else if (optype == 3 && op3 == IOP_V8_POPC) { 650*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 651*0Sstevel@tonic-gate } 652*0Sstevel@tonic-gate 653*0Sstevel@tonic-gate if (optype == OP_V8_LDSTR) { 654*0Sstevel@tonic-gate if (op3 == IOP_V8_LDQF || op3 == IOP_V8_LDQFA || 655*0Sstevel@tonic-gate op3 == IOP_V8_STQF || op3 == IOP_V8_STQFA) 656*0Sstevel@tonic-gate return (do_unaligned(rp, badaddr)); 657*0Sstevel@tonic-gate } 658*0Sstevel@tonic-gate 659*0Sstevel@tonic-gate if (nomatch) 660*0Sstevel@tonic-gate return (SIMU_RETRY); 661*0Sstevel@tonic-gate 662*0Sstevel@tonic-gate /* 663*0Sstevel@tonic-gate * The rest of the code handles v8 binaries with instructions 664*0Sstevel@tonic-gate * that have dirty (non-zero) bits in reserved or 'ignored' 665*0Sstevel@tonic-gate * fields; these will cause core dumps on v9 machines. 666*0Sstevel@tonic-gate * 667*0Sstevel@tonic-gate * We only clean dirty instructions in 32-bit programs (ie, v8) 668*0Sstevel@tonic-gate * running on SPARCv9 processors. True v9 programs are forced 669*0Sstevel@tonic-gate * to use the instruction set as intended. 670*0Sstevel@tonic-gate */ 671*0Sstevel@tonic-gate if (lwp_getdatamodel(curthread->t_lwp) != DATAMODEL_ILP32) 672*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 673*0Sstevel@tonic-gate switch (optype) { 674*0Sstevel@tonic-gate case OP_V8_BRANCH: 675*0Sstevel@tonic-gate case OP_V8_CALL: 676*0Sstevel@tonic-gate return (SIMU_ILLEGAL); /* these don't have ignored fields */ 677*0Sstevel@tonic-gate /*NOTREACHED*/ 678*0Sstevel@tonic-gate case OP_V8_ARITH: 679*0Sstevel@tonic-gate switch (op3) { 680*0Sstevel@tonic-gate case IOP_V8_RETT: 681*0Sstevel@tonic-gate if (rd == 0 && !(i == 0 && ignor)) 682*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 683*0Sstevel@tonic-gate if (rd) 684*0Sstevel@tonic-gate inst &= ~(0x1f << 25); 685*0Sstevel@tonic-gate if (i == 0 && ignor) 686*0Sstevel@tonic-gate inst &= ~(0xff << 5); 687*0Sstevel@tonic-gate break; 688*0Sstevel@tonic-gate case IOP_V8_TCC: 689*0Sstevel@tonic-gate if (i == 0 && ignor != 0) { 690*0Sstevel@tonic-gate inst &= ~(0xff << 5); 691*0Sstevel@tonic-gate } else if (i == 1 && (((inst >> 7) & 0x3f) != 0)) { 692*0Sstevel@tonic-gate inst &= ~(0x3f << 7); 693*0Sstevel@tonic-gate } else { 694*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 695*0Sstevel@tonic-gate } 696*0Sstevel@tonic-gate break; 697*0Sstevel@tonic-gate case IOP_V8_JMPL: 698*0Sstevel@tonic-gate case IOP_V8_RESTORE: 699*0Sstevel@tonic-gate case IOP_V8_SAVE: 700*0Sstevel@tonic-gate if ((op3 == IOP_V8_RETT && rd) || 701*0Sstevel@tonic-gate (i == 0 && ignor)) { 702*0Sstevel@tonic-gate inst &= ~(0xff << 5); 703*0Sstevel@tonic-gate } else { 704*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 705*0Sstevel@tonic-gate } 706*0Sstevel@tonic-gate break; 707*0Sstevel@tonic-gate case IOP_V8_FCMP: 708*0Sstevel@tonic-gate if (rd == 0) 709*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 710*0Sstevel@tonic-gate inst &= ~(0x1f << 25); 711*0Sstevel@tonic-gate break; 712*0Sstevel@tonic-gate case IOP_V8_RDASR: 713*0Sstevel@tonic-gate rs1 = ((inst >> 14) & 0x1f); 714*0Sstevel@tonic-gate if (rs1 == 1 || (rs1 >= 7 && rs1 <= 14)) { 715*0Sstevel@tonic-gate /* 716*0Sstevel@tonic-gate * The instruction specifies an invalid 717*0Sstevel@tonic-gate * state register - better bail out than 718*0Sstevel@tonic-gate * "fix" it when we're not sure what was 719*0Sstevel@tonic-gate * intended. 720*0Sstevel@tonic-gate */ 721*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 722*0Sstevel@tonic-gate } 723*0Sstevel@tonic-gate /* 724*0Sstevel@tonic-gate * Note: this case includes the 'stbar' 725*0Sstevel@tonic-gate * instruction (rs1 == 15 && i == 0). 726*0Sstevel@tonic-gate */ 727*0Sstevel@tonic-gate if ((ignor = (inst & 0x3fff)) != 0) 728*0Sstevel@tonic-gate inst &= ~(0x3fff); 729*0Sstevel@tonic-gate break; 730*0Sstevel@tonic-gate case IOP_V8_SRA: 731*0Sstevel@tonic-gate case IOP_V8_SRL: 732*0Sstevel@tonic-gate case IOP_V8_SLL: 733*0Sstevel@tonic-gate if (ignor == 0) 734*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 735*0Sstevel@tonic-gate inst &= ~(0xff << 5); 736*0Sstevel@tonic-gate break; 737*0Sstevel@tonic-gate case IOP_V8_ADD: 738*0Sstevel@tonic-gate case IOP_V8_AND: 739*0Sstevel@tonic-gate case IOP_V8_OR: 740*0Sstevel@tonic-gate case IOP_V8_XOR: 741*0Sstevel@tonic-gate case IOP_V8_SUB: 742*0Sstevel@tonic-gate case IOP_V8_ANDN: 743*0Sstevel@tonic-gate case IOP_V8_ORN: 744*0Sstevel@tonic-gate case IOP_V8_XNOR: 745*0Sstevel@tonic-gate case IOP_V8_ADDC: 746*0Sstevel@tonic-gate case IOP_V8_UMUL: 747*0Sstevel@tonic-gate case IOP_V8_SMUL: 748*0Sstevel@tonic-gate case IOP_V8_SUBC: 749*0Sstevel@tonic-gate case IOP_V8_UDIV: 750*0Sstevel@tonic-gate case IOP_V8_SDIV: 751*0Sstevel@tonic-gate case IOP_V8_ADDcc: 752*0Sstevel@tonic-gate case IOP_V8_ANDcc: 753*0Sstevel@tonic-gate case IOP_V8_ORcc: 754*0Sstevel@tonic-gate case IOP_V8_XORcc: 755*0Sstevel@tonic-gate case IOP_V8_SUBcc: 756*0Sstevel@tonic-gate case IOP_V8_ANDNcc: 757*0Sstevel@tonic-gate case IOP_V8_ORNcc: 758*0Sstevel@tonic-gate case IOP_V8_XNORcc: 759*0Sstevel@tonic-gate case IOP_V8_ADDCcc: 760*0Sstevel@tonic-gate case IOP_V8_UMULcc: 761*0Sstevel@tonic-gate case IOP_V8_SMULcc: 762*0Sstevel@tonic-gate case IOP_V8_SUBCcc: 763*0Sstevel@tonic-gate case IOP_V8_UDIVcc: 764*0Sstevel@tonic-gate case IOP_V8_SDIVcc: 765*0Sstevel@tonic-gate case IOP_V8_TADDcc: 766*0Sstevel@tonic-gate case IOP_V8_TSUBcc: 767*0Sstevel@tonic-gate case IOP_V8_TADDccTV: 768*0Sstevel@tonic-gate case IOP_V8_TSUBccTV: 769*0Sstevel@tonic-gate case IOP_V8_MULScc: 770*0Sstevel@tonic-gate case IOP_V8_WRASR: 771*0Sstevel@tonic-gate case IOP_V8_FLUSH: 772*0Sstevel@tonic-gate if (i != 0 || ignor == 0) 773*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 774*0Sstevel@tonic-gate inst &= ~(0xff << 5); 775*0Sstevel@tonic-gate break; 776*0Sstevel@tonic-gate default: 777*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 778*0Sstevel@tonic-gate } 779*0Sstevel@tonic-gate break; 780*0Sstevel@tonic-gate case OP_V8_LDSTR: 781*0Sstevel@tonic-gate switch (op3) { 782*0Sstevel@tonic-gate case IOP_V8_STFSR: 783*0Sstevel@tonic-gate case IOP_V8_LDFSR: 784*0Sstevel@tonic-gate if (rd == 0 && !(i == 0 && ignor)) 785*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 786*0Sstevel@tonic-gate if (rd) 787*0Sstevel@tonic-gate inst &= ~(0x1f << 25); 788*0Sstevel@tonic-gate if (i == 0 && ignor) 789*0Sstevel@tonic-gate inst &= ~(0xff << 5); 790*0Sstevel@tonic-gate break; 791*0Sstevel@tonic-gate default: 792*0Sstevel@tonic-gate if (optype == OP_V8_LDSTR && !IS_LDST_ALT(op3) && 793*0Sstevel@tonic-gate i == 0 && ignor) 794*0Sstevel@tonic-gate inst &= ~(0xff << 5); 795*0Sstevel@tonic-gate else 796*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 797*0Sstevel@tonic-gate break; 798*0Sstevel@tonic-gate } 799*0Sstevel@tonic-gate break; 800*0Sstevel@tonic-gate default: 801*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 802*0Sstevel@tonic-gate } 803*0Sstevel@tonic-gate 804*0Sstevel@tonic-gate as = p->p_as; 805*0Sstevel@tonic-gate 806*0Sstevel@tonic-gate AS_LOCK_ENTER(as, &as->a_lock, RW_READER); 807*0Sstevel@tonic-gate mapseg = as_findseg(as, (caddr_t)rp->r_pc, 0); 808*0Sstevel@tonic-gate ASSERT(mapseg != NULL); 809*0Sstevel@tonic-gate svd = (struct segvn_data *)mapseg->s_data; 810*0Sstevel@tonic-gate 811*0Sstevel@tonic-gate /* 812*0Sstevel@tonic-gate * We only create COW page for MAP_PRIVATE mappings. 813*0Sstevel@tonic-gate */ 814*0Sstevel@tonic-gate SEGVN_LOCK_ENTER(as, &svd->lock, RW_READER); 815*0Sstevel@tonic-gate if ((svd->type & MAP_TYPE) & MAP_SHARED) { 816*0Sstevel@tonic-gate SEGVN_LOCK_EXIT(as, &svd->lock); 817*0Sstevel@tonic-gate AS_LOCK_EXIT(as, &as->a_lock); 818*0Sstevel@tonic-gate return (SIMU_ILLEGAL); 819*0Sstevel@tonic-gate } 820*0Sstevel@tonic-gate SEGVN_LOCK_EXIT(as, &svd->lock); 821*0Sstevel@tonic-gate AS_LOCK_EXIT(as, &as->a_lock); 822*0Sstevel@tonic-gate 823*0Sstevel@tonic-gate /* 824*0Sstevel@tonic-gate * A "flush" instruction using the user PC's vaddr will not work 825*0Sstevel@tonic-gate * here, at least on Spitfire. Instead we create a temporary kernel 826*0Sstevel@tonic-gate * mapping to the user's text page, then modify and flush that. 827*0Sstevel@tonic-gate * Break COW by locking user page. 828*0Sstevel@tonic-gate */ 829*0Sstevel@tonic-gate if (as_fault(as->a_hat, as, (caddr_t)(rp->r_pc & PAGEMASK), PAGESIZE, 830*0Sstevel@tonic-gate F_SOFTLOCK, S_READ)) 831*0Sstevel@tonic-gate return (SIMU_FAULT); 832*0Sstevel@tonic-gate 833*0Sstevel@tonic-gate AS_LOCK_ENTER(as, &as->a_lock, RW_READER); 834*0Sstevel@tonic-gate pfnum = hat_getpfnum(as->a_hat, (caddr_t)rp->r_pc); 835*0Sstevel@tonic-gate AS_LOCK_EXIT(as, &as->a_lock); 836*0Sstevel@tonic-gate if (pf_is_memory(pfnum)) { 837*0Sstevel@tonic-gate pp = page_numtopp_nolock(pfnum); 838*0Sstevel@tonic-gate ASSERT(pp == NULL || PAGE_LOCKED(pp)); 839*0Sstevel@tonic-gate } else { 840*0Sstevel@tonic-gate (void) as_fault(as->a_hat, as, (caddr_t)(rp->r_pc & PAGEMASK), 841*0Sstevel@tonic-gate PAGESIZE, F_SOFTUNLOCK, S_READ); 842*0Sstevel@tonic-gate return (SIMU_FAULT); 843*0Sstevel@tonic-gate } 844*0Sstevel@tonic-gate 845*0Sstevel@tonic-gate AS_LOCK_ENTER(as, &as->a_lock, RW_READER); 846*0Sstevel@tonic-gate ka = ppmapin(pp, PROT_READ|PROT_WRITE, (caddr_t)rp->r_pc); 847*0Sstevel@tonic-gate *(uint_t *)(ka + (uintptr_t)(rp->r_pc % PAGESIZE)) = inst; 848*0Sstevel@tonic-gate doflush(ka + (uintptr_t)(rp->r_pc % PAGESIZE)); 849*0Sstevel@tonic-gate ppmapout(ka); 850*0Sstevel@tonic-gate AS_LOCK_EXIT(as, &as->a_lock); 851*0Sstevel@tonic-gate 852*0Sstevel@tonic-gate (void) as_fault(as->a_hat, as, (caddr_t)(rp->r_pc & PAGEMASK), 853*0Sstevel@tonic-gate PAGESIZE, F_SOFTUNLOCK, S_READ); 854*0Sstevel@tonic-gate return (SIMU_RETRY); 855*0Sstevel@tonic-gate } 856*0Sstevel@tonic-gate 857*0Sstevel@tonic-gate /* 858*0Sstevel@tonic-gate * Get the value of a register for instruction simulation 859*0Sstevel@tonic-gate * by using the regs or window structure pointers. 860*0Sstevel@tonic-gate * Return 0 for success, and -1 for failure. If there is a failure, 861*0Sstevel@tonic-gate * save the faulting address using badaddr pointer. 862*0Sstevel@tonic-gate * We have 64 bit globals and outs, and 32 or 64 bit ins and locals. 863*0Sstevel@tonic-gate * Don't truncate globals/outs for 32 bit programs, for v8+ support. 864*0Sstevel@tonic-gate */ 865*0Sstevel@tonic-gate int 866*0Sstevel@tonic-gate getreg(struct regs *rp, uint_t reg, uint64_t *val, caddr_t *badaddr) 867*0Sstevel@tonic-gate { 868*0Sstevel@tonic-gate uint64_t *rgs, *sp; 869*0Sstevel@tonic-gate int rv = 0; 870*0Sstevel@tonic-gate 871*0Sstevel@tonic-gate rgs = (uint64_t *)&rp->r_ps; /* globals and outs */ 872*0Sstevel@tonic-gate sp = (uint64_t *)rp->r_sp; /* ins and locals */ 873*0Sstevel@tonic-gate if (reg == 0) { 874*0Sstevel@tonic-gate *val = 0; 875*0Sstevel@tonic-gate } else if (reg < 16) { 876*0Sstevel@tonic-gate *val = rgs[reg]; 877*0Sstevel@tonic-gate } else if (IS_V9STACK(sp)) { 878*0Sstevel@tonic-gate uint64_t *rw = (uint64_t *)((uintptr_t)sp + V9BIAS64); 879*0Sstevel@tonic-gate uint64_t *addr = (uint64_t *)&rw[reg - 16]; 880*0Sstevel@tonic-gate uint64_t res; 881*0Sstevel@tonic-gate 882*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) { 883*0Sstevel@tonic-gate if (fuword64_nowatch(addr, &res) == -1) { 884*0Sstevel@tonic-gate *badaddr = (caddr_t)addr; 885*0Sstevel@tonic-gate rv = -1; 886*0Sstevel@tonic-gate } 887*0Sstevel@tonic-gate } else { 888*0Sstevel@tonic-gate res = *addr; 889*0Sstevel@tonic-gate } 890*0Sstevel@tonic-gate *val = res; 891*0Sstevel@tonic-gate } else { 892*0Sstevel@tonic-gate uint32_t *rw = (uint32_t *)(caddr32_t)sp; 893*0Sstevel@tonic-gate uint32_t *addr = (uint32_t *)&rw[reg - 16]; 894*0Sstevel@tonic-gate uint32_t res; 895*0Sstevel@tonic-gate 896*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) { 897*0Sstevel@tonic-gate if (fuword32_nowatch(addr, &res) == -1) { 898*0Sstevel@tonic-gate *badaddr = (caddr_t)addr; 899*0Sstevel@tonic-gate rv = -1; 900*0Sstevel@tonic-gate } 901*0Sstevel@tonic-gate } else { 902*0Sstevel@tonic-gate res = *addr; 903*0Sstevel@tonic-gate } 904*0Sstevel@tonic-gate *val = (uint64_t)res; 905*0Sstevel@tonic-gate } 906*0Sstevel@tonic-gate return (rv); 907*0Sstevel@tonic-gate } 908*0Sstevel@tonic-gate 909*0Sstevel@tonic-gate /* 910*0Sstevel@tonic-gate * Set the value of a register after instruction simulation 911*0Sstevel@tonic-gate * by using the regs or window structure pointers. 912*0Sstevel@tonic-gate * Return 0 for succes -1 failure. 913*0Sstevel@tonic-gate * save the faulting address using badaddr pointer. 914*0Sstevel@tonic-gate * We have 64 bit globals and outs, and 32 or 64 bit ins and locals. 915*0Sstevel@tonic-gate * Don't truncate globals/outs for 32 bit programs, for v8+ support. 916*0Sstevel@tonic-gate */ 917*0Sstevel@tonic-gate int 918*0Sstevel@tonic-gate putreg(uint64_t *data, struct regs *rp, uint_t reg, caddr_t *badaddr) 919*0Sstevel@tonic-gate { 920*0Sstevel@tonic-gate uint64_t *rgs, *sp; 921*0Sstevel@tonic-gate int rv = 0; 922*0Sstevel@tonic-gate 923*0Sstevel@tonic-gate rgs = (uint64_t *)&rp->r_ps; /* globals and outs */ 924*0Sstevel@tonic-gate sp = (uint64_t *)rp->r_sp; /* ins and locals */ 925*0Sstevel@tonic-gate if (reg == 0) { 926*0Sstevel@tonic-gate return (0); 927*0Sstevel@tonic-gate } else if (reg < 16) { 928*0Sstevel@tonic-gate rgs[reg] = *data; 929*0Sstevel@tonic-gate } else if (IS_V9STACK(sp)) { 930*0Sstevel@tonic-gate uint64_t *rw = (uint64_t *)((uintptr_t)sp + V9BIAS64); 931*0Sstevel@tonic-gate uint64_t *addr = (uint64_t *)&rw[reg - 16]; 932*0Sstevel@tonic-gate uint64_t res; 933*0Sstevel@tonic-gate 934*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) { 935*0Sstevel@tonic-gate struct machpcb *mpcb = lwptompcb(curthread->t_lwp); 936*0Sstevel@tonic-gate 937*0Sstevel@tonic-gate res = *data; 938*0Sstevel@tonic-gate if (suword64_nowatch(addr, res) != 0) { 939*0Sstevel@tonic-gate *badaddr = (caddr_t)addr; 940*0Sstevel@tonic-gate rv = -1; 941*0Sstevel@tonic-gate } 942*0Sstevel@tonic-gate /* 943*0Sstevel@tonic-gate * We have changed a local or in register; 944*0Sstevel@tonic-gate * nuke the watchpoint return windows. 945*0Sstevel@tonic-gate */ 946*0Sstevel@tonic-gate mpcb->mpcb_rsp[0] = NULL; 947*0Sstevel@tonic-gate mpcb->mpcb_rsp[1] = NULL; 948*0Sstevel@tonic-gate } else { 949*0Sstevel@tonic-gate res = *data; 950*0Sstevel@tonic-gate *addr = res; 951*0Sstevel@tonic-gate } 952*0Sstevel@tonic-gate } else { 953*0Sstevel@tonic-gate uint32_t *rw = (uint32_t *)(caddr32_t)sp; 954*0Sstevel@tonic-gate uint32_t *addr = (uint32_t *)&rw[reg - 16]; 955*0Sstevel@tonic-gate uint32_t res; 956*0Sstevel@tonic-gate 957*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) { 958*0Sstevel@tonic-gate struct machpcb *mpcb = lwptompcb(curthread->t_lwp); 959*0Sstevel@tonic-gate 960*0Sstevel@tonic-gate res = (uint_t)*data; 961*0Sstevel@tonic-gate if (suword32_nowatch(addr, res) != 0) { 962*0Sstevel@tonic-gate *badaddr = (caddr_t)addr; 963*0Sstevel@tonic-gate rv = -1; 964*0Sstevel@tonic-gate } 965*0Sstevel@tonic-gate /* 966*0Sstevel@tonic-gate * We have changed a local or in register; 967*0Sstevel@tonic-gate * nuke the watchpoint return windows. 968*0Sstevel@tonic-gate */ 969*0Sstevel@tonic-gate mpcb->mpcb_rsp[0] = NULL; 970*0Sstevel@tonic-gate mpcb->mpcb_rsp[1] = NULL; 971*0Sstevel@tonic-gate 972*0Sstevel@tonic-gate } else { 973*0Sstevel@tonic-gate res = (uint_t)*data; 974*0Sstevel@tonic-gate *addr = res; 975*0Sstevel@tonic-gate } 976*0Sstevel@tonic-gate } 977*0Sstevel@tonic-gate return (rv); 978*0Sstevel@tonic-gate } 979*0Sstevel@tonic-gate 980*0Sstevel@tonic-gate /* 981*0Sstevel@tonic-gate * Calculate a memory reference address from instruction 982*0Sstevel@tonic-gate * operands, used to return the address of a fault, instead 983*0Sstevel@tonic-gate * of the instruction when an error occurs. This is code that is 984*0Sstevel@tonic-gate * common with most of the routines that simulate instructions. 985*0Sstevel@tonic-gate */ 986*0Sstevel@tonic-gate int 987*0Sstevel@tonic-gate calc_memaddr(struct regs *rp, caddr_t *badaddr) 988*0Sstevel@tonic-gate { 989*0Sstevel@tonic-gate uint_t inst; 990*0Sstevel@tonic-gate uint_t rd, rs1, rs2; 991*0Sstevel@tonic-gate int sz; 992*0Sstevel@tonic-gate int immflg; 993*0Sstevel@tonic-gate int floatflg; 994*0Sstevel@tonic-gate caddr_t addr; 995*0Sstevel@tonic-gate uint64_t val; 996*0Sstevel@tonic-gate 997*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) 998*0Sstevel@tonic-gate inst = fetch_user_instr((caddr_t)rp->r_pc); 999*0Sstevel@tonic-gate else 1000*0Sstevel@tonic-gate inst = *(uint_t *)rp->r_pc; 1001*0Sstevel@tonic-gate 1002*0Sstevel@tonic-gate rd = (inst >> 25) & 0x1f; 1003*0Sstevel@tonic-gate rs1 = (inst >> 14) & 0x1f; 1004*0Sstevel@tonic-gate rs2 = inst & 0x1f; 1005*0Sstevel@tonic-gate floatflg = (inst >> 24) & 1; 1006*0Sstevel@tonic-gate immflg = (inst >> 13) & 1; 1007*0Sstevel@tonic-gate 1008*0Sstevel@tonic-gate if (floatflg) { 1009*0Sstevel@tonic-gate switch ((inst >> 19) & 3) { /* map size bits to a number */ 1010*0Sstevel@tonic-gate case 0: sz = 4; break; /* ldf/stf */ 1011*0Sstevel@tonic-gate case 1: return (0); /* ld[x]fsr/st[x]fsr */ 1012*0Sstevel@tonic-gate case 2: sz = 16; break; /* ldqf/stqf */ 1013*0Sstevel@tonic-gate case 3: sz = 8; break; /* lddf/stdf */ 1014*0Sstevel@tonic-gate } 1015*0Sstevel@tonic-gate /* 1016*0Sstevel@tonic-gate * Fix to access extra double register encoding plus 1017*0Sstevel@tonic-gate * compensate to access the correct fpu_dreg. 1018*0Sstevel@tonic-gate */ 1019*0Sstevel@tonic-gate if (sz > 4) { 1020*0Sstevel@tonic-gate if ((rd & 1) == 1) 1021*0Sstevel@tonic-gate rd = (rd & 0x1e) | 0x20; 1022*0Sstevel@tonic-gate rd = rd >> 1; 1023*0Sstevel@tonic-gate } 1024*0Sstevel@tonic-gate } else { 1025*0Sstevel@tonic-gate switch ((inst >> 19) & 0xf) { /* map size bits to a number */ 1026*0Sstevel@tonic-gate case 0: /* lduw */ 1027*0Sstevel@tonic-gate case 4: /* stw */ 1028*0Sstevel@tonic-gate case 8: /* ldsw */ 1029*0Sstevel@tonic-gate case 0xf: /* swap */ 1030*0Sstevel@tonic-gate sz = 4; break; 1031*0Sstevel@tonic-gate case 1: /* ldub */ 1032*0Sstevel@tonic-gate case 5: /* stb */ 1033*0Sstevel@tonic-gate case 9: /* ldsb */ 1034*0Sstevel@tonic-gate case 0xd: /* ldstub */ 1035*0Sstevel@tonic-gate sz = 1; break; 1036*0Sstevel@tonic-gate case 2: /* lduh */ 1037*0Sstevel@tonic-gate case 6: /* sth */ 1038*0Sstevel@tonic-gate case 0xa: /* ldsh */ 1039*0Sstevel@tonic-gate sz = 2; break; 1040*0Sstevel@tonic-gate case 3: /* ldd */ 1041*0Sstevel@tonic-gate case 7: /* std */ 1042*0Sstevel@tonic-gate case 0xb: /* ldx */ 1043*0Sstevel@tonic-gate case 0xe: /* stx */ 1044*0Sstevel@tonic-gate sz = 8; break; 1045*0Sstevel@tonic-gate } 1046*0Sstevel@tonic-gate } 1047*0Sstevel@tonic-gate 1048*0Sstevel@tonic-gate if (USERMODE(rp->r_tstate)) 1049*0Sstevel@tonic-gate (void) flush_user_windows_to_stack(NULL); 1050*0Sstevel@tonic-gate else 1051*0Sstevel@tonic-gate flush_windows(); 1052*0Sstevel@tonic-gate 1053*0Sstevel@tonic-gate if (getreg(rp, rs1, &val, badaddr)) 1054*0Sstevel@tonic-gate return (SIMU_FAULT); 1055*0Sstevel@tonic-gate addr = (caddr_t)val; 1056*0Sstevel@tonic-gate 1057*0Sstevel@tonic-gate /* check immediate bit and use immediate field or reg (rs2) */ 1058*0Sstevel@tonic-gate if (immflg) { 1059*0Sstevel@tonic-gate int imm; 1060*0Sstevel@tonic-gate imm = inst & 0x1fff; /* mask out immediate field */ 1061*0Sstevel@tonic-gate imm <<= 19; /* sign extend it */ 1062*0Sstevel@tonic-gate imm >>= 19; 1063*0Sstevel@tonic-gate addr += imm; /* compute address */ 1064*0Sstevel@tonic-gate } else { 1065*0Sstevel@tonic-gate if (getreg(rp, rs2, &val, badaddr)) 1066*0Sstevel@tonic-gate return (SIMU_FAULT); 1067*0Sstevel@tonic-gate addr += val; 1068*0Sstevel@tonic-gate } 1069*0Sstevel@tonic-gate 1070*0Sstevel@tonic-gate /* 1071*0Sstevel@tonic-gate * If this is a 32-bit program, chop the address accordingly. 1072*0Sstevel@tonic-gate */ 1073*0Sstevel@tonic-gate if (curproc->p_model == DATAMODEL_ILP32 && 1074*0Sstevel@tonic-gate USERMODE(rp->r_tstate)) 1075*0Sstevel@tonic-gate addr = (caddr_t)(caddr32_t)addr; 1076*0Sstevel@tonic-gate 1077*0Sstevel@tonic-gate *badaddr = addr; 1078*0Sstevel@tonic-gate return ((uintptr_t)addr & (sz - 1) ? SIMU_UNALIGN : SIMU_SUCCESS); 1079*0Sstevel@tonic-gate } 1080*0Sstevel@tonic-gate 1081*0Sstevel@tonic-gate /* 1082*0Sstevel@tonic-gate * Return the size of a load or store instruction (1, 2, 4, 8, 16, 64). 1083*0Sstevel@tonic-gate * Also compute the precise address by instruction disassembly. 1084*0Sstevel@tonic-gate * (v9 page faults only provide the page address via the hardware.) 1085*0Sstevel@tonic-gate * Return 0 on failure (not a load or store instruction). 1086*0Sstevel@tonic-gate */ 1087*0Sstevel@tonic-gate int 1088*0Sstevel@tonic-gate instr_size(struct regs *rp, caddr_t *addrp, enum seg_rw rdwr) 1089*0Sstevel@tonic-gate { 1090*0Sstevel@tonic-gate uint_t inst, op3, asi; 1091*0Sstevel@tonic-gate uint_t rd, rs1, rs2; 1092*0Sstevel@tonic-gate int sz = 0; 1093*0Sstevel@tonic-gate int immflg; 1094*0Sstevel@tonic-gate int floatflg; 1095*0Sstevel@tonic-gate caddr_t addr; 1096*0Sstevel@tonic-gate caddr_t badaddr; 1097*0Sstevel@tonic-gate uint64_t val; 1098*0Sstevel@tonic-gate 1099*0Sstevel@tonic-gate if (rdwr == S_EXEC) { 1100*0Sstevel@tonic-gate *addrp = (caddr_t)rp->r_pc; 1101*0Sstevel@tonic-gate return (4); 1102*0Sstevel@tonic-gate } 1103*0Sstevel@tonic-gate 1104*0Sstevel@tonic-gate /* 1105*0Sstevel@tonic-gate * Fetch the instruction from user-level. 1106*0Sstevel@tonic-gate * We would like to assert this: 1107*0Sstevel@tonic-gate * ASSERT(USERMODE(rp->r_tstate)); 1108*0Sstevel@tonic-gate * but we can't because we can reach this point from a 1109*0Sstevel@tonic-gate * register window underflow/overflow and the v9 wbuf 1110*0Sstevel@tonic-gate * traps call trap() with T_USER even though r_tstate 1111*0Sstevel@tonic-gate * indicates a system trap, not a user trap. 1112*0Sstevel@tonic-gate */ 1113*0Sstevel@tonic-gate inst = fetch_user_instr((caddr_t)rp->r_pc); 1114*0Sstevel@tonic-gate 1115*0Sstevel@tonic-gate op3 = (inst >> 19) & 0x3f; 1116*0Sstevel@tonic-gate rd = (inst >> 25) & 0x1f; 1117*0Sstevel@tonic-gate rs1 = (inst >> 14) & 0x1f; 1118*0Sstevel@tonic-gate rs2 = inst & 0x1f; 1119*0Sstevel@tonic-gate floatflg = (inst >> 24) & 1; 1120*0Sstevel@tonic-gate immflg = (inst >> 13) & 1; 1121*0Sstevel@tonic-gate 1122*0Sstevel@tonic-gate /* if not load or store do nothing. can't happen? */ 1123*0Sstevel@tonic-gate if ((inst >> 30) != 3) 1124*0Sstevel@tonic-gate return (0); 1125*0Sstevel@tonic-gate 1126*0Sstevel@tonic-gate if (immflg) 1127*0Sstevel@tonic-gate asi = (uint_t)((rp->r_tstate >> TSTATE_ASI_SHIFT) & 1128*0Sstevel@tonic-gate TSTATE_ASI_MASK); 1129*0Sstevel@tonic-gate else 1130*0Sstevel@tonic-gate asi = (inst >> 5) & 0xff; 1131*0Sstevel@tonic-gate 1132*0Sstevel@tonic-gate if (floatflg) { 1133*0Sstevel@tonic-gate /* check for ld/st alternate and highest defined V9 asi */ 1134*0Sstevel@tonic-gate if ((op3 & 0x30) == 0x30 && asi > ASI_SNFL) { 1135*0Sstevel@tonic-gate sz = extended_asi_size(asi); 1136*0Sstevel@tonic-gate } else { 1137*0Sstevel@tonic-gate switch (op3 & 3) { 1138*0Sstevel@tonic-gate case 0: 1139*0Sstevel@tonic-gate sz = 4; /* ldf/stf/cas */ 1140*0Sstevel@tonic-gate break; 1141*0Sstevel@tonic-gate case 1: 1142*0Sstevel@tonic-gate if (rd == 0) 1143*0Sstevel@tonic-gate sz = 4; /* ldfsr/stfsr */ 1144*0Sstevel@tonic-gate else 1145*0Sstevel@tonic-gate sz = 8; /* ldxfsr/stxfsr */ 1146*0Sstevel@tonic-gate break; 1147*0Sstevel@tonic-gate case 2: 1148*0Sstevel@tonic-gate if (op3 == 0x3e) 1149*0Sstevel@tonic-gate sz = 8; /* casx */ 1150*0Sstevel@tonic-gate else 1151*0Sstevel@tonic-gate sz = 16; /* ldqf/stqf */ 1152*0Sstevel@tonic-gate break; 1153*0Sstevel@tonic-gate case 3: 1154*0Sstevel@tonic-gate sz = 8; /* lddf/stdf */ 1155*0Sstevel@tonic-gate break; 1156*0Sstevel@tonic-gate } 1157*0Sstevel@tonic-gate } 1158*0Sstevel@tonic-gate } else { 1159*0Sstevel@tonic-gate switch (op3 & 0xf) { /* map size bits to a number */ 1160*0Sstevel@tonic-gate case 0: /* lduw */ 1161*0Sstevel@tonic-gate case 4: /* stw */ 1162*0Sstevel@tonic-gate case 8: /* ldsw */ 1163*0Sstevel@tonic-gate case 0xf: /* swap */ 1164*0Sstevel@tonic-gate sz = 4; break; 1165*0Sstevel@tonic-gate case 1: /* ldub */ 1166*0Sstevel@tonic-gate case 5: /* stb */ 1167*0Sstevel@tonic-gate case 9: /* ldsb */ 1168*0Sstevel@tonic-gate case 0xd: /* ldstub */ 1169*0Sstevel@tonic-gate sz = 1; break; 1170*0Sstevel@tonic-gate case 2: /* lduh */ 1171*0Sstevel@tonic-gate case 6: /* sth */ 1172*0Sstevel@tonic-gate case 0xa: /* ldsh */ 1173*0Sstevel@tonic-gate sz = 2; break; 1174*0Sstevel@tonic-gate case 3: /* ldd */ 1175*0Sstevel@tonic-gate case 7: /* std */ 1176*0Sstevel@tonic-gate case 0xb: /* ldx */ 1177*0Sstevel@tonic-gate case 0xe: /* stx */ 1178*0Sstevel@tonic-gate sz = 8; break; 1179*0Sstevel@tonic-gate } 1180*0Sstevel@tonic-gate } 1181*0Sstevel@tonic-gate 1182*0Sstevel@tonic-gate if (sz == 0) /* can't happen? */ 1183*0Sstevel@tonic-gate return (0); 1184*0Sstevel@tonic-gate (void) flush_user_windows_to_stack(NULL); 1185*0Sstevel@tonic-gate 1186*0Sstevel@tonic-gate if (getreg(rp, rs1, &val, &badaddr)) 1187*0Sstevel@tonic-gate return (0); 1188*0Sstevel@tonic-gate addr = (caddr_t)val; 1189*0Sstevel@tonic-gate 1190*0Sstevel@tonic-gate /* cas/casx don't use rs2 / simm13 to compute the address */ 1191*0Sstevel@tonic-gate if ((op3 & 0x3d) != 0x3c) { 1192*0Sstevel@tonic-gate /* check immediate bit and use immediate field or reg (rs2) */ 1193*0Sstevel@tonic-gate if (immflg) { 1194*0Sstevel@tonic-gate int imm; 1195*0Sstevel@tonic-gate imm = inst & 0x1fff; /* mask out immediate field */ 1196*0Sstevel@tonic-gate imm <<= 19; /* sign extend it */ 1197*0Sstevel@tonic-gate imm >>= 19; 1198*0Sstevel@tonic-gate addr += imm; /* compute address */ 1199*0Sstevel@tonic-gate } else { 1200*0Sstevel@tonic-gate /* 1201*0Sstevel@tonic-gate * asi's in the 0xCx range are partial store 1202*0Sstevel@tonic-gate * instructions. For these, rs2 is a mask, not part of 1203*0Sstevel@tonic-gate * the address. 1204*0Sstevel@tonic-gate */ 1205*0Sstevel@tonic-gate if (!(floatflg && (asi & 0xf0) == 0xc0)) { 1206*0Sstevel@tonic-gate if (getreg(rp, rs2, &val, &badaddr)) 1207*0Sstevel@tonic-gate return (0); 1208*0Sstevel@tonic-gate addr += val; 1209*0Sstevel@tonic-gate } 1210*0Sstevel@tonic-gate } 1211*0Sstevel@tonic-gate } 1212*0Sstevel@tonic-gate 1213*0Sstevel@tonic-gate /* 1214*0Sstevel@tonic-gate * If this is a 32-bit program, chop the address accordingly. 1215*0Sstevel@tonic-gate */ 1216*0Sstevel@tonic-gate if (curproc->p_model == DATAMODEL_ILP32) 1217*0Sstevel@tonic-gate addr = (caddr_t)(caddr32_t)addr; 1218*0Sstevel@tonic-gate 1219*0Sstevel@tonic-gate *addrp = addr; 1220*0Sstevel@tonic-gate ASSERT(sz != 0); 1221*0Sstevel@tonic-gate return (sz); 1222*0Sstevel@tonic-gate } 1223*0Sstevel@tonic-gate 1224*0Sstevel@tonic-gate /* 1225*0Sstevel@tonic-gate * Fetch an instruction from user-level. 1226*0Sstevel@tonic-gate * Deal with watchpoints, if they are in effect. 1227*0Sstevel@tonic-gate */ 1228*0Sstevel@tonic-gate int32_t 1229*0Sstevel@tonic-gate fetch_user_instr(caddr_t vaddr) 1230*0Sstevel@tonic-gate { 1231*0Sstevel@tonic-gate proc_t *p = curproc; 1232*0Sstevel@tonic-gate int32_t instr; 1233*0Sstevel@tonic-gate 1234*0Sstevel@tonic-gate /* 1235*0Sstevel@tonic-gate * If this is a 32-bit program, chop the address accordingly. 1236*0Sstevel@tonic-gate */ 1237*0Sstevel@tonic-gate if (p->p_model == DATAMODEL_ILP32) 1238*0Sstevel@tonic-gate vaddr = (caddr_t)(caddr32_t)vaddr; 1239*0Sstevel@tonic-gate 1240*0Sstevel@tonic-gate if (fuword32_nowatch(vaddr, (uint32_t *)&instr) == -1) 1241*0Sstevel@tonic-gate instr = -1; 1242*0Sstevel@tonic-gate 1243*0Sstevel@tonic-gate return (instr); 1244*0Sstevel@tonic-gate } 1245