1*1414Scindi /* 2*1414Scindi * CDDL HEADER START 3*1414Scindi * 4*1414Scindi * The contents of this file are subject to the terms of the 5*1414Scindi * Common Development and Distribution License, Version 1.0 only 6*1414Scindi * (the "License"). You may not use this file except in compliance 7*1414Scindi * with the License. 8*1414Scindi * 9*1414Scindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*1414Scindi * or http://www.opensolaris.org/os/licensing. 11*1414Scindi * See the License for the specific language governing permissions 12*1414Scindi * and limitations under the License. 13*1414Scindi * 14*1414Scindi * When distributing Covered Code, include this CDDL HEADER in each 15*1414Scindi * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*1414Scindi * If applicable, add the following below this CDDL HEADER, with the 17*1414Scindi * fields enclosed by brackets "[]" replaced with your own identifying 18*1414Scindi * information: Portions Copyright [yyyy] [name of copyright owner] 19*1414Scindi * 20*1414Scindi * CDDL HEADER END 21*1414Scindi * 22*1414Scindi * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23*1414Scindi * Use is subject to license terms. 24*1414Scindi */ 25*1414Scindi 26*1414Scindi #ifndef _SYS_MCA_X86_H 27*1414Scindi #define _SYS_MCA_X86_H 28*1414Scindi 29*1414Scindi #pragma ident "%Z%%M% %I% %E% SMI" 30*1414Scindi 31*1414Scindi /* 32*1414Scindi * Constants for the Memory Check Architecture as implemented on generic x86 33*1414Scindi * CPUs. 34*1414Scindi */ 35*1414Scindi 36*1414Scindi #ifdef __cplusplus 37*1414Scindi extern "C" { 38*1414Scindi #endif 39*1414Scindi 40*1414Scindi /* 41*1414Scindi * Intel has defined a number of MSRs as part of the IA32 architecture. The 42*1414Scindi * MCG registers are part of that set, as are the first four banks (0-3) as 43*1414Scindi * implemented by the P4 processor. Bank MSRs were laid out slightly 44*1414Scindi * differently on the P6 family of processors, and thus have their own #defines 45*1414Scindi * following the architecture-generic ones. 46*1414Scindi */ 47*1414Scindi #define IA32_MSR_MCG_CAP 0x179 48*1414Scindi #define IA32_MSR_MCG_STATUS 0x17a 49*1414Scindi #define IA32_MSR_MCG_CTL 0x17b 50*1414Scindi 51*1414Scindi #define MCG_CAP_COUNT_MASK 0x000000ffULL 52*1414Scindi #define MCG_CAP_CTL_P 0x00000100ULL 53*1414Scindi #define MCG_CAP_EXT_P 0x00000200ULL 54*1414Scindi #define MCG_CAP_EXT_CNT_MASK 0x00ff0000ULL 55*1414Scindi #define MCG_CAP_EXT_CNT_SHIFT 16 56*1414Scindi 57*1414Scindi #define MCG_STATUS_RIPV 0x01 58*1414Scindi #define MCG_STATUS_EIPV 0x02 59*1414Scindi #define MCG_STATUS_MCIP 0x04 60*1414Scindi 61*1414Scindi #define IA32_MSR_MC0_CTL 0x400 62*1414Scindi #define IA32_MSR_MC0_STATUS 0x401 63*1414Scindi #define IA32_MSR_MC0_ADDR 0x402 64*1414Scindi #define IA32_MSR_MC0_MISC 0x403 65*1414Scindi 66*1414Scindi #define IA32_MSR_MC1_CTL 0x404 67*1414Scindi #define IA32_MSR_MC1_STATUS 0x405 68*1414Scindi #define IA32_MSR_MC1_ADDR 0x406 69*1414Scindi #define IA32_MSR_MC1_MISC 0x407 70*1414Scindi 71*1414Scindi #define IA32_MSR_MC2_CTL 0x408 72*1414Scindi #define IA32_MSR_MC2_STATUS 0x409 73*1414Scindi #define IA32_MSR_MC2_ADDR 0x40a 74*1414Scindi #define IA32_MSR_MC2_MISC 0x40b 75*1414Scindi 76*1414Scindi #define IA32_MSR_MC3_CTL 0x40c 77*1414Scindi #define IA32_MSR_MC3_STATUS 0x40d 78*1414Scindi #define IA32_MSR_MC3_ADDR 0x40e 79*1414Scindi #define IA32_MSR_MC3_MISC 0x40f 80*1414Scindi 81*1414Scindi #define MSR_MC_STATUS_VAL 0x8000000000000000ULL 82*1414Scindi #define MSR_MC_STATUS_O 0x4000000000000000ULL 83*1414Scindi #define MSR_MC_STATUS_UC 0x2000000000000000ULL 84*1414Scindi #define MSR_MC_STATUS_EN 0x1000000000000000ULL 85*1414Scindi #define MSR_MC_STATUS_MISCV 0x0800000000000000ULL 86*1414Scindi #define MSR_MC_STATUS_ADDRV 0x0400000000000000ULL 87*1414Scindi #define MSR_MC_STATUS_PCC 0x0200000000000000ULL 88*1414Scindi #define MSR_MC_STATUS_OTHER_MASK 0x01ffffff00000000ULL 89*1414Scindi #define MSR_MC_STATUS_OTHER_SHIFT 32 90*1414Scindi #define MSR_MC_STATUS_MSERR_MASK 0x00000000ffff0000ULL 91*1414Scindi #define MSR_MC_STATUS_MSERR_SHIFT 16 92*1414Scindi #define MSR_MC_STATUS_MCAERR_MASK 0x000000000000ffffULL 93*1414Scindi 94*1414Scindi /* 95*1414Scindi * P6 MCA bank MSRs. Note that the ordering is 0, 1, 2, *4*, 3. Yes, really. 96*1414Scindi */ 97*1414Scindi #define P6_MSR_MC0_CTL 0x400 98*1414Scindi #define P6_MSR_MC0_STATUS 0x401 99*1414Scindi #define P6_MSR_MC0_ADDR 0x402 100*1414Scindi #define P6_MSR_MC0_MISC 0x403 101*1414Scindi 102*1414Scindi #define P6_MSR_MC1_CTL 0x404 103*1414Scindi #define P6_MSR_MC1_STATUS 0x405 104*1414Scindi #define P6_MSR_MC1_ADDR 0x406 105*1414Scindi #define P6_MSR_MC1_MISC 0x407 106*1414Scindi 107*1414Scindi #define P6_MSR_MC2_CTL 0x408 108*1414Scindi #define P6_MSR_MC2_STATUS 0x409 109*1414Scindi #define P6_MSR_MC2_ADDR 0x40a 110*1414Scindi #define P6_MSR_MC2_MISC 0x40b 111*1414Scindi 112*1414Scindi #define P6_MSR_MC4_CTL 0x40c 113*1414Scindi #define P6_MSR_MC4_STATUS 0x40d 114*1414Scindi #define P6_MSR_MC4_ADDR 0x40e 115*1414Scindi #define P6_MSR_MC4_MISC 0x40f 116*1414Scindi 117*1414Scindi #define P6_MSR_MC3_CTL 0x410 118*1414Scindi #define P6_MSR_MC3_STATUS 0x411 119*1414Scindi #define P6_MSR_MC3_ADDR 0x412 120*1414Scindi #define P6_MSR_MC3_MISC 0x413 121*1414Scindi 122*1414Scindi #ifdef __cplusplus 123*1414Scindi } 124*1414Scindi #endif 125*1414Scindi 126*1414Scindi #endif /* _SYS_MCA_X86_H */ 127