11414Scindi /* 21414Scindi * CDDL HEADER START 31414Scindi * 41414Scindi * The contents of this file are subject to the terms of the 55254Sgavinm * Common Development and Distribution License (the "License"). 65254Sgavinm * You may not use this file except in compliance with the License. 71414Scindi * 81414Scindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 91414Scindi * or http://www.opensolaris.org/os/licensing. 101414Scindi * See the License for the specific language governing permissions 111414Scindi * and limitations under the License. 121414Scindi * 131414Scindi * When distributing Covered Code, include this CDDL HEADER in each 141414Scindi * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 151414Scindi * If applicable, add the following below this CDDL HEADER, with the 161414Scindi * fields enclosed by brackets "[]" replaced with your own identifying 171414Scindi * information: Portions Copyright [yyyy] [name of copyright owner] 181414Scindi * 191414Scindi * CDDL HEADER END 201414Scindi * 217349SAdrian.Frost@Sun.COM * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 221414Scindi * Use is subject to license terms. 231414Scindi */ 241414Scindi 251414Scindi #ifndef _SYS_MCA_X86_H 261414Scindi #define _SYS_MCA_X86_H 271414Scindi 281414Scindi /* 291414Scindi * Constants for the Memory Check Architecture as implemented on generic x86 301414Scindi * CPUs. 311414Scindi */ 321414Scindi 335254Sgavinm #include <sys/types.h> 345254Sgavinm #include <sys/isa_defs.h> 355254Sgavinm 361414Scindi #ifdef __cplusplus 371414Scindi extern "C" { 381414Scindi #endif 391414Scindi 401414Scindi /* 415254Sgavinm * Architectural MSRs from the IA-32 Software Developer's Manual - IA32_MSR_* 421414Scindi */ 431414Scindi #define IA32_MSR_MCG_CAP 0x179 441414Scindi #define IA32_MSR_MCG_STATUS 0x17a 451414Scindi #define IA32_MSR_MCG_CTL 0x17b 461414Scindi 471414Scindi #define MCG_CAP_CTL_P 0x00000100ULL 481414Scindi #define MCG_CAP_EXT_P 0x00000200ULL 495254Sgavinm #define MCG_CAP_TES_P 0x00000800ULL 50*7415SAdrian.Frost@Sun.COM #define MCG_CAP_CTL2_P 0x00000400ULL 515254Sgavinm 525254Sgavinm #define MCG_CAP_COUNT_MASK 0x000000ffULL 535254Sgavinm #define MCG_CAP_COUNT(cap) ((cap) & MCG_CAP_COUNT_MASK) 545254Sgavinm 551414Scindi #define MCG_CAP_EXT_CNT_MASK 0x00ff0000ULL 561414Scindi #define MCG_CAP_EXT_CNT_SHIFT 16 575254Sgavinm #define MCG_CAP_EXT_CNT(cap) \ 585254Sgavinm (((cap) & MCG_CAP_EXT_CNT_MASK) >> MCG_CAP_EXT_CNT_SHIFT) 591414Scindi 601414Scindi #define MCG_STATUS_RIPV 0x01 611414Scindi #define MCG_STATUS_EIPV 0x02 621414Scindi #define MCG_STATUS_MCIP 0x04 631414Scindi 645254Sgavinm /* 655254Sgavinm * There are as many error detector "banks" as indicated by 665254Sgavinm * IA32_MSR_MCG_CAP.COUNT. Each bank has a minimum of 3 associated 675254Sgavinm * registers (MCi_CTL, MCi_STATUS, and MCi_ADDR) and some banks 685254Sgavinm * may implement a fourth (MCi_MISC) which should only be read 695254Sgavinm * when MCi_STATUS.MISCV indicates that it exists and has valid data. 705254Sgavinm * 715254Sgavinm * The first bank features at MSR offsets 0x400 to 0x403, the next at 725254Sgavinm * 0x404 to 0x407, and so on. Current processors implement up to 6 735254Sgavinm * banks (sixth one at 0x414 to 0x417). 745254Sgavinm * 755254Sgavinm * It is, sadly, not the case that the i'th set of 4 registers starting 765254Sgavinm * at 0x400 corresponds to MCi_{CTL,STATUS,ADDR,MISC} - for some Intel 775254Sgavinm * processors, for example, the order is 0/1/2/4/3. Nonetheless, we can 785254Sgavinm * still iterate through the banks and read all telemetry - there'll just 795254Sgavinm * be some potential confusion as to which processor unit a bank is 805254Sgavinm * associated with. Error reports should seek to disambiguate. 815254Sgavinm * 825254Sgavinm * IA32_MSR_MC(i, which) calculates the MSR address for th i'th bank 835254Sgavinm * of registers (not for MCi_*, as above) and one of CTL, STATUS, ADDR, MISC 845254Sgavinm */ 851414Scindi 865254Sgavinm #define _IA32_MSR_MC0_CTL 0x400ULL /* first/base reg */ 875254Sgavinm #define _IA32_MSR_OFFSET_CTL 0x0 /* offset within a bank */ 885254Sgavinm #define _IA32_MSR_OFFSET_STATUS 0x1 /* offset within a bank */ 895254Sgavinm #define _IA32_MSR_OFFSET_ADDR 0x2 /* offset within a bank */ 905254Sgavinm #define _IA32_MSR_OFFSET_MISC 0x3 /* offset within a bank */ 915254Sgavinm 92*7415SAdrian.Frost@Sun.COM #define _IA32_MSR_MC0_CTL2 0x280ULL /* first MCi_CTL2 reg */ 935254Sgavinm 945254Sgavinm #define IA32_MSR_MC(i, which) \ 955254Sgavinm (_IA32_MSR_MC0_CTL + (i) * 4 + _IA32_MSR_OFFSET_##which) 965254Sgavinm 97*7415SAdrian.Frost@Sun.COM #define IA32_MSR_MC_CTL2(i) (_IA32_MSR_MC0_CTL2 + (i)) 987349SAdrian.Frost@Sun.COM 995254Sgavinm /* 1005254Sgavinm * IA32_MSR_MCG_CAP.MCG_EXT_P indicates that a processor implements 1015254Sgavinm * a set of extended machine-check registers starting at MSR 0x180; 1025254Sgavinm * when that is set, IA32_MSR_MCG_CAP.MCG_EXT_CNT indicates how 1035254Sgavinm * many of these extended registers (addresses 0x180, 0x181, ...) 1045254Sgavinm * are present. Which registers are present depends on whether support 1055254Sgavinm * for 64-bit architecture is present. 1065254Sgavinm */ 1075254Sgavinm 1085254Sgavinm #define _IA32_MCG_RAX 0x180ULL /* first/base extended reg */ 1095254Sgavinm 1105254Sgavinm #define IA32_MSR_EXT(i) (_IA32_MCG_RAX + (i)) 1111414Scindi 1125254Sgavinm #ifdef _BIT_FIELDS_LTOH 1135254Sgavinm typedef union mca_x86_mcistatus { 1145254Sgavinm uint64_t _val64; 1155254Sgavinm struct { 1165254Sgavinm /* 1175254Sgavinm * Lower 32 bits of MCi_STATUS 1185254Sgavinm */ 1195254Sgavinm struct { 1205254Sgavinm uint32_t _errcode:16; /* <15:0> */ 1215254Sgavinm uint32_t _ms_errcode:16; /* <31:16> */ 1225254Sgavinm } _mcis_lo; 1235254Sgavinm /* 1245254Sgavinm * Upper 32 bits of MCi_STATUS 1255254Sgavinm */ 1265254Sgavinm union { 1275254Sgavinm /* 1285254Sgavinm * If IA32_MCG_CAP.MCG_TES_P is set then <54:53> 1295254Sgavinm * and <56:55> are architectural. 1305254Sgavinm */ 1315254Sgavinm struct { 1325254Sgavinm uint32_t _otherinfo:21; /* <52:32> */ 1335254Sgavinm uint32_t _tbes:2; /* <54:53> */ 1345254Sgavinm uint32_t _reserved:2; /* <56:55> */ 1355254Sgavinm uint32_t _pcc:1; /* <57> */ 1365254Sgavinm uint32_t _addrv:1; /* <58> */ 1375254Sgavinm uint32_t _miscv:1; /* <59> */ 1385254Sgavinm uint32_t _en:1; /* <60> */ 1395254Sgavinm uint32_t _uc:1; /* <61> */ 1405254Sgavinm uint32_t _over:1; /* <62> */ 1415254Sgavinm uint32_t _val:1; /* <63> */ 1425254Sgavinm } _mcis_hi_tes_p; 1435254Sgavinm /* 1445254Sgavinm * If IA32_MCG_CAP.MCG_TES_P is clear then <56:53> 1455254Sgavinm * are model-specific. 1465254Sgavinm */ 1475254Sgavinm struct { 1485254Sgavinm uint32_t _otherinfo:25; /* <56:32> */ 1495254Sgavinm uint32_t _pcc:1; /* <57> */ 1505254Sgavinm uint32_t _addrv:1; /* <58> */ 1515254Sgavinm uint32_t _miscv:1; /* <59> */ 1525254Sgavinm uint32_t _en:1; /* <60> */ 1535254Sgavinm uint32_t _uc:1; /* <61> */ 1545254Sgavinm uint32_t _over:1; /* <62> */ 1555254Sgavinm uint32_t _val:1; /* <63> */ 1565254Sgavinm } _mcis_hi_tes_np; 1575254Sgavinm } _mcis_hi; 1585254Sgavinm } _mcis_hilo; 1595254Sgavinm } mca_x86_mcistatus_t; 1601414Scindi 1615254Sgavinm #define mcistatus_errcode _mcis_hilo._mcis_lo._errcode 1625254Sgavinm #define mcistatus_mserrcode _mcis_hilo._mcis_lo._ms_errcode 1635254Sgavinm #define mcistatus_pcc _mcis_hilo._mcis_hi._mcis_hi_tes_np._pcc 1645254Sgavinm #define mcistatus_addrv _mcis_hilo._mcis_hi._mcis_hi_tes_np._addrv 1655254Sgavinm #define mcistatus_miscv _mcis_hilo._mcis_hi._mcis_hi_tes_np._miscv 1665254Sgavinm #define mcistatus_en _mcis_hilo._mcis_hi._mcis_hi_tes_np._en 1675254Sgavinm #define mcistatus_uc _mcis_hilo._mcis_hi._mcis_hi_tes_np._uc 1685254Sgavinm #define mcistatus_over _mcis_hilo._mcis_hi._mcis_hi_tes_np._over 1695254Sgavinm #define mcistatus_val _mcis_hilo._mcis_hi._mcis_hi_tes_np._val 1705254Sgavinm 1715254Sgavinm /* 1725254Sgavinm * The consumer must check for TES_P before using these. 1735254Sgavinm */ 1745254Sgavinm #define mcistatus_tbes _mcis_hilo._mcis_hi._mcis_hi_tes_p._tbes 1755254Sgavinm #define mcistatus_reserved \ 1765254Sgavinm _mcis_hilo._mcis_hi._mcis_hi_tes_p._reserved 1775254Sgavinm #define mcistatus_otherinfo_tes_p \ 1785254Sgavinm _mcis_hilo._mcis_hi._mcis_hi_tes_p._otherinfo 1795254Sgavinm #define mcistatus_otherinfo_tes_np \ 1805254Sgavinm _mcis_hilo._mcis_hi._mcis_hi_tes_np._otherinfo 1815254Sgavinm 1825254Sgavinm #endif /* _BIT_FIELDS_LTOH */ 1831414Scindi 1841414Scindi #define MSR_MC_STATUS_VAL 0x8000000000000000ULL 1855254Sgavinm #define MSR_MC_STATUS_OVER 0x4000000000000000ULL 1861414Scindi #define MSR_MC_STATUS_UC 0x2000000000000000ULL 1871414Scindi #define MSR_MC_STATUS_EN 0x1000000000000000ULL 1881414Scindi #define MSR_MC_STATUS_MISCV 0x0800000000000000ULL 1891414Scindi #define MSR_MC_STATUS_ADDRV 0x0400000000000000ULL 1901414Scindi #define MSR_MC_STATUS_PCC 0x0200000000000000ULL 1915254Sgavinm #define MSR_MC_STATUS_RESERVED_MASK 0x0180000000000000ULL 1925254Sgavinm #define MSR_MC_STATUS_TBES_MASK 0x0060000000000000ULL 1935254Sgavinm #define MSR_MC_STATUS_TBES_SHIFT 53 1947349SAdrian.Frost@Sun.COM #define MSR_MC_STATUS_CEC_MASK 0x001fffc000000000ULL 1957349SAdrian.Frost@Sun.COM #define MSR_MC_STATUS_CEC_SHIFT 38 1961414Scindi #define MSR_MC_STATUS_MSERR_MASK 0x00000000ffff0000ULL 1971414Scindi #define MSR_MC_STATUS_MSERR_SHIFT 16 1981414Scindi #define MSR_MC_STATUS_MCAERR_MASK 0x000000000000ffffULL 1991414Scindi 200*7415SAdrian.Frost@Sun.COM #define MSR_MC_CTL2_EN 0x0000000040000000ULL 201*7415SAdrian.Frost@Sun.COM #define MSR_MC_CTL2_THRESHOLD_MASK 0x0000000000007fffULL 202*7415SAdrian.Frost@Sun.COM #define MSR_MC_CTL2_THRESHOLD_OVERFLOW 0x0000000000004000ULL 2037349SAdrian.Frost@Sun.COM 2041414Scindi /* 2055254Sgavinm * Macros to extract error code and model-specific error code. 2065254Sgavinm */ 2075254Sgavinm #define MCAX86_ERRCODE(stat) ((stat) & MSR_MC_STATUS_MCAERR_MASK) 2085254Sgavinm #define MCAX86_MSERRCODE(stat) \ 2095254Sgavinm (((stat) & MSR_MC_STATUS_MSERR_MASK) >> MSR_MC_STATUS_MSERR_SHIFT) 2105254Sgavinm 2115254Sgavinm /* 2125254Sgavinm * Macro to extract threshold based error state (if MCG_CAP.TES_P) 2135254Sgavinm */ 2145254Sgavinm #define MCAX86_TBES_VALUE(stat) \ 2155254Sgavinm (((stat) & MSR_MC_STATUS_TBES_MASK) >> MSR_MC_STATUS_TBES_SHIFT) 2165254Sgavinm 2175254Sgavinm /* 2185254Sgavinm * Bit definitions for the architectural error code. 2191414Scindi */ 2205254Sgavinm 2215254Sgavinm #define MCAX86_ERRCODE_TT_MASK 0x000c 2225254Sgavinm #define MCAX86_ERRCODE_TT_SHIFT 2 2235254Sgavinm #define MCAX86_ERRCODE_TT_INSTR 0x0 2245254Sgavinm #define MCAX86_ERRCODE_TT_DATA 0x1 2255254Sgavinm #define MCAX86_ERRCODE_TT_GEN 0x2 2265254Sgavinm #define MCAX86_ERRCODE_TT(code) \ 2275254Sgavinm (((code) & MCAX86_ERRCODE_TT_MASK) >> MCAX86_ERRCODE_TT_SHIFT) 2285254Sgavinm 2295254Sgavinm #define MCAX86_ERRCODE_LL_MASK 0x0003 2305254Sgavinm #define MCAX86_ERRCODE_LL_SHIFT 0 2315254Sgavinm #define MCAX86_ERRCODE_LL_L0 0x0 2325254Sgavinm #define MCAX86_ERRCODE_LL_L1 0x1 2335254Sgavinm #define MCAX86_ERRCODE_LL_L2 0x2 2345254Sgavinm #define MCAX86_ERRCODE_LL_LG 0x3 2355254Sgavinm #define MCAX86_ERRCODE_LL(code) \ 2365254Sgavinm ((code) & MCAX86_ERRCODE_LL_MASK) 2375254Sgavinm 2385254Sgavinm #define MCAX86_ERRCODE_RRRR_MASK 0x00f0 2395254Sgavinm #define MCAX86_ERRCODE_RRRR_SHIFT 4 2405254Sgavinm #define MCAX86_ERRCODE_RRRR_ERR 0x0 2415254Sgavinm #define MCAX86_ERRCODE_RRRR_RD 0x1 2425254Sgavinm #define MCAX86_ERRCODE_RRRR_WR 0x2 2435254Sgavinm #define MCAX86_ERRCODE_RRRR_DRD 0x3 2445254Sgavinm #define MCAX86_ERRCODE_RRRR_DWR 0x4 2455254Sgavinm #define MCAX86_ERRCODE_RRRR_IRD 0x5 2465254Sgavinm #define MCAX86_ERRCODE_RRRR_PREFETCH 0x6 2475254Sgavinm #define MCAX86_ERRCODE_RRRR_EVICT 0x7 2485254Sgavinm #define MCAX86_ERRCODE_RRRR_SNOOP 0x8 2495254Sgavinm #define MCAX86_ERRCODE_RRRR(code) \ 2505254Sgavinm (((code) & MCAX86_ERRCODE_RRRR_MASK) >> MCAX86_ERRCODE_RRRR_SHIFT) 2511414Scindi 2525254Sgavinm #define MCAX86_ERRCODE_PP_MASK 0x0600 2535254Sgavinm #define MCAX86_ERRCODE_PP_SHIFT 9 2545254Sgavinm #define MCAX86_ERRCODE_PP_SRC 0x0 2555254Sgavinm #define MCAX86_ERRCODE_PP_RES 0x1 2565254Sgavinm #define MCAX86_ERRCODE_PP_OBS 0x2 2575254Sgavinm #define MCAX86_ERRCODE_PP_GEN 0x3 2585254Sgavinm #define MCAX86_ERRCODE_PP(code) \ 2595254Sgavinm (((code) & MCAX86_ERRCODE_PP_MASK) >> MCAX86_ERRCODE_PP_SHIFT) 2605254Sgavinm 2615254Sgavinm #define MCAX86_ERRCODE_II_MASK 0x000c 2625254Sgavinm #define MCAX86_ERRCODE_II_SHIFT 2 2635254Sgavinm #define MCAX86_ERRCODE_II_MEM 0x0 2645254Sgavinm #define MCAX86_ERRCODE_II_IO 0x2 2655254Sgavinm #define MCAX86_ERRCODE_II_GEN 0x3 2665254Sgavinm #define MCAX86_ERRCODE_II(code) \ 2675254Sgavinm (((code) & MCAX86_ERRCODE_II_MASK) >> MCAX86_ERRCODE_II_SHIFT) 2685254Sgavinm 2695254Sgavinm #define MCAX86_ERRCODE_T_MASK 0x0100 2705254Sgavinm #define MCAX86_ERRCODE_T_SHIFT 8 2715254Sgavinm #define MCAX86_ERRCODE_T_NONE 0x0 2725254Sgavinm #define MCAX86_ERRCODE_T_TIMEOUT 0x1 2735254Sgavinm #define MCAX86_ERRCODE_T(code) \ 2745254Sgavinm (((code) & MCAX86_ERRCODE_T_MASK) >> MCAX86_ERRCODE_T_SHIFT) 2755254Sgavinm 2767349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_MASK 0x0070 2777349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_SHIFT 4 2787349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_GEN 0x0 2797349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_RD 0x1 2807349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_WR 0x2 2817349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM_ADRCMD 0x3 2827349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_MMM(code) \ 2837349SAdrian.Frost@Sun.COM (((code) & MCAX86_ERRCODE_MMM_MASK) >> MCAX86_ERRCODE_MMM_SHIFT) 2847349SAdrian.Frost@Sun.COM 2857349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_MASK 0x000f 2867349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_SHIFT 0 2877349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH0 0x0 2887349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH1 0x1 2897349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH2 0x2 2907349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH3 0x3 2917349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH4 0x4 2927349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH5 0x5 2937349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH6 0x6 2947349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH7 0x7 2957349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH8 0x8 2967349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH9 0x9 2977349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH10 0xa 2987349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH11 0xb 2997349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH12 0xc 3007349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH13 0xd 3017349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_CH14 0xe 3027349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC_GEN 0xf 3037349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_CCCC(code) \ 3047349SAdrian.Frost@Sun.COM (((code) & MCAX86_ERRCODE_CCCC_MASK) >> MCAX86_ERRCODE_CCCC_SHIFT) 3057349SAdrian.Frost@Sun.COM 3065254Sgavinm /* 3075254Sgavinm * Simple error encoding. MASKON are bits that must be set for a match 3085254Sgavinm * at the same time bits indicated by MASKOFF are clear. 3095254Sgavinm */ 3105254Sgavinm #define MCAX86_SIMPLE_UNCLASSIFIED_MASKON 0x0001 3115254Sgavinm #define MCAX86_SIMPLE_UNCLASSIFIED_MASKOFF 0xfffe 3125254Sgavinm 3135254Sgavinm #define MCAX86_SIMPLE_MC_CODE_PARITY_MASKON 0x0002 3145254Sgavinm #define MCAX86_SIMPLE_MC_CODE_PARITY_MASKOFF 0xfffd 3155254Sgavinm 3165254Sgavinm #define MCAX86_SIMPLE_EXTERNAL_MASKON 0x0003 3175254Sgavinm #define MCAX86_SIMPLE_EXTERNAL_MASKOFF 0xfffc 3185254Sgavinm 3195254Sgavinm #define MCAX86_SIMPLE_FRC_MASKON 0x0004 3205254Sgavinm #define MCAX86_SIMPLE_FRC_MASKOFF 0xfffb 3215254Sgavinm 3227349SAdrian.Frost@Sun.COM #define MCAX86_SIMPLE_INTERNAL_PARITY_MASKON 0x0005 3237349SAdrian.Frost@Sun.COM #define MCAX86_SIMPLE_INTERNAL_PARITY_MASKOFF 0xfffa 3247349SAdrian.Frost@Sun.COM 3255254Sgavinm #define MCAX86_SIMPLE_INTERNAL_TIMER_MASKON 0x0400 3265254Sgavinm #define MCAX86_SIMPLE_INTERNAL_TIMER_MASKOFF 0xfbff 3271414Scindi 3285254Sgavinm #define MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON 0x0400 3295254Sgavinm #define MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF 0xf800 3305254Sgavinm #define MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK 0x03ff 3315254Sgavinm 3325254Sgavinm /* 3335254Sgavinm * Macros to make an internal unclassified error code, and to test if 3345254Sgavinm * a given code is internal unclassified. 3355254Sgavinm */ 3365254Sgavinm #define MCAX86_MKERRCODE_INTERNAL_UNCLASS(val) \ 3375254Sgavinm (MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON | \ 3385254Sgavinm ((val) & MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK)) 3395254Sgavinm #define MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code) \ 3405254Sgavinm (((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON) == \ 3415254Sgavinm MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKON && \ 3425254Sgavinm ((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_MASK_MASKOFF) == 0 && \ 3435254Sgavinm ((code) & MCAX86_SIMPLE_INTERNAL_UNCLASS_VALUE_MASK) != 0) 3445254Sgavinm 3455254Sgavinm /* 3465254Sgavinm * Is the given error code a simple error encoding? 3475254Sgavinm */ 3485254Sgavinm #define MCAX86_ERRCODE_ISSIMPLE(code) \ 3495254Sgavinm ((code) >= MCAX86_SIMPLE_UNCLASSIFIED_MASKON && \ 3507349SAdrian.Frost@Sun.COM (code) <= MCAX86_SIMPLE_INTERNAL_PARITY_MASKON || \ 3515254Sgavinm (code) == MCAX86_SIMPLE_INTERNAL_TIMER_MASKON || \ 3525254Sgavinm MCAX86_ERRCODE_ISSIMPLE_INTERNAL_UNCLASS(code)) 3535254Sgavinm 3545254Sgavinm /* 3555254Sgavinm * Compound error encoding. We always ignore the 'F' bit (which indicates 3565254Sgavinm * "correction report filtering") in classifying the error type. 3575254Sgavinm */ 3585254Sgavinm #define MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON 0x000c 3595254Sgavinm #define MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF 0xeff0 3605254Sgavinm 3615254Sgavinm #define MCAX86_COMPOUND_TLB_MASKON 0x0010 3625254Sgavinm #define MCAX86_COMPOUND_TLB_MASKOFF 0xefe0 3635254Sgavinm 3645254Sgavinm #define MCAX86_COMPOUND_MEMHIER_MASKON 0x0100 3655254Sgavinm #define MCAX86_COMPOUND_MEMHIER_MASKOFF 0xee00 3665254Sgavinm 3675254Sgavinm #define MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON 0x0800 3685254Sgavinm #define MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF 0xe000 3691414Scindi 3707349SAdrian.Frost@Sun.COM #define MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON 0x0080 3717349SAdrian.Frost@Sun.COM #define MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF 0xff00 3727349SAdrian.Frost@Sun.COM 3735254Sgavinm /* 3745254Sgavinm * Macros to make compound error codes and to test for each type. 3755254Sgavinm */ 3765254Sgavinm #define MCAX86_MKERRCODE_GENERIC_MEMHIER(ll) \ 3775254Sgavinm (MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON | \ 3785254Sgavinm ((ll) & MCAX86_ERRCODE_LL_MASK)) 3795254Sgavinm #define MCAX86_ERRCODE_ISGENERIC_MEMHIER(code) \ 3805254Sgavinm (((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON) == \ 3815254Sgavinm MCAX86_COMPOUND_GENERIC_MEMHIER_MASKON && \ 3825254Sgavinm ((code) & MCAX86_COMPOUND_GENERIC_MEMHIER_MASKOFF) == 0) 3835254Sgavinm 3845254Sgavinm #define MCAX86_MKERRCODE_TLB(tt, ll) \ 3855254Sgavinm (MCAX86_COMPOUND_TLB_MASKON | \ 3865254Sgavinm ((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \ 3875254Sgavinm ((ll) & MCAX86_ERRCODE_LL_MASK)) 3885254Sgavinm #define MCAX86_ERRCODE_ISTLB(code) \ 3895254Sgavinm (((code) & MCAX86_COMPOUND_TLB_MASKON) == \ 3905254Sgavinm MCAX86_COMPOUND_TLB_MASKON && \ 3915254Sgavinm ((code) & MCAX86_COMPOUND_TLB_MASKOFF) == 0) 3921414Scindi 3935254Sgavinm #define MCAX86_MKERRCODE_MEMHIER(rrrr, tt, ll) \ 3945254Sgavinm (MCAX86_COMPOUND_MEMHIER_MASKON | \ 3955254Sgavinm ((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \ 3965254Sgavinm ((tt) << MCAX86_ERRCODE_TT_SHIFT & MCAX86_ERRCODE_TT_MASK) | \ 3975254Sgavinm ((ll) & MCAX86_ERRCODE_LL_MASK)) 3985254Sgavinm #define MCAX86_ERRCODE_ISMEMHIER(code) \ 3995254Sgavinm (((code) & MCAX86_COMPOUND_MEMHIER_MASKON) == \ 4005254Sgavinm MCAX86_COMPOUND_MEMHIER_MASKON && \ 4015254Sgavinm ((code) & MCAX86_COMPOUND_MEMHIER_MASKOFF) == 0) 4025254Sgavinm 4035254Sgavinm #define MCAX86_MKERRCODE_BUS_INTERCONNECT(pp, t, rrrr, ii, ll) \ 4045254Sgavinm (MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON | \ 4055254Sgavinm ((pp) << MCAX86_ERRCODE_PP_SHIFT & MCAX86_ERRCODE_PP_MASK) | \ 4065254Sgavinm ((t) << MCAX86_ERRCODE_T_SHIFT & MCAX86_ERRCODE_T_MASK) | \ 4075254Sgavinm ((rrrr) << MCAX86_ERRCODE_RRRR_SHIFT & MCAX86_ERRCODE_RRRR_MASK) | \ 4085254Sgavinm ((ii) << MCAX86_ERRCODE_II_SHIFT & MCAX86_ERRCODE_II_MASK) | \ 4095254Sgavinm ((ll) & MCAX86_ERRCODE_LL_MASK)) 4105254Sgavinm #define MCAX86_ERRCODE_ISBUS_INTERCONNECT(code) \ 4115254Sgavinm (((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON) == \ 4125254Sgavinm MCAX86_COMPOUND_BUS_INTERCONNECT_MASKON && \ 4135254Sgavinm ((code) & MCAX86_COMPOUND_BUS_INTERCONNECT_MASKOFF) == 0) 4145254Sgavinm 4157349SAdrian.Frost@Sun.COM #define MCAX86_MKERRCODE_MEMORY_CONTROLLER (mmm, cccc) \ 4167349SAdrian.Frost@Sun.COM (MCAX86_COMPOUNT_MEMORY_CONTROLLER_MASKON | \ 4177349SAdrian.Frost@Sun.COM ((mmm) << MCAX86_ERRCODE_MMM_SHIFT & MCAX86_ERRCODE_MMM_MASK) | \ 4187349SAdrian.Frost@Sun.COM ((cccc) << MCAX86_ERRCODE_CCCC_SHIFT & MCAX86_ERRCODE_CCCC_MASK)) 4197349SAdrian.Frost@Sun.COM #define MCAX86_ERRCODE_ISMEMORY_CONTROLLER(code) \ 4207349SAdrian.Frost@Sun.COM (((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON) == \ 4217349SAdrian.Frost@Sun.COM MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKON && \ 4227349SAdrian.Frost@Sun.COM ((code) & MCAX86_COMPOUND_MEMORY_CONTROLLER_MASKOFF) == 0) 4237349SAdrian.Frost@Sun.COM 4245254Sgavinm #define MCAX86_ERRCODE_ISCOMPOUND(code) \ 4255254Sgavinm (MCAX86_ERRCODE_ISGENERIC_MEMHIER(code) || \ 4265254Sgavinm MCAX86_ERRCODE_ISTLB(code) || \ 4277349SAdrian.Frost@Sun.COM MCAX86_ERRCODE_ISMEMHIER(code) || \ 4287349SAdrian.Frost@Sun.COM MCAX86_ERRCODE_ISBUS_INTERCONNECT(code) || \ 4297349SAdrian.Frost@Sun.COM MCAX86_ERRCODE_ISMEMORY_CONTROLLER(code)) 4305254Sgavinm 4315254Sgavinm #define MCAX86_ERRCODE_UNKNOWN(code) \ 4325254Sgavinm (!MCAX86_ERRCODE_ISSIMPLE(code) && !MCAX86_ERRCODE_ISCOMPOUND(code)) 4331414Scindi 4341414Scindi #ifdef __cplusplus 4351414Scindi } 4361414Scindi #endif 4371414Scindi 4381414Scindi #endif /* _SYS_MCA_X86_H */ 439