xref: /onnv-gate/usr/src/uts/intel/sys/mc_amd.h (revision 11947:e9d33e5d3842)
11414Scindi /*
21414Scindi  * CDDL HEADER START
31414Scindi  *
41414Scindi  * The contents of this file are subject to the terms of the
52869Sgavinm  * Common Development and Distribution License (the "License").
62869Sgavinm  * You may not use this file except in compliance with the License.
71414Scindi  *
81414Scindi  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
91414Scindi  * or http://www.opensolaris.org/os/licensing.
101414Scindi  * See the License for the specific language governing permissions
111414Scindi  * and limitations under the License.
121414Scindi  *
131414Scindi  * When distributing Covered Code, include this CDDL HEADER in each
141414Scindi  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
151414Scindi  * If applicable, add the following below this CDDL HEADER, with the
161414Scindi  * fields enclosed by brackets "[]" replaced with your own identifying
171414Scindi  * information: Portions Copyright [yyyy] [name of copyright owner]
181414Scindi  *
191414Scindi  * CDDL HEADER END
201414Scindi  *
21*11947Ssrihari.venkatesan@oracle.com  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
221414Scindi  * Use is subject to license terms.
231414Scindi  */
241414Scindi 
251414Scindi #ifndef _MC_AMD_H
261414Scindi #define	_MC_AMD_H
271414Scindi 
282869Sgavinm #include <sys/mc.h>
295254Sgavinm #include <sys/isa_defs.h>
302869Sgavinm #include <sys/x86_archext.h>
312869Sgavinm 
323323Scindi #ifdef __cplusplus
333323Scindi extern "C" {
343323Scindi #endif
353323Scindi 
362869Sgavinm /*
373766Sgavinm  * Definitions, register offsets, register structure etc pertaining to
383766Sgavinm  * the memory controller on AMD64 systems.  These are used by both the
393766Sgavinm  * AMD cpu module and the mc-amd driver.
403766Sgavinm  */
413766Sgavinm 
423766Sgavinm /*
432869Sgavinm  * The mc-amd driver exports an nvlist to userland, where the primary
442869Sgavinm  * consumer is the "chip" topology enumerator for this platform type which
452869Sgavinm  * builds a full topology subtree from this information.  Others can use
463164Sgavinm  * it, too, but don't depend on it not changing without an ARC contract
473164Sgavinm  * (and the contract should probably concern the topology, not this nvlist).
482869Sgavinm  *
492869Sgavinm  * In the initial mc-amd implementation this nvlist was not versioned;
502869Sgavinm  * we'll think of that as version 0 and it may be recognised by the absence
512869Sgavinm  * of a "mcamd-nvlist-version member.
522869Sgavinm  *
532869Sgavinm  * Version 1 is defined as follows.  A name in square brackets indicates
542869Sgavinm  * that member is optional (only present if the actual value is valid).
552869Sgavinm  *
562869Sgavinm  * Name			Type		Description
572869Sgavinm  * -------------------- --------------- ---------------------------------------
582869Sgavinm  * mcamd-nvlist-version	uint8		Exported nvlist version number
592869Sgavinm  * num			uint64		Chip id of this memory controller
602869Sgavinm  * revision		uint64		cpuid_getchiprev() result
612869Sgavinm  * revname		string		cpuid_getchiprevstr() result
622869Sgavinm  * socket		string		"Socket 755|939|940|AM2|F(1207)|S1g1"
632869Sgavinm  * ecc-type		string		"ChipKill 128/16" or "Normal 64/8"
642869Sgavinm  * base-addr		uint64		Node base address
652869Sgavinm  * lim-addr		uint64		Node limit address
662869Sgavinm  * node-ilen		uint64		0|1|3|7 for 0/2/4/8 way node interleave
672869Sgavinm  * node-ilsel		uint64		Node interleave position of this node
682869Sgavinm  * cs-intlv-factor	uint64		chip-select interleave: 1/2/4/8
692869Sgavinm  * dram-hole-size	uint64		size in bytes from dram hole addr reg
702869Sgavinm  * access-width		uint64		MC mode, 64 or 128 bit
712869Sgavinm  * bank-mapping		uint64		Raw DRAM Bank Address Mapping Register
722869Sgavinm  * bankswizzle		uint64		1 if bank swizzling enabled; else 0
732869Sgavinm  * mismatched-dimm-support uint64	1 if active; else 0
742869Sgavinm  * [spare-csnum]	uint64		Chip-select pair number of any spare
752869Sgavinm  * [bad-csnum]		uint64		Chip-select pair number of swapped cs
762869Sgavinm  * cslist		nvlist array	See below; may have 0 members
772869Sgavinm  * dimmlist		nvlist array	See below; may have 0 members
782869Sgavinm  *
792869Sgavinm  * cslist is an array of nvlist, each as follows:
802869Sgavinm  *
812869Sgavinm  * Name			Type		Description
822869Sgavinm  * -------------------- --------------- ---------------------------------------
832869Sgavinm  * num			uint64		Chip-select base/mask pair number
842869Sgavinm  * base-addr		uint64		Chip-select base address (rel to node)
852869Sgavinm  * mask			uint64		Chip-select mask
862869Sgavinm  * size			uint64		Chip-select size in bytes
872869Sgavinm  * dimm1-num		uint64		First dimm (lodimm if a pair)
882869Sgavinm  * dimm1-csname		string		Socket cs# line name for 1st dimm rank
892869Sgavinm  * [dimm2-num]		uint64		Second dimm if applicable (updimm)
902869Sgavinm  * [dimm2-csname]	string		Socket cs# line name for 2nd dimm rank
912869Sgavinm  *
922869Sgavinm  * dimmlist is an array of nvlist, each as follows:
932869Sgavinm  *
942869Sgavinm  * Name			Type		Description
952869Sgavinm  * -------------------- --------------- ---------------------------------------
962869Sgavinm  * num			uint64		DIMM instance number
972869Sgavinm  * size			uint64		DIMM size in bytes
982869Sgavinm  * csnums		uint64 array	CS base/mask pair(s) on this DIMM
992869Sgavinm  * csnames		string array	Socket cs# line name(s) on this DIMM
1002869Sgavinm  *
1012869Sgavinm  *	The n'th csnums entry corresponds to the n'th csnames entry
1022869Sgavinm  */
1032869Sgavinm #define	MC_NVLIST_VERSTR	"mcamd-nvlist-version"
1042869Sgavinm #define	MC_NVLIST_VERS0		0
1052869Sgavinm #define	MC_NVLIST_VERS1		1
1062869Sgavinm #define	MC_NVLIST_VERS		MC_NVLIST_VERS1
1072869Sgavinm 
1081414Scindi /*
1092869Sgavinm  * Constants and feature/revision test macros that are not expected to vary
1102869Sgavinm  * among different AMD family 0xf processor revisions.
1112869Sgavinm  */
1122869Sgavinm 
1132869Sgavinm /*
1141414Scindi  * Configuration constants
1151414Scindi  */
1162869Sgavinm #define	MC_CHIP_MAXNODES	8	/* max number of MCs in system */
1171414Scindi #define	MC_CHIP_NDIMM		8	/* max dimms per MC */
1181414Scindi #define	MC_CHIP_NCS		8	/* number of chip-selects per MC */
1192869Sgavinm #define	MC_CHIP_NDRAMCHAN	2	/* maximum number of dram channels */
1201414Scindi #define	MC_CHIP_DIMMRANKMAX	4	/* largest number of ranks per dimm */
1211414Scindi #define	MC_CHIP_DIMMPERCS	2	/* max number of dimms per cs */
1221414Scindi #define	MC_CHIP_DIMMPAIR(csnum)	(csnum / MC_CHIP_DIMMPERCS)
1231414Scindi 
1243766Sgavinm /*
1253766Sgavinm  * Memory controller registers are read via PCI config space accesses on
1265254Sgavinm  * bus 0, device 0x18 + NodeId, and function as follows:
1273766Sgavinm  *
1283766Sgavinm  * Function 0: HyperTransport Technology Configuration
1293766Sgavinm  * Function 1: Address Map
1303766Sgavinm  * Function 2: DRAM Controller & HyperTransport Technology Trace Mode
1313766Sgavinm  * Function 3: Miscellaneous Control
1323766Sgavinm  */
1335254Sgavinm 
1345254Sgavinm #define	MC_AMD_DEV_OFFSET	0x18	/* node ID + offset == PCI dev num */
1355254Sgavinm 
1363766Sgavinm enum mc_funcnum {
1373766Sgavinm 	MC_FUNC_HTCONFIG = 0,
1383766Sgavinm 	MC_FUNC_ADDRMAP	= 1,
1393766Sgavinm 	MC_FUNC_DRAMCTL = 2,
1403766Sgavinm 	MC_FUNC_MISCCTL = 3
1413766Sgavinm };
1423766Sgavinm 
1433766Sgavinm /*
1443766Sgavinm  * For a given (bus, device, function) a particular offset selects the
1453766Sgavinm  * desired register.  All registers are 32-bits wide.
1463766Sgavinm  *
1473766Sgavinm  * Different family 0xf processor revisions vary slightly in the content
1483766Sgavinm  * of these configuration registers.  The biggest change is with rev F
1493766Sgavinm  * where DDR2 support has been introduced along with some hardware-controlled
1503766Sgavinm  * correctable memory error thresholding.  Fortunately most of the config info
1513766Sgavinm  * required by the mc-amd driver is similar across revisions.
1523766Sgavinm  *
1533766Sgavinm  * We will try to insulate most of the driver code from config register
1543766Sgavinm  * details by reading all memory-controller PCI config registers that we
1553766Sgavinm  * will need at driver attach time for each of functions 0 through 3, and
1563766Sgavinm  * storing them in a "cooked" form as memory controller properties.
1573766Sgavinm  * These are to be accessed directly where we have an mc_t to hand, otherwise
1583766Sgavinm  * through mcamd_get_numprop.  As such we expect most/all use of the
1593766Sgavinm  * structures and macros defined below to be in those attach codepaths.
1603766Sgavinm  */
1613766Sgavinm 
1623766Sgavinm /*
1633766Sgavinm  * Function 0 (HT Config) offsets
1643766Sgavinm  */
1653766Sgavinm #define	MC_HT_REG_RTBL_NODE_0	0x40
1663766Sgavinm #define	MC_HT_REG_RTBL_INCR	4
1673766Sgavinm #define	MC_HT_REG_NODEID	0x60
1683766Sgavinm #define	MC_HT_REG_UNITID	0x64
1692869Sgavinm 
1701414Scindi /*
1713766Sgavinm  * Function 1 (address map) offsets for DRAM base, DRAM limit, DRAM hole
1723766Sgavinm  * registers.
1733766Sgavinm  */
1743766Sgavinm #define	MC_AM_REG_DRAMBASE_0	0x40	/* Offset for DRAM Base 0 */
1753766Sgavinm #define	MC_AM_REG_DRAMLIM_0	0x44	/* Offset for DRAM Limit 0 */
1763766Sgavinm #define	MC_AM_REG_DRAM_INCR	8	/* incr between base/limit pairs */
1773766Sgavinm #define	MC_AM_REG_HOLEADDR	0xf0	/* DRAM Hole Address Register */
1783766Sgavinm 
1793766Sgavinm /*
1803766Sgavinm  * Function 2 (dram controller) offsets for chip-select base, chip-select mask,
1813766Sgavinm  * DRAM bank address mapping, DRAM configuration registers.
1823766Sgavinm  */
1833766Sgavinm #define	MC_DC_REG_CS_INCR	4	/* incr for CS base and mask */
1843766Sgavinm #define	MC_DC_REG_CSBASE_0	0x40	/* 0x40 - 0x5c */
1853766Sgavinm #define	MC_DC_REG_CSMASK_0	0x60	/* 0x60 - 0x7c */
1863766Sgavinm #define	MC_DC_REG_BANKADDRMAP	0x80	/* DRAM Bank Address Mapping */
1873766Sgavinm #define	MC_DC_REG_DRAMCFGLO	0x90	/* DRAM Configuration Low */
1883766Sgavinm #define	MC_DC_REG_DRAMCFGHI	0x94	/* DRAM Configuration High */
1893766Sgavinm #define	MC_DC_REG_DRAMMISC	0xa0	/* DRAM Miscellaneous */
1903766Sgavinm 
1913766Sgavinm /*
1925327Sgavinm  * Function 3 (misc control) offset for NB MCA config, scrubber control,
1935327Sgavinm  * online spare control and NB capabilities.
1942869Sgavinm  */
1953766Sgavinm #define	MC_CTL_REG_NBCFG	0x44	/* MCA NB configuration register */
1963766Sgavinm #define	MC_CTL_REG_SCRUBCTL	0x58	/* Scrub control register */
1973766Sgavinm #define	MC_CTL_REG_SCRUBADDR_LO	0x5c	/* DRAM Scrub Address Low */
1983766Sgavinm #define	MC_CTL_REG_SCRUBADDR_HI	0x60	/* DRAM Scrub Address High */
1993766Sgavinm #define	MC_CTL_REG_SPARECTL	0xb0	/* On-line spare control register */
2005327Sgavinm #define	MC_CTL_REG_NBCAP	0xe8	/* NB Capabilities */
201*11947Ssrihari.venkatesan@oracle.com #define	MC_CTL_REG_EXTNBCFG	0x180	/* Ext. MCA NB configuration register */
2025327Sgavinm 
20310026SKuriakose.Kuruvilla@Sun.COM #define	MC_NBCAP_L3CAPABLE	(1U << 25)
20410026SKuriakose.Kuruvilla@Sun.COM #define	MC_NBCAP_MULTINODECPU	(1U << 29)
205*11947Ssrihari.venkatesan@oracle.com #define	MC_EXTNBCFG_ECCSYMSZ	(1U << 25)
2063766Sgavinm 
2073766Sgavinm /*
2085254Sgavinm  * MC4_MISC MSR and MC4_MISCj MSRs
2095254Sgavinm  */
2105254Sgavinm #define	MC_MSR_NB_MISC0		0x413
2115254Sgavinm #define	MC_MSR_NB_MISC1		0xc0000408
2125254Sgavinm #define	MC_MSR_NB_MISC2		0xc0000409
2135254Sgavinm #define	MC_MSR_NB_MISC3		0xc000040a
2145254Sgavinm #define	MC_MSR_NB_MISC(j) \
2155254Sgavinm 	((j) == 0 ? MC_MSR_NB_MISC0 : MC_MSR_NB_MISC1 + (j) - 1)
2165254Sgavinm 
2175254Sgavinm /*
2185254Sgavinm  * PCI registers will be represented as unions, with one fixed-width unsigned
2193766Sgavinm  * integer member providing access to the raw register value and one or more
2203766Sgavinm  * structs breaking the register out into bitfields (more than one struct if
2213766Sgavinm  * the register definitions varies across processor revisions).
2223766Sgavinm  *
2233766Sgavinm  * The "raw" union member will always be '_val32'.  Use MCREG_VAL32 to
2243766Sgavinm  * access this member.
2253766Sgavinm  *
2263766Sgavinm  * The bitfield structs are all named _fmt_xxx where xxx identifies the
2273766Sgavinm  * processor revision to which it applies.  At this point the only xxx
2283766Sgavinm  * values in use are:
2293766Sgavinm  *			'cmn' - applies to all revisions
2305254Sgavinm  *			'f_preF' - applies to revisions E and earlier
2315254Sgavinm  *			'f_revFG' - applies to revisions F and G
2325254Sgavinm  *
2333766Sgavinm  * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced
2343766Sgavinm  * as requirements arise.  The MC_REV_* and MC_REV_MATCH etc macros
2353766Sgavinm  * will also need to grow to match.  Use MCREG_FIELD_* to access the
2363766Sgavinm  * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH
2373766Sgavinm  * to decide which revision suffix to provide.  Where a bitfield appears
2383766Sgavinm  * in different revisions but has the same use it should be named identically
2393766Sgavinm  * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros
2403766Sgavinm  * can lookup that member based on revision only.
2413766Sgavinm  */
2423766Sgavinm 
2432869Sgavinm #define	MC_REV_UNKNOWN	X86_CHIPREV_UNKNOWN
2445254Sgavinm 
2455254Sgavinm #define	MC_F_REV_B	X86_CHIPREV_AMD_F_REV_B
2465254Sgavinm #define	MC_F_REV_C	(X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG)
2475254Sgavinm #define	MC_F_REV_D	X86_CHIPREV_AMD_F_REV_D
2485254Sgavinm #define	MC_F_REV_E	X86_CHIPREV_AMD_F_REV_E
2495254Sgavinm #define	MC_F_REV_F	X86_CHIPREV_AMD_F_REV_F
2505254Sgavinm #define	MC_F_REV_G	X86_CHIPREV_AMD_F_REV_G
2515254Sgavinm 
2525254Sgavinm #define	MC_10_REV_A	X86_CHIPREV_AMD_10_REV_A
2535254Sgavinm #define	MC_10_REV_B	X86_CHIPREV_AMD_10_REV_B
2542869Sgavinm 
2552869Sgavinm /*
2562869Sgavinm  * The most common groupings for memory controller features.
2571414Scindi  */
2585254Sgavinm #define	MC_F_REVS_BC	(MC_F_REV_B | MC_F_REV_C)
2595254Sgavinm #define	MC_F_REVS_DE	(MC_F_REV_D | MC_F_REV_E)
2605254Sgavinm #define	MC_F_REVS_BCDE	(MC_F_REVS_BC | MC_F_REVS_DE)
2615254Sgavinm #define	MC_F_REVS_FG	(MC_F_REV_F | MC_F_REV_G)
2625254Sgavinm 
2635254Sgavinm #define	MC_10_REVS_AB	(MC_10_REV_A | MC_10_REV_B)
2642869Sgavinm 
2652869Sgavinm /*
2662869Sgavinm  * Is 'rev' included in the 'revmask' bitmask?
2672869Sgavinm  */
2682869Sgavinm #define	MC_REV_MATCH(rev, revmask)	X86_CHIPREV_MATCH(rev, revmask)
2692869Sgavinm 
2702869Sgavinm /*
2712869Sgavinm  * Is 'rev' at least revision 'revmin' or greater
2722869Sgavinm  */
2732869Sgavinm #define	MC_REV_ATLEAST(rev, minrev)	X86_CHIPREV_ATLEAST(rev, minrev)
2742869Sgavinm 
2752869Sgavinm #define	_MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
2762869Sgavinm 
2772869Sgavinm #define	MCREG_VAL32(up) ((up)->_val32)
2782869Sgavinm 
2795254Sgavinm /*
2805254Sgavinm  * Access a field that has the same structure in all families and revisions
2815254Sgavinm  */
2822869Sgavinm #define	MCREG_FIELD_CMN(up, field)	_MCREG_FIELD(up, cmn, field)
2835254Sgavinm 
2845254Sgavinm /*
2855254Sgavinm  * Access a field as defined for family 0xf prior to revision F
2865254Sgavinm  */
2875254Sgavinm #define	MCREG_FIELD_F_preF(up, field)	_MCREG_FIELD(up, f_preF, field)
2885254Sgavinm 
2895254Sgavinm /*
2905254Sgavinm  * Access a field as defined for family 0xf revisions F and G
2915254Sgavinm  */
2925254Sgavinm #define	MCREG_FIELD_F_revFG(up, field)	_MCREG_FIELD(up, f_revFG, field)
2935254Sgavinm 
2945254Sgavinm /*
2955254Sgavinm  * Access a field as defined for family 0x10 revisions A and
2965254Sgavinm  */
2975254Sgavinm #define	MCREG_FIELD_10_revAB(up, field)	_MCREG_FIELD(up, 10_revAB, field)
2985254Sgavinm 
2995254Sgavinm /*
3005254Sgavinm  * We will only define the register bitfields for little-endian order
3015254Sgavinm  */
3025254Sgavinm #ifdef	_BIT_FIELDS_LTOH
3031414Scindi 
3041414Scindi /*
3053323Scindi  * Function 0 - HT Configuration: Routing Table Node Register
3063323Scindi  */
3073323Scindi union mcreg_htroute {
3083323Scindi 	uint32_t	_val32;
3093323Scindi 	struct {
3103323Scindi 		uint32_t	RQRte:4;	/*  3:0 */
3113323Scindi 		uint32_t	reserved1:4;	/*  7:4 */
3123323Scindi 		uint32_t	RPRte:4;	/* 11:8 */
3133323Scindi 		uint32_t	reserved2:4;	/* 15:12 */
3143323Scindi 		uint32_t	BCRte:4;	/* 19:16 */
3153323Scindi 		uint32_t	reserved3:12;	/* 31:20 */
3163323Scindi 	} _fmt_cmn;
3173323Scindi };
3183323Scindi 
3193323Scindi /*
3203323Scindi  * Function 0 - HT Configuration: Node ID Register
3213323Scindi  */
3223323Scindi union mcreg_nodeid {
3233323Scindi 	uint32_t	_val32;
3243323Scindi 	struct {
3253323Scindi 		uint32_t	NodeId:3;	/*  2:0 */
3263323Scindi 		uint32_t	reserved1:1;	/*  3:3 */
3273323Scindi 		uint32_t	NodeCnt:3;	/*  6:4 */
3283323Scindi 		uint32_t	reserved2:1;	/*  7:7 */
3293323Scindi 		uint32_t	SbNode:3;	/* 10:8 */
3303323Scindi 		uint32_t	reserved3:1;	/* 11:11 */
3313323Scindi 		uint32_t	LkNode:3;	/* 14:12 */
3323323Scindi 		uint32_t	reserved4:1;	/* 15:15 */
3333323Scindi 		uint32_t	CpuCnt:4;	/* 19:16 */
3343323Scindi 		uint32_t	reserved:12;	/* 31:20 */
3353323Scindi 	} _fmt_cmn;
3363323Scindi };
3373323Scindi 
3383323Scindi #define	HT_COHERENTNODES(up)	(MCREG_FIELD_CMN(up, NodeCnt) + 1)
3393323Scindi #define	HT_SYSTEMCORECOUNT(up)	(MCREG_FIELD_CMN(up, CpuCnt) + 1)
3403323Scindi 
3413323Scindi /*
3423323Scindi  * Function 0 - HT Configuration: Unit ID Register
3433323Scindi  */
3443323Scindi union mcreg_unitid {
3453323Scindi 	uint32_t	_val32;
3463323Scindi 	struct {
3473323Scindi 		uint32_t	C0Unit:2;	/*  1:0 */
3483323Scindi 		uint32_t	C1Unit:2;	/*  3:2 */
3493323Scindi 		uint32_t	McUnit:2;	/*  5:4 */
3503323Scindi 		uint32_t	HbUnit:2;	/*  7:6 */
3513323Scindi 		uint32_t	SbLink:2;	/*  9:8 */
3523323Scindi 		uint32_t	reserved:22;	/* 31:10 */
3533323Scindi 	} _fmt_cmn;
3543323Scindi };
3553323Scindi 
3563323Scindi /*
3572869Sgavinm  * Function 1 - DRAM Address Map: DRAM Base i Registers
3582869Sgavinm  *
3592869Sgavinm  */
3602869Sgavinm 
3612869Sgavinm union mcreg_drambase {
3622869Sgavinm 	uint32_t	_val32;
3632869Sgavinm 	struct {
3642869Sgavinm 		uint32_t	RE:1;		/*  0:0  - Read Enable */
3652869Sgavinm 		uint32_t	WE:1;		/*  1:1  - Write Enable */
3662869Sgavinm 		uint32_t	reserved1:6;	/*  7:2 */
3672869Sgavinm 		uint32_t	IntlvEn:3;	/* 10:8  - Interleave Enable */
3682869Sgavinm 		uint32_t	reserved2:5;	/* 15:11 */
3692869Sgavinm 		uint32_t	DRAMBasei:16;	/* 31:16 - Base Addr 39:24 */
3702869Sgavinm 	} _fmt_cmn;
3712869Sgavinm };
3722869Sgavinm 
3732869Sgavinm #define	MC_DRAMBASE(up)	((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24)
3742869Sgavinm 
3752869Sgavinm /*
3762869Sgavinm  * Function 1 - DRAM Address Map: DRAM Limit i Registers
3772869Sgavinm  *
3781414Scindi  */
3792869Sgavinm 
3802869Sgavinm union mcreg_dramlimit {
3812869Sgavinm 	uint32_t	_val32;
3822869Sgavinm 	struct {
3832869Sgavinm 		uint32_t	DstNode:3;	/*  2:0  - Destination Node */
3842869Sgavinm 		uint32_t	reserved1:5;	/*  7:3 */
3852869Sgavinm 		uint32_t	IntlvSel:3;	/* 10:8  - Interleave Select */
3862869Sgavinm 		uint32_t	reserved2:5;	/* 15:11 */
3872869Sgavinm 		uint32_t	DRAMLimiti:16;	/* 31:16 - Limit Addr 39:24 */
3882869Sgavinm 	} _fmt_cmn;
3892869Sgavinm };
3902869Sgavinm 
3912869Sgavinm #define	MC_DRAMLIM(up) \
3922869Sgavinm 	((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 |		\
3932869Sgavinm 	(MCREG_FIELD_CMN(up, DRAMLimiti) ?  ((1 << 24) - 1) : 0))
3942869Sgavinm 
3952869Sgavinm /*
3962869Sgavinm  * Function 1 - DRAM Address Map: DRAM Hole Address Register
3972869Sgavinm  */
3982869Sgavinm 
3992869Sgavinm union mcreg_dramhole {
4002869Sgavinm 	uint32_t	_val32;
4012869Sgavinm 	struct {
4022869Sgavinm 		uint32_t	DramHoleValid:1;	/*  0:0 */
4032869Sgavinm 		uint32_t	reserved1:7;		/*  7:1 */
4042869Sgavinm 		uint32_t	DramHoleOffset:8;	/* 15:8 */
4052869Sgavinm 		uint32_t	reserved2:8;		/* 23:16 */
4062869Sgavinm 		uint32_t	DramHoleBase:8;		/* 31:24 */
4072869Sgavinm 	} _fmt_cmn;
4082869Sgavinm };
4092869Sgavinm 
4102869Sgavinm #define	MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24)
4111414Scindi 
4121414Scindi /*
4132869Sgavinm  * Function 2 - DRAM Controller: DRAM CS Base Address Registers
4141414Scindi  */
4152869Sgavinm 
4162869Sgavinm union mcreg_csbase {
4172869Sgavinm 	uint32_t	_val32;
4182869Sgavinm 	/*
4195254Sgavinm 	 * Register format in family 0xf revisions E and earlier
4202869Sgavinm 	 */
4212869Sgavinm 	struct {
4222869Sgavinm 		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
4232869Sgavinm 		uint32_t	reserved1:8;	/*  8:1 */
4242869Sgavinm 		uint32_t	BaseAddrLo:7;	/* 15:9  - Base Addr 19:13 */
4252869Sgavinm 		uint32_t	reserved2:5;	/* 20:16 */
4262869Sgavinm 		uint32_t	BaseAddrHi:11;	/* 31:21 - Base Addr 35:25 */
4275254Sgavinm 	} _fmt_f_preF;
4282869Sgavinm 	/*
4295254Sgavinm 	 * Register format in family 0xf revisions F and G
4302869Sgavinm 	 */
4312869Sgavinm 	struct {
4322869Sgavinm 		uint32_t	CSEnable:1;	/*  0:0  - CS Bank Enable */
4332869Sgavinm 		uint32_t	Spare:1;	/*  1:1  - Spare Rank */
4342869Sgavinm 		uint32_t	TestFail:1;	/*  2:2  - Memory Test Failed */
4352869Sgavinm 		uint32_t	reserved1:2;	/*  4:3 */
4362869Sgavinm 		uint32_t	BaseAddrLo:9;	/* 13:5  - Base Addr 21:13 */
4372869Sgavinm 		uint32_t	reserved2:5;	/* 18:14 */
4382869Sgavinm 		uint32_t	BaseAddrHi:10;	/* 28:19 - Base Addr 36:27 */
4392869Sgavinm 		uint32_t	reserved3:3;	/* 31:39 */
4405254Sgavinm 	} _fmt_f_revFG;
4412869Sgavinm };
4422869Sgavinm 
4435254Sgavinm #define	MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ?	\
4445254Sgavinm 	(uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrHi) << 27 |		\
4455254Sgavinm 	(uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrLo) << 13 :		\
4465254Sgavinm 	(uint64_t)MCREG_FIELD_F_preF(up, BaseAddrHi) << 25 |		\
4475254Sgavinm 	(uint64_t)MCREG_FIELD_F_preF(up, BaseAddrLo) << 13)
4481414Scindi 
4492869Sgavinm /*
4502869Sgavinm  * Function 2 - DRAM Controller: DRAM CS Mask Registers
4512869Sgavinm  */
4521414Scindi 
4532869Sgavinm union mcreg_csmask {
4542869Sgavinm 	uint32_t	_val32;
4552869Sgavinm 	/*
4565254Sgavinm 	 * Register format in family 0xf revisions E and earlier
4572869Sgavinm 	 */
4582869Sgavinm 	struct {
4592869Sgavinm 		uint32_t	reserved1:9;	/*  8:0 */
4602869Sgavinm 		uint32_t	AddrMaskLo:7;	/* 15:9  - Addr Mask 19:13 */
4612869Sgavinm 		uint32_t	reserved2:5;	/* 20:16 */
4622869Sgavinm 		uint32_t	AddrMaskHi:9;	/* 29:21 - Addr Mask 33:25 */
4632869Sgavinm 		uint32_t	reserved3:2;	/* 31:30 */
4645254Sgavinm 	} _fmt_f_preF;
4652869Sgavinm 	/*
4665254Sgavinm 	 * Register format in family 0xf revisions F and G
4672869Sgavinm 	 */
4682869Sgavinm 	struct {
4692869Sgavinm 		uint32_t	reserved1:5;	/*  4:0 */
4702869Sgavinm 		uint32_t	AddrMaskLo:9;	/* 13:5  - Addr Mask 21:13 */
4712869Sgavinm 		uint32_t	reserved2:5;	/* 18:14 */
4722869Sgavinm 		uint32_t	AddrMaskHi:10;	/* 28:19 - Addr Mask 36:27 */
4732869Sgavinm 		uint32_t	reserved3:3;	/* 31:29 */
4745254Sgavinm 	} _fmt_f_revFG;
4752869Sgavinm };
4761414Scindi 
4775254Sgavinm #define	MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 13 : 13)
4785254Sgavinm #define	MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 21 : 19)
4792869Sgavinm 
4805254Sgavinm #define	MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 27 : 25)
4815254Sgavinm #define	MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 36 : 33)
4822869Sgavinm 
4835254Sgavinm #define	MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 0 : 2)
4842869Sgavinm 
4855254Sgavinm #define	MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \
4865254Sgavinm 	(uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskHi) << 27 | \
4875254Sgavinm 	(uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \
4885254Sgavinm 	(uint64_t)MCREG_FIELD_F_preF(up, AddrMaskHi) << 25 | \
4895254Sgavinm 	(uint64_t)MCREG_FIELD_F_preF(up, AddrMaskLo) << 13 | 0x1f01fff)
4901414Scindi 
4911414Scindi /*
4922869Sgavinm  * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers
4931414Scindi  */
4941414Scindi 
4952869Sgavinm union mcreg_bankaddrmap {
4962869Sgavinm 	uint32_t	_val32;
4972869Sgavinm 	/*
4985254Sgavinm 	 * Register format in family 0xf revisions E and earlier
4992869Sgavinm 	 */
5002869Sgavinm 	struct {
5012869Sgavinm 		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
5022869Sgavinm 		uint32_t	cs32:4;			/*  7:4  - CS3/2 */
5032869Sgavinm 		uint32_t	cs54:4;			/* 11:8  - CS5/4 */
5042869Sgavinm 		uint32_t	cs76:4;			/* 15:12 - CS7/6 */
5052869Sgavinm 		uint32_t	reserved1:14;		/* 29:16 */
5062869Sgavinm 		uint32_t	BankSwizzleMode:1;	/* 30:30 */
5072869Sgavinm 		uint32_t	reserved2:1;		/* 31:31 */
5085254Sgavinm 	} _fmt_f_preF;
5092869Sgavinm 	/*
5105254Sgavinm 	 * Register format in family 0xf revisions F and G
5112869Sgavinm 	 */
5122869Sgavinm 	struct {
5132869Sgavinm 		uint32_t	cs10:4;			/*  3:0  - CS1/0 */
5142869Sgavinm 		uint32_t	cs32:4;			/*  7:4  - CS3/2 */
5152869Sgavinm 		uint32_t	cs54:4;			/* 11:8  - CS5/4 */
5162869Sgavinm 		uint32_t	cs76:4;			/* 15:12 - CS7/6 */
5172869Sgavinm 		uint32_t	reserved1:16;		/* 31:16 */
5185254Sgavinm 	} _fmt_f_revFG;
5192869Sgavinm 	/*
5202869Sgavinm 	 * Accessing all mode encodings as one uint16
5212869Sgavinm 	 */
5222869Sgavinm 	struct {
5232869Sgavinm 		uint32_t	allcsmodes:16;		/* 15:0 */
5242869Sgavinm 		uint32_t	pad:16;			/* 31:16 */
5252869Sgavinm 	} _fmt_bankmodes;
5262869Sgavinm };
5271414Scindi 
5282869Sgavinm #define	MC_DC_BAM_CSBANK_MASK	0x0000000f
5292869Sgavinm #define	MC_DC_BAM_CSBANK_SHIFT	4
5301414Scindi 
5312869Sgavinm #define	MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >>	\
5322869Sgavinm     MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK)
5331414Scindi 
5341414Scindi /*
5352869Sgavinm  * Function 2 - DRAM Controller: DRAM Configuration Low and High
5361414Scindi  */
5371414Scindi 
5382869Sgavinm union mcreg_dramcfg_lo {
5392869Sgavinm 	uint32_t _val32;
5402869Sgavinm 	/*
5415254Sgavinm 	 * Register format in family 0xf revisions E and earlier.
5422869Sgavinm 	 * Bit 7 is a BIOS ScratchBit in revs D and earlier,
5432869Sgavinm 	 * PwrDwnTriEn in revision E;  we don't use it so
5442869Sgavinm 	 * we'll call it ambig1.
5452869Sgavinm 	 */
5462869Sgavinm 	struct {
5472869Sgavinm 		uint32_t	DLL_Dis:1;	/* 0 */
5482869Sgavinm 		uint32_t	D_DRV:1;	/* 1 */
5492869Sgavinm 		uint32_t	QFC_EN:1;	/* 2 */
5502869Sgavinm 		uint32_t	DisDqsHys:1;	/* 3 */
5512869Sgavinm 		uint32_t	reserved1:1;	/* 4 */
5522869Sgavinm 		uint32_t	Burst2Opt:1;	/* 5 */
5532869Sgavinm 		uint32_t	Mod64BitMux:1;	/* 6 */
5542869Sgavinm 		uint32_t	ambig1:1;	/* 7 */
5552869Sgavinm 		uint32_t	DramInit:1;	/* 8 */
5562869Sgavinm 		uint32_t	DualDimmEn:1;	/* 9 */
5572869Sgavinm 		uint32_t	DramEnable:1;	/* 10 */
5582869Sgavinm 		uint32_t	MemClrStatus:1;	/* 11 */
5592869Sgavinm 		uint32_t	ESR:1;		/* 12 */
5602869Sgavinm 		uint32_t	SR_S:1;		/* 13 */
5612869Sgavinm 		uint32_t	RdWrQByp:2;	/* 15:14 */
5622869Sgavinm 		uint32_t	Width128:1;	/* 16 */
5632869Sgavinm 		uint32_t	DimmEcEn:1;	/* 17 */
5642869Sgavinm 		uint32_t	UnBufDimm:1;	/* 18 */
5652869Sgavinm 		uint32_t	ByteEn32:1;	/* 19 */
5662869Sgavinm 		uint32_t	x4DIMMs:4;	/* 23:20 */
5672869Sgavinm 		uint32_t	DisInRcvrs:1;	/* 24 */
5682869Sgavinm 		uint32_t	BypMax:3;	/* 27:25 */
5692869Sgavinm 		uint32_t	En2T:1;		/* 28 */
5702869Sgavinm 		uint32_t	UpperCSMap:1;	/* 29 */
5712869Sgavinm 		uint32_t	PwrDownCtl:2;	/* 31:30 */
5725254Sgavinm 	} _fmt_f_preF;
5732869Sgavinm 	/*
5745254Sgavinm 	 * Register format in family 0xf revisions F and G
5752869Sgavinm 	 */
5762869Sgavinm 	struct {
5772869Sgavinm 		uint32_t	InitDram:1;		/* 0 */
5782869Sgavinm 		uint32_t	ExitSelfRef:1;		/* 1 */
5792869Sgavinm 		uint32_t	reserved1:2;		/* 3:2 */
5802869Sgavinm 		uint32_t	DramTerm:2;		/* 5:4 */
5812869Sgavinm 		uint32_t	reserved2:1;		/* 6 */
5822869Sgavinm 		uint32_t	DramDrvWeak:1;		/* 7 */
5832869Sgavinm 		uint32_t	ParEn:1;		/* 8 */
5842869Sgavinm 		uint32_t	SelRefRateEn:1;		/* 9 */
5852869Sgavinm 		uint32_t	BurstLength32:1;	/* 10 */
5862869Sgavinm 		uint32_t	Width128:1;		/* 11 */
5872869Sgavinm 		uint32_t	x4DIMMs:4;		/* 15:12 */
5882869Sgavinm 		uint32_t	UnBuffDimm:1;		/* 16 */
5892869Sgavinm 		uint32_t	reserved3:2;		/* 18:17 */
5902869Sgavinm 		uint32_t	DimmEccEn:1;		/* 19 */
5912869Sgavinm 		uint32_t	reserved4:12;		/* 31:20 */
5925254Sgavinm 	} _fmt_f_revFG;
5932869Sgavinm };
5941414Scindi 
5951414Scindi /*
5962869Sgavinm  * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data
5972869Sgavinm  */
5982869Sgavinm 
5992869Sgavinm union mcreg_drammisc {
6002869Sgavinm 	uint32_t _val32;
6012869Sgavinm 	/*
6025254Sgavinm 	 * Register format in family 0xf revisions F and G
6032869Sgavinm 	 */
6042869Sgavinm 	struct {
6052869Sgavinm 		uint32_t	reserved2:1;		/* 0 */
6062869Sgavinm 		uint32_t	DisableJitter:1;	/* 1 */
6072869Sgavinm 		uint32_t	RdWrQByp:2;		/* 3:2 */
6082869Sgavinm 		uint32_t	Mod64Mux:1;		/* 4 */
6092869Sgavinm 		uint32_t	DCC_EN:1;		/* 5 */
6102869Sgavinm 		uint32_t	ILD_lmt:3;		/* 8:6 */
6112869Sgavinm 		uint32_t	DramEnabled:1;		/* 9 */
6122869Sgavinm 		uint32_t	PwrSavingsEn:1;		/* 10 */
6132869Sgavinm 		uint32_t	reserved1:13;		/* 23:11 */
6142869Sgavinm 		uint32_t	MemClkDis:8;		/* 31:24 */
6155254Sgavinm 	} _fmt_f_revFG;
6162869Sgavinm };
6172869Sgavinm 
6182869Sgavinm union mcreg_dramcfg_hi {
6192869Sgavinm 	uint32_t _val32;
6202869Sgavinm 	/*
6215254Sgavinm 	 * Register format in family 0xf revisions E and earlier.
6222869Sgavinm 	 */
6232869Sgavinm 	struct {
6242869Sgavinm 		uint32_t	AsyncLat:4;		/* 3:0 */
6252869Sgavinm 		uint32_t	reserved1:4;		/* 7:4 */
6262869Sgavinm 		uint32_t	RdPreamble:4;		/* 11:8 */
6272869Sgavinm 		uint32_t	reserved2:1;		/* 12 */
6282869Sgavinm 		uint32_t	MemDQDrvStren:2;	/* 14:13 */
6292869Sgavinm 		uint32_t	DisableJitter:1;	/* 15 */
6302869Sgavinm 		uint32_t	ILD_lmt:3;		/* 18:16 */
6312869Sgavinm 		uint32_t	DCC_EN:1;		/* 19 */
6322869Sgavinm 		uint32_t	MemClk:3;		/* 22:20 */
6332869Sgavinm 		uint32_t	reserved3:2;		/* 24:23 */
6342869Sgavinm 		uint32_t	MCR:1;			/* 25 */
6352869Sgavinm 		uint32_t	MC0_EN:1;		/* 26 */
6362869Sgavinm 		uint32_t	MC1_EN:1;		/* 27 */
6372869Sgavinm 		uint32_t	MC2_EN:1;		/* 28 */
6382869Sgavinm 		uint32_t	MC3_EN:1;		/* 29 */
6392869Sgavinm 		uint32_t	reserved4:1;		/* 30 */
6402869Sgavinm 		uint32_t	OddDivisorCorrect:1;	/* 31 */
6415254Sgavinm 	} _fmt_f_preF;
6422869Sgavinm 	/*
6435254Sgavinm 	 * Register format in family 0xf revisions F and G
6442869Sgavinm 	 */
6452869Sgavinm 	struct {
6462869Sgavinm 		uint32_t	MemClkFreq:3;		/* 2:0 */
6472869Sgavinm 		uint32_t	MemClkFreqVal:1;	/* 3 */
6482869Sgavinm 		uint32_t	MaxAsyncLat:4;		/* 7:4 */
6492869Sgavinm 		uint32_t	reserved1:4;		/* 11:8 */
6502869Sgavinm 		uint32_t	RDqsEn:1;		/* 12 */
6512869Sgavinm 		uint32_t	reserved2:1;		/* 13 */
6522869Sgavinm 		uint32_t	DisDramInterface:1;	/* 14 */
6532869Sgavinm 		uint32_t	PowerDownEn:1;		/* 15 */
6542869Sgavinm 		uint32_t	PowerDownMode:1;	/* 16 */
6552869Sgavinm 		uint32_t	FourRankSODimm:1;	/* 17 */
6562869Sgavinm 		uint32_t	FourRankRDimm:1;	/* 18 */
6572869Sgavinm 		uint32_t	reserved3:1;		/* 19 */
6582869Sgavinm 		uint32_t	SlowAccessMode:1;	/* 20 */
6592869Sgavinm 		uint32_t	reserved4:1;		/* 21 */
6602869Sgavinm 		uint32_t	BankSwizzleMode:1;	/* 22 */
6612869Sgavinm 		uint32_t	undocumented1:1;	/* 23 */
6622869Sgavinm 		uint32_t	DcqBypassMax:4;		/* 27:24 */
6632869Sgavinm 		uint32_t	FourActWindow:4;	/* 31:28 */
6645254Sgavinm 	} _fmt_f_revFG;
6652869Sgavinm };
6662869Sgavinm 
6672869Sgavinm /*
6682869Sgavinm  * Function 3 - Miscellaneous Control: Scrub Control Register
6692869Sgavinm  */
6702869Sgavinm 
6712869Sgavinm union mcreg_scrubctl {
6722869Sgavinm 	uint32_t _val32;
6732869Sgavinm 	struct {
6742869Sgavinm 		uint32_t	DramScrub:5;		/* 4:0 */
6752869Sgavinm 		uint32_t	reserved3:3;		/* 7:5 */
6762869Sgavinm 		uint32_t	L2Scrub:5;		/* 12:8 */
6772869Sgavinm 		uint32_t	reserved2:3;		/* 15:13 */
6782869Sgavinm 		uint32_t	DcacheScrub:5;		/* 20:16 */
6792869Sgavinm 		uint32_t	reserved1:11;		/* 31:21 */
6802869Sgavinm 	} _fmt_cmn;
6812869Sgavinm };
6822869Sgavinm 
6835254Sgavinm union mcreg_dramscrublo {
6845254Sgavinm 	uint32_t _val32;
6855254Sgavinm 	struct {
6865254Sgavinm 		uint32_t	ScrubReDirEn:1;		/* 0 */
6875254Sgavinm 		uint32_t	reserved:5;		/* 5:1 */
6885254Sgavinm 		uint32_t	ScrubAddrLo:26;		/* 31:6 */
6895254Sgavinm 	} _fmt_cmn;
6905254Sgavinm };
6915254Sgavinm 
6925254Sgavinm union mcreg_dramscrubhi {
6935254Sgavinm 	uint32_t _val32;
6945254Sgavinm 	struct {
6955254Sgavinm 		uint32_t	ScrubAddrHi:8;		/* 7:0 */
6965254Sgavinm 		uint32_t	reserved:24;		/* 31:8 */
6975254Sgavinm 	} _fmt_cmn;
6985254Sgavinm };
6995254Sgavinm 
7002869Sgavinm /*
7012869Sgavinm  * Function 3 - Miscellaneous Control: On-Line Spare Control Register
7021414Scindi  */
7032869Sgavinm 
7042869Sgavinm union mcreg_nbcfg {
7052869Sgavinm 	uint32_t _val32;
7062869Sgavinm 	/*
7075254Sgavinm 	 * Register format in family 0xf revisions E and earlier.
7082869Sgavinm 	 */
7092869Sgavinm 	struct {
7102869Sgavinm 		uint32_t	CpuEccErrEn:1;			/* 0 */
7112869Sgavinm 		uint32_t	CpuRdDatErrEn:1;		/* 1 */
7122869Sgavinm 		uint32_t	SyncOnUcEccEn:1;		/* 2 */
7132869Sgavinm 		uint32_t	SyncPktGenDis:1;		/* 3 */
7142869Sgavinm 		uint32_t	SyncPktPropDis:1;		/* 4 */
7152869Sgavinm 		uint32_t	IoMstAbortDis:1;		/* 5 */
7162869Sgavinm 		uint32_t	CpuErrDis:1;			/* 6 */
7172869Sgavinm 		uint32_t	IoErrDis:1;			/* 7 */
7182869Sgavinm 		uint32_t	WdogTmrDis:1;			/* 8 */
7192869Sgavinm 		uint32_t	WdogTmrCntSel:3;		/* 11:9 */
7202869Sgavinm 		uint32_t	WdogTmrBaseSel:2;		/* 13:12 */
7212869Sgavinm 		uint32_t	LdtLinkSel:2;			/* 15:14 */
7222869Sgavinm 		uint32_t	GenCrcErrByte0:1;		/* 16 */
7232869Sgavinm 		uint32_t	GenCrcErrByte1:1;		/* 17 */
7242869Sgavinm 		uint32_t	reserved1:2;			/* 19:18 */
7252869Sgavinm 		uint32_t	SyncOnWdogEn:1;			/* 20 */
7262869Sgavinm 		uint32_t	SyncOnAnyErrEn:1;		/* 21 */
7272869Sgavinm 		uint32_t	EccEn:1;			/* 22 */
7282869Sgavinm 		uint32_t	ChipKillEccEn:1;		/* 23 */
7292869Sgavinm 		uint32_t	IoRdDatErrEn:1;			/* 24 */
7302869Sgavinm 		uint32_t	DisPciCfgCpuErrRsp:1;		/* 25 */
7312869Sgavinm 		uint32_t	reserved2:1;			/* 26 */
7322869Sgavinm 		uint32_t	NbMcaToMstCpuEn:1;		/* 27 */
7332869Sgavinm 		uint32_t	reserved3:4;			/* 31:28 */
7345254Sgavinm 	} _fmt_f_preF;
7352869Sgavinm 	/*
7365254Sgavinm 	 * Register format in family 0xf revisions F and G
7372869Sgavinm 	 */
7382869Sgavinm 	struct {
7392869Sgavinm 		uint32_t	CpuEccErrEn:1;			/* 0 */
7402869Sgavinm 		uint32_t	CpuRdDatErrEn:1;		/* 1 */
7412869Sgavinm 		uint32_t	SyncOnUcEccEn:1;		/* 2 */
7422869Sgavinm 		uint32_t	SyncPktGenDis:1;		/* 3 */
7432869Sgavinm 		uint32_t	SyncPktPropDis:1;		/* 4 */
7442869Sgavinm 		uint32_t	IoMstAbortDis:1;		/* 5 */
7452869Sgavinm 		uint32_t	CpuErrDis:1;			/* 6 */
7462869Sgavinm 		uint32_t	IoErrDis:1;			/* 7 */
7472869Sgavinm 		uint32_t	WdogTmrDis:1;			/* 8 */
7482869Sgavinm 		uint32_t	WdogTmrCntSel:3;		/* 11:9 */
7492869Sgavinm 		uint32_t	WdogTmrBaseSel:2;		/* 13:12 */
7502869Sgavinm 		uint32_t	LdtLinkSel:2;			/* 15:14 */
7512869Sgavinm 		uint32_t	GenCrcErrByte0:1;		/* 16 */
7522869Sgavinm 		uint32_t	GenCrcErrByte1:1;		/* 17 */
7532869Sgavinm 		uint32_t	reserved1:2;			/* 19:18 */
7542869Sgavinm 		uint32_t	SyncOnWdogEn:1;			/* 20 */
7552869Sgavinm 		uint32_t	SyncOnAnyErrEn:1;		/* 21 */
7562869Sgavinm 		uint32_t	EccEn:1;			/* 22 */
7572869Sgavinm 		uint32_t	ChipKillEccEn:1;		/* 23 */
7582869Sgavinm 		uint32_t	IoRdDatErrEn:1;			/* 24 */
7592869Sgavinm 		uint32_t	DisPciCfgCpuErrRsp:1;		/* 25 */
7602869Sgavinm 		uint32_t	reserved2:1;			/* 26 */
7612869Sgavinm 		uint32_t	NbMcaToMstCpuEn:1;		/* 27 */
7622869Sgavinm 		uint32_t	DisTgtAbtCpuErrRsp:1;		/* 28 */
7632869Sgavinm 		uint32_t	DisMstAbtCpuErrRsp:1;		/* 29 */
7642869Sgavinm 		uint32_t	SyncOnDramAdrParErrEn:1;	/* 30 */
7652869Sgavinm 		uint32_t	reserved3:1;			/* 31 */
7662869Sgavinm 
7675254Sgavinm 	} _fmt_f_revFG;
7682869Sgavinm };
7692869Sgavinm 
7702869Sgavinm /*
7712869Sgavinm  * Function 3 - Miscellaneous Control: On-Line Spare Control Register
7722869Sgavinm  */
7732869Sgavinm 
7742869Sgavinm union mcreg_sparectl {
7752869Sgavinm 	uint32_t _val32;
7762869Sgavinm 	/*
7775254Sgavinm 	 * Register format in family 0xf revisions F and G
7782869Sgavinm 	 */
7792869Sgavinm 	struct {
7802869Sgavinm 		uint32_t	SwapEn:1;		/* 0 */
7812869Sgavinm 		uint32_t	SwapDone:1;		/* 1 */
7822869Sgavinm 		uint32_t	reserved1:2;		/* 3:2 */
7832869Sgavinm 		uint32_t	BadDramCs:3;		/* 6:4 */
7842869Sgavinm 		uint32_t	reserved2:5;		/* 11:7 */
7852869Sgavinm 		uint32_t	SwapDoneInt:2;		/* 13:12 */
7862869Sgavinm 		uint32_t	EccErrInt:2;		/* 15:14 */
7872869Sgavinm 		uint32_t	EccErrCntDramCs:3;	/* 18:16 */
7882869Sgavinm 		uint32_t	reserved3:1;		/* 19 */
7892869Sgavinm 		uint32_t	EccErrCntDramChan:1;	/* 20 */
7902869Sgavinm 		uint32_t	reserved4:2;		/* 22:21 */
7912869Sgavinm 		uint32_t	EccErrCntWrEn:1;	/* 23 */
7922869Sgavinm 		uint32_t	EccErrCnt:4;		/* 27:24 */
7932869Sgavinm 		uint32_t	reserved5:4;		/* 31:28 */
7945254Sgavinm 	} _fmt_f_revFG;
7955254Sgavinm 	/*
7965254Sgavinm 	 * Regiser format in family 0x10 revisions A and B
7975254Sgavinm 	 */
7985254Sgavinm 	struct {
7995254Sgavinm 		uint32_t	SwapEn0:1;		/* 0 */
8005254Sgavinm 		uint32_t	SwapDone0:1;		/* 1 */
8015254Sgavinm 		uint32_t	SwapEn1:1;		/* 2 */
8025254Sgavinm 		uint32_t	SwapDone1:1;		/* 3 */
8035254Sgavinm 		uint32_t	BadDramCs0:3;		/* 6:4 */
8045254Sgavinm 		uint32_t	reserved1:1;		/* 7 */
8055254Sgavinm 		uint32_t	BadDramCs1:3;		/* 10:8 */
8065254Sgavinm 		uint32_t	reserved2:1;		/* 11 */
8075254Sgavinm 		uint32_t	SwapDoneInt:2;		/* 13:12 */
8085254Sgavinm 		uint32_t	EccErrInt:2;		/* 15:14 */
8095254Sgavinm 		uint32_t	EccErrCntDramCs:4;	/* 19:16 */
8105254Sgavinm 		uint32_t	EccErrCntDramChan:2;	/* 21:20 */
8115254Sgavinm 		uint32_t	reserved4:1;		/* 22 */
8125254Sgavinm 		uint32_t	EccErrCntWrEn:1;	/* 23 */
8135254Sgavinm 		uint32_t	EccErrCnt:4;		/* 27:24 */
8145254Sgavinm 		uint32_t	LvtOffset:4;		/* 31:28 */
8155254Sgavinm 	} _fmt_10_revAB;
8162869Sgavinm };
8171414Scindi 
8185254Sgavinm /*
8195254Sgavinm  * Since the NB is on-chip some registers are also accessible as MSRs.
8205254Sgavinm  * We will represent such registers as bitfields as in the 32-bit PCI
8215254Sgavinm  * registers above, with the restriction that we must compile for 32-bit
8225254Sgavinm  * kernels and so 64-bit bitfields cannot be used.
8235254Sgavinm  */
8245254Sgavinm 
8255254Sgavinm #define	_MCMSR_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field)
8265254Sgavinm 
8275254Sgavinm #define	MCMSR_VAL(up) ((up)->_val64)
8285254Sgavinm 
8295254Sgavinm #define	MCMSR_FIELD_CMN(up, field)	_MCMSR_FIELD(up, cmn, field)
8305254Sgavinm #define	MCMSR_FIELD_F_preF(up, field)	_MCMSR_FIELD(up, f_preF, field)
8315254Sgavinm #define	MCMSR_FIELD_F_revFG(up, field)	_MCMSR_FIELD(up, f_revFG, field)
8325254Sgavinm #define	MCMSR_FIELD_10_revAB(up, field)	_MCMSR_FIELD(up, 10_revAB, field)
8335254Sgavinm 
8345254Sgavinm /*
8355254Sgavinm  * The NB MISC registers.  On family 0xf rev F this was introduced with
8365254Sgavinm  * a 12-bit ECC error count of all ECC errors observed on this memory-
8375254Sgavinm  * controller (regardless of channel or chip-select) and the ability to
8385254Sgavinm  * raise an interrupt or SMI on overflow.  In family 0x10 it has a similar
8395254Sgavinm  * purpose, but the register is is split into 4 misc registers
8405254Sgavinm  * MC4_MISC{0,1,2,3} accessible via both MSRs and PCI config space;
8415254Sgavinm  * they perform thresholding for dram, l3, HT errors.
8425254Sgavinm  */
8435254Sgavinm 
8445254Sgavinm union mcmsr_nbmisc {
8455254Sgavinm 	uint64_t _val64;
8465254Sgavinm 	/*
8475254Sgavinm 	 * MSR format in family 0xf revision F and later
8485254Sgavinm 	 */
8495254Sgavinm 	struct {
8505254Sgavinm 		/*
8515254Sgavinm 		 * Lower 32 bits
8525254Sgavinm 		 */
8535254Sgavinm 		struct {
8545254Sgavinm 			uint32_t _reserved;			/* 31:0 */
8555254Sgavinm 		} _mcimisc_lo;
8565254Sgavinm 		/*
8575254Sgavinm 		 * Upper 32 bits
8585254Sgavinm 		 */
8595254Sgavinm 		struct {
8605254Sgavinm 			uint32_t _ErrCount:12;			/* 43:32 */
8615254Sgavinm 			uint32_t _reserved1:4;			/* 47:44 */
8625254Sgavinm 			uint32_t _Ovrflw:1;			/* 48 */
8635254Sgavinm 			uint32_t _IntType:2;			/* 50:49 */
8645254Sgavinm 			uint32_t _CntEn:1;			/* 51 */
8655254Sgavinm 			uint32_t _LvtOff:4;			/* 55:52 */
8665254Sgavinm 			uint32_t _reserved2:5;			/* 60:56 */
8675254Sgavinm 			uint32_t _Locked:1;			/* 61 */
8685254Sgavinm 			uint32_t _CntP:1;			/* 62 */
8695254Sgavinm 			uint32_t _Valid:1;			/* 63 */
8705254Sgavinm 		} _mcimisc_hi;
8715254Sgavinm 	} _fmt_f_revFG;
8725254Sgavinm 	/*
8735254Sgavinm 	 * MSR format in family 0x10 revisions A and B
8745254Sgavinm 	 */
8755254Sgavinm 	struct {
8765254Sgavinm 		/*
8775254Sgavinm 		 * Lower 32 bits
8785254Sgavinm 		 */
8795254Sgavinm 		struct {
8805254Sgavinm 			uint32_t _reserved:24;			/* 23:0 */
8815254Sgavinm 			uint32_t _BlkPtr:8;			/* 31:24 */
8825254Sgavinm 		} _mcimisc_lo;
8835254Sgavinm 		/*
8845254Sgavinm 		 * Upper 32 bits
8855254Sgavinm 		 */
8865254Sgavinm 		struct {
8875254Sgavinm 			uint32_t _ErrCnt:12;			/* 43:32 */
8885254Sgavinm 			uint32_t _reserved1:4;			/* 47:44 */
8895254Sgavinm 			uint32_t _Ovrflw:1;			/* 48 */
8905254Sgavinm 			uint32_t _IntType:2;			/* 50:49 */
8915254Sgavinm 			uint32_t _CntEn:1;			/* 51 */
8925254Sgavinm 			uint32_t _LvtOff:4;			/* 55:52 */
8935254Sgavinm 			uint32_t _reserved2:5;			/* 60:56 */
8945254Sgavinm 			uint32_t _Locked:1;			/* 61 */
8955254Sgavinm 			uint32_t _CntP:1;			/* 62 */
8965254Sgavinm 			uint32_t _Valid:1;			/* 63 */
8975254Sgavinm 
8985254Sgavinm 		} _mcimisc_hi;
8995254Sgavinm 	} _fmt_10_revAB;
9005254Sgavinm };
9015254Sgavinm 
9025254Sgavinm #define	mcmisc_BlkPtr	_mcimisc_lo._BlkPtr
9035254Sgavinm #define	mcmisc_ErrCount	_mcimisc_hi._ErrCount
9045254Sgavinm #define	mcmisc_Ovrflw	_mcimisc_hi._Ovrflw
9055254Sgavinm #define	mcmisc_IntType	_mcimisc_hi._IntType
9065254Sgavinm #define	mcmisc_CntEn	_mcimisc_hi._CntEn
9075254Sgavinm #define	mcmisc_LvtOff	_mcimisc_hi._LvtOff
9085254Sgavinm #define	mcmisc_Locked	_mcimisc_hi._Locked
9095254Sgavinm #define	mcmisc_CntP	_mcimisc_hi._CntP
9105254Sgavinm #define	mcmisc_Valid	_mcimisc_hi._Valid
9115254Sgavinm 
9125254Sgavinm #endif /* _BIT_FIELDS_LTOH */
9135254Sgavinm 
9141414Scindi #ifdef __cplusplus
9151414Scindi }
9161414Scindi #endif
9171414Scindi 
9181414Scindi #endif /* _MC_AMD_H */
919