1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_MACHLOCK_H 28*0Sstevel@tonic-gate #define _SYS_MACHLOCK_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifndef _ASM 33*0Sstevel@tonic-gate #include <sys/types.h> 34*0Sstevel@tonic-gate #include <sys/time.h> 35*0Sstevel@tonic-gate #endif /* _ASM */ 36*0Sstevel@tonic-gate 37*0Sstevel@tonic-gate #ifdef __cplusplus 38*0Sstevel@tonic-gate extern "C" { 39*0Sstevel@tonic-gate #endif 40*0Sstevel@tonic-gate 41*0Sstevel@tonic-gate #ifndef _ASM 42*0Sstevel@tonic-gate 43*0Sstevel@tonic-gate #ifdef _KERNEL 44*0Sstevel@tonic-gate 45*0Sstevel@tonic-gate extern void lock_set(lock_t *lp); 46*0Sstevel@tonic-gate extern int lock_try(lock_t *lp); 47*0Sstevel@tonic-gate extern int lock_spin_try(lock_t *lp); 48*0Sstevel@tonic-gate extern int ulock_try(lock_t *lp); 49*0Sstevel@tonic-gate extern void lock_clear(lock_t *lp); 50*0Sstevel@tonic-gate extern void ulock_clear(lock_t *lp); 51*0Sstevel@tonic-gate extern void lock_set_spl(lock_t *lp, int new_pil, ushort_t *old_pil); 52*0Sstevel@tonic-gate extern void lock_clear_splx(lock_t *lp, int s); 53*0Sstevel@tonic-gate 54*0Sstevel@tonic-gate #endif /* _KERNEL */ 55*0Sstevel@tonic-gate 56*0Sstevel@tonic-gate #define LOCK_HELD_VALUE 0xff 57*0Sstevel@tonic-gate #define LOCK_INIT_CLEAR(lp) (*(lp) = 0) 58*0Sstevel@tonic-gate #define LOCK_INIT_HELD(lp) (*(lp) = LOCK_HELD_VALUE) 59*0Sstevel@tonic-gate #define LOCK_HELD(lp) (*(volatile lock_t *)(lp) != 0) 60*0Sstevel@tonic-gate 61*0Sstevel@tonic-gate typedef lock_t disp_lock_t; /* dispatcher lock type */ 62*0Sstevel@tonic-gate 63*0Sstevel@tonic-gate /* 64*0Sstevel@tonic-gate * SPIN_LOCK() macro indicates whether lock is implemented as a spin lock or 65*0Sstevel@tonic-gate * an adaptive mutex, depending on what interrupt levels use it. 66*0Sstevel@tonic-gate */ 67*0Sstevel@tonic-gate #define SPIN_LOCK(pl) ((pl) > ipltospl(LOCK_LEVEL)) 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate /* 70*0Sstevel@tonic-gate * Macro to control loops which spin on a lock and then check state 71*0Sstevel@tonic-gate * periodically. Its passed an integer, and returns a boolean value 72*0Sstevel@tonic-gate * that if true indicates its a good time to get the scheduler lock and 73*0Sstevel@tonic-gate * check the state of the current owner of the lock. 74*0Sstevel@tonic-gate */ 75*0Sstevel@tonic-gate #define LOCK_SAMPLE_INTERVAL(i) (((i) & 0xff) == 0) 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate /* 78*0Sstevel@tonic-gate * Externs for CLOCK_LOCK and clock resolution 79*0Sstevel@tonic-gate */ 80*0Sstevel@tonic-gate #ifdef __STDC__ 81*0Sstevel@tonic-gate extern volatile int hres_lock; 82*0Sstevel@tonic-gate #else 83*0Sstevel@tonic-gate extern int hres_lock; 84*0Sstevel@tonic-gate #endif 85*0Sstevel@tonic-gate extern hrtime_t hrtime_base; 86*0Sstevel@tonic-gate extern int clock_res; 87*0Sstevel@tonic-gate 88*0Sstevel@tonic-gate #endif /* _ASM */ 89*0Sstevel@tonic-gate 90*0Sstevel@tonic-gate /* 91*0Sstevel@tonic-gate * The definitions of the symbolic interrupt levels: 92*0Sstevel@tonic-gate * 93*0Sstevel@tonic-gate * CLOCK_LEVEL => The level at which one must be to block the clock. 94*0Sstevel@tonic-gate * 95*0Sstevel@tonic-gate * LOCK_LEVEL => The highest level at which one may block (and thus the 96*0Sstevel@tonic-gate * highest level at which one may acquire adaptive locks) 97*0Sstevel@tonic-gate * Also the highest level at which one may be preempted. 98*0Sstevel@tonic-gate * 99*0Sstevel@tonic-gate * DISP_LEVEL => The level at which one must be to perform dispatcher 100*0Sstevel@tonic-gate * operations. 101*0Sstevel@tonic-gate * 102*0Sstevel@tonic-gate * The constraints on the platform: 103*0Sstevel@tonic-gate * 104*0Sstevel@tonic-gate * - CLOCK_LEVEL must be less than or equal to LOCK_LEVEL 105*0Sstevel@tonic-gate * - LOCK_LEVEL must be less than DISP_LEVEL 106*0Sstevel@tonic-gate * - DISP_LEVEL should be as close to LOCK_LEVEL as possible 107*0Sstevel@tonic-gate * 108*0Sstevel@tonic-gate * Note that LOCK_LEVEL and CLOCK_LEVEL have historically always been equal; 109*0Sstevel@tonic-gate * changing this relationship is probably possible but not advised. 110*0Sstevel@tonic-gate * 111*0Sstevel@tonic-gate */ 112*0Sstevel@tonic-gate 113*0Sstevel@tonic-gate #define PIL_MAX 15 114*0Sstevel@tonic-gate 115*0Sstevel@tonic-gate #define CLOCK_LEVEL 10 116*0Sstevel@tonic-gate #define LOCK_LEVEL 10 117*0Sstevel@tonic-gate #define DISP_LEVEL (LOCK_LEVEL + 1) 118*0Sstevel@tonic-gate 119*0Sstevel@tonic-gate #define HIGH_LEVELS (PIL_MAX - LOCK_LEVEL) 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate /* 122*0Sstevel@tonic-gate * The following mask is for the cpu_intr_actv bits corresponding to 123*0Sstevel@tonic-gate * high-level PILs. It should equal: 124*0Sstevel@tonic-gate * ((((1 << PIL_MAX + 1) - 1) >> LOCK_LEVEL + 1) << LOCK_LEVEL + 1) 125*0Sstevel@tonic-gate */ 126*0Sstevel@tonic-gate #define CPU_INTR_ACTV_HIGH_LEVEL_MASK 0xF800 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate /* 129*0Sstevel@tonic-gate * The semaphore code depends on being able to represent a lock plus 130*0Sstevel@tonic-gate * owner in a single 32-bit word. (Mutexes used to have a similar 131*0Sstevel@tonic-gate * dependency, but no longer.) Thus the owner must contain at most 132*0Sstevel@tonic-gate * 24 significant bits. At present only threads and semaphores 133*0Sstevel@tonic-gate * must be aware of this vile constraint. Different ISAs may handle this 134*0Sstevel@tonic-gate * differently depending on their capabilities (e.g. compare-and-swap) 135*0Sstevel@tonic-gate * and limitations (e.g. constraints on alignment and/or KERNELBASE). 136*0Sstevel@tonic-gate */ 137*0Sstevel@tonic-gate #define PTR24_LSB 5 /* lower bits all zero */ 138*0Sstevel@tonic-gate #define PTR24_MSB (PTR24_LSB + 24) /* upper bits all one */ 139*0Sstevel@tonic-gate #define PTR24_ALIGN 32 /* minimum alignment (1 << lsb) */ 140*0Sstevel@tonic-gate #define PTR24_BASE 0xe0000000 /* minimum ptr value (-1 >> (32-msb)) */ 141*0Sstevel@tonic-gate 142*0Sstevel@tonic-gate #ifdef __cplusplus 143*0Sstevel@tonic-gate } 144*0Sstevel@tonic-gate #endif 145*0Sstevel@tonic-gate 146*0Sstevel@tonic-gate #endif /* _SYS_MACHLOCK_H */ 147