1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_CONTROLREGS_H 28*0Sstevel@tonic-gate #define _SYS_CONTROLREGS_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifndef _ASM 33*0Sstevel@tonic-gate #include <sys/types.h> 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate #ifdef __cplusplus 37*0Sstevel@tonic-gate extern "C" { 38*0Sstevel@tonic-gate #endif 39*0Sstevel@tonic-gate 40*0Sstevel@tonic-gate /* 41*0Sstevel@tonic-gate * This file describes the x86 architecture control registers which 42*0Sstevel@tonic-gate * are part of the privileged architecture. 43*0Sstevel@tonic-gate * 44*0Sstevel@tonic-gate * Many of these definitions are shared between IA-32-style and 45*0Sstevel@tonic-gate * AMD64-style processors. 46*0Sstevel@tonic-gate */ 47*0Sstevel@tonic-gate 48*0Sstevel@tonic-gate /* CR0 Register */ 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate #define CR0_PG 0x80000000 /* paging enabled */ 51*0Sstevel@tonic-gate #define CR0_CD 0x40000000 /* cache disable */ 52*0Sstevel@tonic-gate #define CR0_NW 0x20000000 /* not writethrough */ 53*0Sstevel@tonic-gate #define CR0_AM 0x00040000 /* alignment mask */ 54*0Sstevel@tonic-gate #define CR0_WP 0x00010000 /* write protect */ 55*0Sstevel@tonic-gate #define CR0_NE 0x00000020 /* numeric error */ 56*0Sstevel@tonic-gate #define CR0_ET 0x00000010 /* extension type */ 57*0Sstevel@tonic-gate #define CR0_TS 0x00000008 /* task switch */ 58*0Sstevel@tonic-gate #define CR0_EM 0x00000004 /* emulation */ 59*0Sstevel@tonic-gate #define CR0_MP 0x00000002 /* monitor coprocessor */ 60*0Sstevel@tonic-gate #define CR0_PE 0x00000001 /* protection enabled */ 61*0Sstevel@tonic-gate 62*0Sstevel@tonic-gate /* XX64 eliminate these compatibility defines */ 63*0Sstevel@tonic-gate 64*0Sstevel@tonic-gate #define CR0_CE CR0_CD 65*0Sstevel@tonic-gate #define CR0_WT CR0_NW 66*0Sstevel@tonic-gate 67*0Sstevel@tonic-gate #define FMT_CR0 \ 68*0Sstevel@tonic-gate "\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe" 69*0Sstevel@tonic-gate 70*0Sstevel@tonic-gate /* CR3 Register */ 71*0Sstevel@tonic-gate 72*0Sstevel@tonic-gate #define CR3_PCD 0x00000010 /* cache disable */ 73*0Sstevel@tonic-gate #define CR3_PWT 0x00000008 /* write through */ 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate #define FMT_CR3 "\20\5pcd\4pwt" 76*0Sstevel@tonic-gate 77*0Sstevel@tonic-gate /* CR4 Register */ 78*0Sstevel@tonic-gate 79*0Sstevel@tonic-gate #define CR4_VME 0x0001 /* virtual-8086 mode extensions */ 80*0Sstevel@tonic-gate #define CR4_PVI 0x0002 /* protected-mode virtual interrupts */ 81*0Sstevel@tonic-gate #define CR4_TSD 0x0004 /* time stamp disable */ 82*0Sstevel@tonic-gate #define CR4_DE 0x0008 /* debugging extensions */ 83*0Sstevel@tonic-gate #define CR4_PSE 0x0010 /* page size extensions */ 84*0Sstevel@tonic-gate #define CR4_PAE 0x0020 /* physical address extension */ 85*0Sstevel@tonic-gate #define CR4_MCE 0x0040 /* machine check enable */ 86*0Sstevel@tonic-gate #define CR4_PGE 0x0080 /* page global enable */ 87*0Sstevel@tonic-gate #define CR4_PCE 0x0100 /* perf-monitoring counter enable */ 88*0Sstevel@tonic-gate #define CR4_OSFXSR 0x0200 /* OS fxsave/fxrstor support */ 89*0Sstevel@tonic-gate #define CR4_OSXMMEXCPT 0x0400 /* OS unmasked exception support */ 90*0Sstevel@tonic-gate 91*0Sstevel@tonic-gate #define FMT_CR4 \ 92*0Sstevel@tonic-gate "\20\13xmme\12fxsr\11pce\10pge\7mce\6pae\5pse\4de\3tsd\2pvi\1vme" 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* Intel's SYSENTER configuration registers */ 95*0Sstevel@tonic-gate 96*0Sstevel@tonic-gate #define MSR_INTC_SEP_CS 0x174 /* kernel code selector MSR */ 97*0Sstevel@tonic-gate #define MSR_INTC_SEP_ESP 0x175 /* kernel esp MSR */ 98*0Sstevel@tonic-gate #define MSR_INTC_SEP_EIP 0x176 /* kernel eip MSR */ 99*0Sstevel@tonic-gate 100*0Sstevel@tonic-gate /* AMD's EFER register */ 101*0Sstevel@tonic-gate 102*0Sstevel@tonic-gate #define MSR_AMD_EFER 0xc0000080 /* extended feature enable MSR */ 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate #define AMD_EFER_NXE 0x800 /* no-execute enable */ 105*0Sstevel@tonic-gate #define AMD_EFER_LMA 0x400 /* long mode active (read-only) */ 106*0Sstevel@tonic-gate #define AMD_EFER_LME 0x100 /* long mode enable */ 107*0Sstevel@tonic-gate #define AMD_EFER_SCE 0x001 /* system call extensions */ 108*0Sstevel@tonic-gate 109*0Sstevel@tonic-gate #define FMT_AMD_EFER \ 110*0Sstevel@tonic-gate "\20\14nxe\13lma\11lme\1sce" 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate /* AMD's SYSCFG register */ 113*0Sstevel@tonic-gate 114*0Sstevel@tonic-gate #define MSR_AMD_SYSCFG 0xc0000010 /* system configuration MSR */ 115*0Sstevel@tonic-gate 116*0Sstevel@tonic-gate #define AMD_SYSCFG_TOM2 0x200000 /* MtrrTom2En */ 117*0Sstevel@tonic-gate #define AMD_SYSCFG_MVDM 0x100000 /* MtrrVarDramEn */ 118*0Sstevel@tonic-gate #define AMD_SYSCFG_MFDM 0x080000 /* MtrrFixDramModEn */ 119*0Sstevel@tonic-gate #define AMD_SYSCFG_MFDE 0x040000 /* MtrrFixDramEn */ 120*0Sstevel@tonic-gate 121*0Sstevel@tonic-gate #define FMT_AMD_SYSCFG \ 122*0Sstevel@tonic-gate "\20\26tom2\25mvdm\24mfdm\23mfde" 123*0Sstevel@tonic-gate 124*0Sstevel@tonic-gate /* AMD's syscall/sysret MSRs */ 125*0Sstevel@tonic-gate 126*0Sstevel@tonic-gate #define MSR_AMD_STAR 0xc0000081 /* %cs:%ss:%cs:%ss:%eip for syscall */ 127*0Sstevel@tonic-gate #define MSR_AMD_LSTAR 0xc0000082 /* target %rip of 64-bit syscall */ 128*0Sstevel@tonic-gate #define MSR_AMD_CSTAR 0xc0000083 /* target %rip of 32-bit syscall */ 129*0Sstevel@tonic-gate #define MSR_AMD_SFMASK 0xc0000084 /* syscall flag mask */ 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate /* AMD's FS.base and GS.base MSRs */ 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate #define MSR_AMD_FSBASE 0xc0000100 /* 64-bit base address for %fs */ 134*0Sstevel@tonic-gate #define MSR_AMD_GSBASE 0xc0000101 /* 64-bit base address for %gs */ 135*0Sstevel@tonic-gate #define MSR_AMD_KGSBASE 0xc0000102 /* swapgs swaps this with gsbase */ 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate /* AMD's configuration MSRs, weakly documented in the revision guide */ 138*0Sstevel@tonic-gate 139*0Sstevel@tonic-gate #define MSR_AMD_DC_CFG 0xc0011022 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate #define AMD_DC_CFG_DIS_CNV_WC_SSO (UINT64_C(1) << 3) 142*0Sstevel@tonic-gate #define AMD_DC_CFG_DIS_SMC_CHK_BUF (UINT64_C(1) << 10) 143*0Sstevel@tonic-gate 144*0Sstevel@tonic-gate /* AMD's HWCR MSR */ 145*0Sstevel@tonic-gate #define MSR_AMD_HWCR 0xc0010015 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate #define AMD_HWCR_FFDIS 0x40 /* set to disable TLB Flush Filter */ 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate /* AMD */ 150*0Sstevel@tonic-gate #define MSR_AMD_PATCHLEVEL 0x8b 151*0Sstevel@tonic-gate 152*0Sstevel@tonic-gate #ifdef __cplusplus 153*0Sstevel@tonic-gate } 154*0Sstevel@tonic-gate #endif 155*0Sstevel@tonic-gate 156*0Sstevel@tonic-gate #endif /* !_SYS_CONTROLREGS_H */ 157