1*0Sstevel@tonic-gate /****************************************************************************** 2*0Sstevel@tonic-gate * 3*0Sstevel@tonic-gate * Name: actbl2.h - ACPI Specification Revision 2.0 Tables 4*0Sstevel@tonic-gate * $Revision: 41 $ 5*0Sstevel@tonic-gate * 6*0Sstevel@tonic-gate *****************************************************************************/ 7*0Sstevel@tonic-gate 8*0Sstevel@tonic-gate /****************************************************************************** 9*0Sstevel@tonic-gate * 10*0Sstevel@tonic-gate * 1. Copyright Notice 11*0Sstevel@tonic-gate * 12*0Sstevel@tonic-gate * Some or all of this work - Copyright (c) 1999 - 2005, Intel Corp. 13*0Sstevel@tonic-gate * All rights reserved. 14*0Sstevel@tonic-gate * 15*0Sstevel@tonic-gate * 2. License 16*0Sstevel@tonic-gate * 17*0Sstevel@tonic-gate * 2.1. This is your license from Intel Corp. under its intellectual property 18*0Sstevel@tonic-gate * rights. You may have additional license terms from the party that provided 19*0Sstevel@tonic-gate * you this software, covering your right to use that party's intellectual 20*0Sstevel@tonic-gate * property rights. 21*0Sstevel@tonic-gate * 22*0Sstevel@tonic-gate * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 23*0Sstevel@tonic-gate * copy of the source code appearing in this file ("Covered Code") an 24*0Sstevel@tonic-gate * irrevocable, perpetual, worldwide license under Intel's copyrights in the 25*0Sstevel@tonic-gate * base code distributed originally by Intel ("Original Intel Code") to copy, 26*0Sstevel@tonic-gate * make derivatives, distribute, use and display any portion of the Covered 27*0Sstevel@tonic-gate * Code in any form, with the right to sublicense such rights; and 28*0Sstevel@tonic-gate * 29*0Sstevel@tonic-gate * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 30*0Sstevel@tonic-gate * license (with the right to sublicense), under only those claims of Intel 31*0Sstevel@tonic-gate * patents that are infringed by the Original Intel Code, to make, use, sell, 32*0Sstevel@tonic-gate * offer to sell, and import the Covered Code and derivative works thereof 33*0Sstevel@tonic-gate * solely to the minimum extent necessary to exercise the above copyright 34*0Sstevel@tonic-gate * license, and in no event shall the patent license extend to any additions 35*0Sstevel@tonic-gate * to or modifications of the Original Intel Code. No other license or right 36*0Sstevel@tonic-gate * is granted directly or by implication, estoppel or otherwise; 37*0Sstevel@tonic-gate * 38*0Sstevel@tonic-gate * The above copyright and patent license is granted only if the following 39*0Sstevel@tonic-gate * conditions are met: 40*0Sstevel@tonic-gate * 41*0Sstevel@tonic-gate * 3. Conditions 42*0Sstevel@tonic-gate * 43*0Sstevel@tonic-gate * 3.1. Redistribution of Source with Rights to Further Distribute Source. 44*0Sstevel@tonic-gate * Redistribution of source code of any substantial portion of the Covered 45*0Sstevel@tonic-gate * Code or modification with rights to further distribute source must include 46*0Sstevel@tonic-gate * the above Copyright Notice, the above License, this list of Conditions, 47*0Sstevel@tonic-gate * and the following Disclaimer and Export Compliance provision. In addition, 48*0Sstevel@tonic-gate * Licensee must cause all Covered Code to which Licensee contributes to 49*0Sstevel@tonic-gate * contain a file documenting the changes Licensee made to create that Covered 50*0Sstevel@tonic-gate * Code and the date of any change. Licensee must include in that file the 51*0Sstevel@tonic-gate * documentation of any changes made by any predecessor Licensee. Licensee 52*0Sstevel@tonic-gate * must include a prominent statement that the modification is derived, 53*0Sstevel@tonic-gate * directly or indirectly, from Original Intel Code. 54*0Sstevel@tonic-gate * 55*0Sstevel@tonic-gate * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 56*0Sstevel@tonic-gate * Redistribution of source code of any substantial portion of the Covered 57*0Sstevel@tonic-gate * Code or modification without rights to further distribute source must 58*0Sstevel@tonic-gate * include the following Disclaimer and Export Compliance provision in the 59*0Sstevel@tonic-gate * documentation and/or other materials provided with distribution. In 60*0Sstevel@tonic-gate * addition, Licensee may not authorize further sublicense of source of any 61*0Sstevel@tonic-gate * portion of the Covered Code, and must include terms to the effect that the 62*0Sstevel@tonic-gate * license from Licensee to its licensee is limited to the intellectual 63*0Sstevel@tonic-gate * property embodied in the software Licensee provides to its licensee, and 64*0Sstevel@tonic-gate * not to intellectual property embodied in modifications its licensee may 65*0Sstevel@tonic-gate * make. 66*0Sstevel@tonic-gate * 67*0Sstevel@tonic-gate * 3.3. Redistribution of Executable. Redistribution in executable form of any 68*0Sstevel@tonic-gate * substantial portion of the Covered Code or modification must reproduce the 69*0Sstevel@tonic-gate * above Copyright Notice, and the following Disclaimer and Export Compliance 70*0Sstevel@tonic-gate * provision in the documentation and/or other materials provided with the 71*0Sstevel@tonic-gate * distribution. 72*0Sstevel@tonic-gate * 73*0Sstevel@tonic-gate * 3.4. Intel retains all right, title, and interest in and to the Original 74*0Sstevel@tonic-gate * Intel Code. 75*0Sstevel@tonic-gate * 76*0Sstevel@tonic-gate * 3.5. Neither the name Intel nor any other trademark owned or controlled by 77*0Sstevel@tonic-gate * Intel shall be used in advertising or otherwise to promote the sale, use or 78*0Sstevel@tonic-gate * other dealings in products derived from or relating to the Covered Code 79*0Sstevel@tonic-gate * without prior written authorization from Intel. 80*0Sstevel@tonic-gate * 81*0Sstevel@tonic-gate * 4. Disclaimer and Export Compliance 82*0Sstevel@tonic-gate * 83*0Sstevel@tonic-gate * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 84*0Sstevel@tonic-gate * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 85*0Sstevel@tonic-gate * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 86*0Sstevel@tonic-gate * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 87*0Sstevel@tonic-gate * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 88*0Sstevel@tonic-gate * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 89*0Sstevel@tonic-gate * PARTICULAR PURPOSE. 90*0Sstevel@tonic-gate * 91*0Sstevel@tonic-gate * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 92*0Sstevel@tonic-gate * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 93*0Sstevel@tonic-gate * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 94*0Sstevel@tonic-gate * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 95*0Sstevel@tonic-gate * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 96*0Sstevel@tonic-gate * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 97*0Sstevel@tonic-gate * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 98*0Sstevel@tonic-gate * LIMITED REMEDY. 99*0Sstevel@tonic-gate * 100*0Sstevel@tonic-gate * 4.3. Licensee shall not export, either directly or indirectly, any of this 101*0Sstevel@tonic-gate * software or system incorporating such software without first obtaining any 102*0Sstevel@tonic-gate * required license or other approval from the U. S. Department of Commerce or 103*0Sstevel@tonic-gate * any other agency or department of the United States Government. In the 104*0Sstevel@tonic-gate * event Licensee exports any such software from the United States or 105*0Sstevel@tonic-gate * re-exports any such software from a foreign destination, Licensee shall 106*0Sstevel@tonic-gate * ensure that the distribution and export/re-export of the software is in 107*0Sstevel@tonic-gate * compliance with all laws, regulations, orders, or other restrictions of the 108*0Sstevel@tonic-gate * U.S. Export Administration Regulations. Licensee agrees that neither it nor 109*0Sstevel@tonic-gate * any of its subsidiaries will export/re-export any technical data, process, 110*0Sstevel@tonic-gate * software, or service, directly or indirectly, to any country for which the 111*0Sstevel@tonic-gate * United States government or any agency thereof requires an export license, 112*0Sstevel@tonic-gate * other governmental approval, or letter of assurance, without first obtaining 113*0Sstevel@tonic-gate * such license, approval or letter. 114*0Sstevel@tonic-gate * 115*0Sstevel@tonic-gate *****************************************************************************/ 116*0Sstevel@tonic-gate 117*0Sstevel@tonic-gate #ifndef __ACTBL2_H__ 118*0Sstevel@tonic-gate #define __ACTBL2_H__ 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate /* 121*0Sstevel@tonic-gate * Prefered Power Management Profiles 122*0Sstevel@tonic-gate */ 123*0Sstevel@tonic-gate #define PM_UNSPECIFIED 0 124*0Sstevel@tonic-gate #define PM_DESKTOP 1 125*0Sstevel@tonic-gate #define PM_MOBILE 2 126*0Sstevel@tonic-gate #define PM_WORKSTATION 3 127*0Sstevel@tonic-gate #define PM_ENTERPRISE_SERVER 4 128*0Sstevel@tonic-gate #define PM_SOHO_SERVER 5 129*0Sstevel@tonic-gate #define PM_APPLIANCE_PC 6 130*0Sstevel@tonic-gate 131*0Sstevel@tonic-gate /* 132*0Sstevel@tonic-gate * ACPI Boot Arch Flags 133*0Sstevel@tonic-gate */ 134*0Sstevel@tonic-gate #define BAF_LEGACY_DEVICES 0x0001 135*0Sstevel@tonic-gate #define BAF_8042_KEYBOARD_CONTROLLER 0x0002 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate #define FADT2_REVISION_ID 3 138*0Sstevel@tonic-gate #define FADT2_MINUS_REVISION_ID 2 139*0Sstevel@tonic-gate 140*0Sstevel@tonic-gate 141*0Sstevel@tonic-gate #pragma pack(1) 142*0Sstevel@tonic-gate 143*0Sstevel@tonic-gate /* 144*0Sstevel@tonic-gate * ACPI 2.0 Root System Description Table (RSDT) 145*0Sstevel@tonic-gate */ 146*0Sstevel@tonic-gate typedef struct rsdt_descriptor_rev2 147*0Sstevel@tonic-gate { 148*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 149*0Sstevel@tonic-gate UINT32 TableOffsetEntry [1]; /* Array of pointers to */ 150*0Sstevel@tonic-gate /* ACPI table headers */ 151*0Sstevel@tonic-gate } RSDT_DESCRIPTOR_REV2; 152*0Sstevel@tonic-gate 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate /* 155*0Sstevel@tonic-gate * ACPI 2.0 Extended System Description Table (XSDT) 156*0Sstevel@tonic-gate */ 157*0Sstevel@tonic-gate typedef struct xsdt_descriptor_rev2 158*0Sstevel@tonic-gate { 159*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 160*0Sstevel@tonic-gate UINT64 TableOffsetEntry [1]; /* Array of pointers to */ 161*0Sstevel@tonic-gate /* ACPI table headers */ 162*0Sstevel@tonic-gate } XSDT_DESCRIPTOR_REV2; 163*0Sstevel@tonic-gate 164*0Sstevel@tonic-gate 165*0Sstevel@tonic-gate /* 166*0Sstevel@tonic-gate * ACPI 2.0 Firmware ACPI Control Structure (FACS) 167*0Sstevel@tonic-gate */ 168*0Sstevel@tonic-gate typedef struct facs_descriptor_rev2 169*0Sstevel@tonic-gate { 170*0Sstevel@tonic-gate char Signature[4]; /* ACPI signature */ 171*0Sstevel@tonic-gate UINT32 Length; /* Length of structure, in bytes */ 172*0Sstevel@tonic-gate UINT32 HardwareSignature; /* Hardware configuration signature */ 173*0Sstevel@tonic-gate UINT32 FirmwareWakingVector; /* 32bit physical address of the Firmware Waking Vector. */ 174*0Sstevel@tonic-gate UINT32 GlobalLock; /* Global Lock used to synchronize access to shared hardware resources */ 175*0Sstevel@tonic-gate UINT32_BIT S4Bios_f : 1; /* S4Bios_f - Indicates if S4BIOS support is present */ 176*0Sstevel@tonic-gate UINT32_BIT Reserved1 : 31; /* Must be 0 */ 177*0Sstevel@tonic-gate UINT64 XFirmwareWakingVector; /* 64bit physical address of the Firmware Waking Vector. */ 178*0Sstevel@tonic-gate UINT8 Version; /* Version of this table */ 179*0Sstevel@tonic-gate UINT8 Reserved3 [31]; /* Reserved - must be zero */ 180*0Sstevel@tonic-gate 181*0Sstevel@tonic-gate } FACS_DESCRIPTOR_REV2; 182*0Sstevel@tonic-gate 183*0Sstevel@tonic-gate 184*0Sstevel@tonic-gate /* 185*0Sstevel@tonic-gate * ACPI 2.0+ Generic Address Structure (GAS) 186*0Sstevel@tonic-gate */ 187*0Sstevel@tonic-gate typedef struct acpi_generic_address 188*0Sstevel@tonic-gate { 189*0Sstevel@tonic-gate UINT8 AddressSpaceId; /* Address space where struct or register exists. */ 190*0Sstevel@tonic-gate UINT8 RegisterBitWidth; /* Size in bits of given register */ 191*0Sstevel@tonic-gate UINT8 RegisterBitOffset; /* Bit offset within the register */ 192*0Sstevel@tonic-gate UINT8 AccessWidth; /* Minimum Access size (ACPI 3.0) */ 193*0Sstevel@tonic-gate UINT64 Address; /* 64-bit address of struct or register */ 194*0Sstevel@tonic-gate 195*0Sstevel@tonic-gate } ACPI_GENERIC_ADDRESS; 196*0Sstevel@tonic-gate 197*0Sstevel@tonic-gate 198*0Sstevel@tonic-gate #define FADT_REV2_COMMON \ 199*0Sstevel@tonic-gate UINT32 V1_FirmwareCtrl; /* 32-bit physical address of FACS */ \ 200*0Sstevel@tonic-gate UINT32 V1_Dsdt; /* 32-bit physical address of DSDT */ \ 201*0Sstevel@tonic-gate UINT8 Reserved1; /* System Interrupt Model isn't used in ACPI 2.0*/ \ 202*0Sstevel@tonic-gate UINT8 Prefer_PM_Profile; /* Conveys preferred power management profile to OSPM. */ \ 203*0Sstevel@tonic-gate UINT16 SciInt; /* System vector of SCI interrupt */ \ 204*0Sstevel@tonic-gate UINT32 SmiCmd; /* Port address of SMI command port */ \ 205*0Sstevel@tonic-gate UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */ \ 206*0Sstevel@tonic-gate UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */ \ 207*0Sstevel@tonic-gate UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ \ 208*0Sstevel@tonic-gate UINT8 PstateCnt; /* Processor performance state control*/ \ 209*0Sstevel@tonic-gate UINT32 V1_Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */ \ 210*0Sstevel@tonic-gate UINT32 V1_Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */ \ 211*0Sstevel@tonic-gate UINT32 V1_Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ \ 212*0Sstevel@tonic-gate UINT32 V1_Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ \ 213*0Sstevel@tonic-gate UINT32 V1_Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ \ 214*0Sstevel@tonic-gate UINT32 V1_PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \ 215*0Sstevel@tonic-gate UINT32 V1_Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */ \ 216*0Sstevel@tonic-gate UINT32 V1_Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */ \ 217*0Sstevel@tonic-gate UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ \ 218*0Sstevel@tonic-gate UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ \ 219*0Sstevel@tonic-gate UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ \ 220*0Sstevel@tonic-gate UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ \ 221*0Sstevel@tonic-gate UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ \ 222*0Sstevel@tonic-gate UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ \ 223*0Sstevel@tonic-gate UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */ \ 224*0Sstevel@tonic-gate UINT8 CstCnt; /* Support for the _CST object and C States change notification.*/ \ 225*0Sstevel@tonic-gate UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */ \ 226*0Sstevel@tonic-gate UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */ \ 227*0Sstevel@tonic-gate UINT16 FlushSize; /* Number of flush strides that need to be read */ \ 228*0Sstevel@tonic-gate UINT16 FlushStride; /* Processor's memory cache line width, in bytes */ \ 229*0Sstevel@tonic-gate UINT8 DutyOffset; /* Processor's duty cycle index in processor's P_CNT reg*/ \ 230*0Sstevel@tonic-gate UINT8 DutyWidth; /* Processor's duty cycle value bit width in P_CNT register.*/ \ 231*0Sstevel@tonic-gate UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \ 232*0Sstevel@tonic-gate UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \ 233*0Sstevel@tonic-gate UINT8 Century; /* Index to century in RTC CMOS RAM */ \ 234*0Sstevel@tonic-gate UINT16 IapcBootArch; /* IA-PC Boot Architecture Flags. See Table 5-10 for description*/ 235*0Sstevel@tonic-gate 236*0Sstevel@tonic-gate /* 237*0Sstevel@tonic-gate * ACPI 2.0+ Fixed ACPI Description Table (FADT) 238*0Sstevel@tonic-gate */ 239*0Sstevel@tonic-gate typedef struct fadt_descriptor_rev2 240*0Sstevel@tonic-gate { 241*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 242*0Sstevel@tonic-gate FADT_REV2_COMMON 243*0Sstevel@tonic-gate UINT8 Reserved2; /* Reserved */ 244*0Sstevel@tonic-gate UINT32_BIT WbInvd : 1; /* The wbinvd instruction works properly */ 245*0Sstevel@tonic-gate UINT32_BIT WbInvdFlush : 1; /* The wbinvd flushes but does not invalidate */ 246*0Sstevel@tonic-gate UINT32_BIT ProcC1 : 1; /* All processors support C1 state */ 247*0Sstevel@tonic-gate UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */ 248*0Sstevel@tonic-gate UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */ 249*0Sstevel@tonic-gate UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */ 250*0Sstevel@tonic-gate UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */ 251*0Sstevel@tonic-gate UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ 252*0Sstevel@tonic-gate UINT32_BIT TmrValExt : 1; /* Indicates tmr_val is 32 bits 0=24-bits */ 253*0Sstevel@tonic-gate UINT32_BIT DockCap : 1; /* Supports Docking */ 254*0Sstevel@tonic-gate UINT32_BIT ResetRegSup : 1; /* Indicates system supports system reset via the FADT RESET_REG */ 255*0Sstevel@tonic-gate UINT32_BIT SealedCase : 1; /* Indicates system has no internal expansion capabilities and case is sealed */ 256*0Sstevel@tonic-gate UINT32_BIT Headless : 1; /* Indicates system does not have local video capabilities or local input devices */ 257*0Sstevel@tonic-gate UINT32_BIT CpuSwSleep : 1; /* Indicates to OSPM that a processor native instruction */ 258*0Sstevel@tonic-gate /* must be executed after writing the SLP_TYPx register */ 259*0Sstevel@tonic-gate /* ACPI 3.0 flag bits */ 260*0Sstevel@tonic-gate 261*0Sstevel@tonic-gate UINT32_BIT PciExpWak : 1; /* System supports PCIEXP_WAKE (STS/EN) bits */ 262*0Sstevel@tonic-gate UINT32_BIT UsePlatformClock : 1; /* OSPM should use platform-provided timer */ 263*0Sstevel@tonic-gate UINT32_BIT S4RtcStsValid : 1; /* Contents of RTC_STS valid after S4 wake */ 264*0Sstevel@tonic-gate UINT32_BIT RemotePowerOnCapable : 1; /* System is compatible with remote power on */ 265*0Sstevel@tonic-gate UINT32_BIT ForceApicClusterModel : 1; /* All local APICs must use cluster model */ 266*0Sstevel@tonic-gate UINT32_BIT ForceApicPhysicalDestinationMode : 1; /* All local xAPICs must use physical dest mode */ 267*0Sstevel@tonic-gate UINT32_BIT Reserved6 : 12;/* Reserved - must be zero */ 268*0Sstevel@tonic-gate 269*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */ 270*0Sstevel@tonic-gate UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system */ 271*0Sstevel@tonic-gate UINT8 Reserved7[3]; /* These three bytes must be zero */ 272*0Sstevel@tonic-gate UINT64 XFirmwareCtrl; /* 64-bit physical address of FACS */ 273*0Sstevel@tonic-gate UINT64 XDsdt; /* 64-bit physical address of DSDT */ 274*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPm1aEvtBlk; /* Extended Power Mgt 1a AcpiEvent Reg Blk address */ 275*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPm1bEvtBlk; /* Extended Power Mgt 1b AcpiEvent Reg Blk address */ 276*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPm1aCntBlk; /* Extended Power Mgt 1a Control Reg Blk address */ 277*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPm1bCntBlk; /* Extended Power Mgt 1b Control Reg Blk address */ 278*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPm2CntBlk; /* Extended Power Mgt 2 Control Reg Blk address */ 279*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XPmTmrBlk; /* Extended Power Mgt Timer Ctrl Reg Blk address */ 280*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XGpe0Blk; /* Extended General Purpose AcpiEvent 0 Reg Blk address */ 281*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS XGpe1Blk; /* Extended General Purpose AcpiEvent 1 Reg Blk address */ 282*0Sstevel@tonic-gate 283*0Sstevel@tonic-gate } FADT_DESCRIPTOR_REV2; 284*0Sstevel@tonic-gate 285*0Sstevel@tonic-gate 286*0Sstevel@tonic-gate /* "Down-revved" ACPI 2.0 FADT descriptor */ 287*0Sstevel@tonic-gate 288*0Sstevel@tonic-gate typedef struct fadt_descriptor_rev2_minus 289*0Sstevel@tonic-gate { 290*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 291*0Sstevel@tonic-gate FADT_REV2_COMMON 292*0Sstevel@tonic-gate UINT8 Reserved2; /* Reserved */ 293*0Sstevel@tonic-gate UINT32 Flags; 294*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS ResetRegister; /* Reset register address in GAS format */ 295*0Sstevel@tonic-gate UINT8 ResetValue; /* Value to write to the ResetRegister port to reset the system. */ 296*0Sstevel@tonic-gate UINT8 Reserved7[3]; /* These three bytes must be zero */ 297*0Sstevel@tonic-gate 298*0Sstevel@tonic-gate } FADT_DESCRIPTOR_REV2_MINUS; 299*0Sstevel@tonic-gate 300*0Sstevel@tonic-gate 301*0Sstevel@tonic-gate /* ECDT - Embedded Controller Boot Resources Table */ 302*0Sstevel@tonic-gate 303*0Sstevel@tonic-gate typedef struct ec_boot_resources 304*0Sstevel@tonic-gate { 305*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF 306*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS EcControl; /* Address of EC command/status register */ 307*0Sstevel@tonic-gate ACPI_GENERIC_ADDRESS EcData; /* Address of EC data register */ 308*0Sstevel@tonic-gate UINT32 Uid; /* Unique ID - must be same as the EC _UID method */ 309*0Sstevel@tonic-gate UINT8 GpeBit; /* The GPE for the EC */ 310*0Sstevel@tonic-gate UINT8 EcId[1]; /* Full namepath of the EC in the ACPI namespace */ 311*0Sstevel@tonic-gate 312*0Sstevel@tonic-gate } EC_BOOT_RESOURCES; 313*0Sstevel@tonic-gate 314*0Sstevel@tonic-gate 315*0Sstevel@tonic-gate /* SRAT - System Resource Affinity Table */ 316*0Sstevel@tonic-gate 317*0Sstevel@tonic-gate typedef struct static_resource_alloc 318*0Sstevel@tonic-gate { 319*0Sstevel@tonic-gate UINT8 Type; 320*0Sstevel@tonic-gate UINT8 Length; 321*0Sstevel@tonic-gate UINT8 ProximityDomainLo; 322*0Sstevel@tonic-gate UINT8 ApicId; 323*0Sstevel@tonic-gate UINT32_BIT Enabled :1; 324*0Sstevel@tonic-gate UINT32_BIT Reserved3 :31; 325*0Sstevel@tonic-gate UINT8 LocalSapicEid; 326*0Sstevel@tonic-gate UINT8 ProximityDomainHi[3]; 327*0Sstevel@tonic-gate UINT32 Reserved4; 328*0Sstevel@tonic-gate 329*0Sstevel@tonic-gate } STATIC_RESOURCE_ALLOC; 330*0Sstevel@tonic-gate 331*0Sstevel@tonic-gate typedef struct memory_affinity 332*0Sstevel@tonic-gate { 333*0Sstevel@tonic-gate UINT8 Type; 334*0Sstevel@tonic-gate UINT8 Length; 335*0Sstevel@tonic-gate UINT32 ProximityDomain; 336*0Sstevel@tonic-gate UINT16 Reserved3; 337*0Sstevel@tonic-gate UINT64 BaseAddress; 338*0Sstevel@tonic-gate UINT64 AddressLength; 339*0Sstevel@tonic-gate UINT32 Reserved4; 340*0Sstevel@tonic-gate UINT32_BIT Enabled :1; 341*0Sstevel@tonic-gate UINT32_BIT HotPluggable :1; 342*0Sstevel@tonic-gate UINT32_BIT NonVolatile :1; 343*0Sstevel@tonic-gate UINT32_BIT Reserved5 :29; 344*0Sstevel@tonic-gate UINT64 Reserved6; 345*0Sstevel@tonic-gate 346*0Sstevel@tonic-gate } MEMORY_AFFINITY; 347*0Sstevel@tonic-gate 348*0Sstevel@tonic-gate typedef struct system_resource_affinity 349*0Sstevel@tonic-gate { 350*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF 351*0Sstevel@tonic-gate UINT32 Reserved1; /* Must be value '1' */ 352*0Sstevel@tonic-gate UINT64 Reserved2; 353*0Sstevel@tonic-gate 354*0Sstevel@tonic-gate } SYSTEM_RESOURCE_AFFINITY; 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate 357*0Sstevel@tonic-gate /* SLIT - System Locality Distance Information Table */ 358*0Sstevel@tonic-gate 359*0Sstevel@tonic-gate typedef struct system_locality_info 360*0Sstevel@tonic-gate { 361*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF 362*0Sstevel@tonic-gate UINT64 LocalityCount; 363*0Sstevel@tonic-gate UINT8 Entry[1][1]; 364*0Sstevel@tonic-gate 365*0Sstevel@tonic-gate } SYSTEM_LOCALITY_INFO; 366*0Sstevel@tonic-gate 367*0Sstevel@tonic-gate 368*0Sstevel@tonic-gate #pragma pack() 369*0Sstevel@tonic-gate 370*0Sstevel@tonic-gate #endif /* __ACTBL2_H__ */ 371*0Sstevel@tonic-gate 372