1*0Sstevel@tonic-gate /****************************************************************************** 2*0Sstevel@tonic-gate * 3*0Sstevel@tonic-gate * Name: actbl1.h - ACPI 1.0 tables 4*0Sstevel@tonic-gate * $Revision: 29 $ 5*0Sstevel@tonic-gate * 6*0Sstevel@tonic-gate *****************************************************************************/ 7*0Sstevel@tonic-gate 8*0Sstevel@tonic-gate /****************************************************************************** 9*0Sstevel@tonic-gate * 10*0Sstevel@tonic-gate * 1. Copyright Notice 11*0Sstevel@tonic-gate * 12*0Sstevel@tonic-gate * Some or all of this work - Copyright (c) 1999 - 2005, Intel Corp. 13*0Sstevel@tonic-gate * All rights reserved. 14*0Sstevel@tonic-gate * 15*0Sstevel@tonic-gate * 2. License 16*0Sstevel@tonic-gate * 17*0Sstevel@tonic-gate * 2.1. This is your license from Intel Corp. under its intellectual property 18*0Sstevel@tonic-gate * rights. You may have additional license terms from the party that provided 19*0Sstevel@tonic-gate * you this software, covering your right to use that party's intellectual 20*0Sstevel@tonic-gate * property rights. 21*0Sstevel@tonic-gate * 22*0Sstevel@tonic-gate * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a 23*0Sstevel@tonic-gate * copy of the source code appearing in this file ("Covered Code") an 24*0Sstevel@tonic-gate * irrevocable, perpetual, worldwide license under Intel's copyrights in the 25*0Sstevel@tonic-gate * base code distributed originally by Intel ("Original Intel Code") to copy, 26*0Sstevel@tonic-gate * make derivatives, distribute, use and display any portion of the Covered 27*0Sstevel@tonic-gate * Code in any form, with the right to sublicense such rights; and 28*0Sstevel@tonic-gate * 29*0Sstevel@tonic-gate * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent 30*0Sstevel@tonic-gate * license (with the right to sublicense), under only those claims of Intel 31*0Sstevel@tonic-gate * patents that are infringed by the Original Intel Code, to make, use, sell, 32*0Sstevel@tonic-gate * offer to sell, and import the Covered Code and derivative works thereof 33*0Sstevel@tonic-gate * solely to the minimum extent necessary to exercise the above copyright 34*0Sstevel@tonic-gate * license, and in no event shall the patent license extend to any additions 35*0Sstevel@tonic-gate * to or modifications of the Original Intel Code. No other license or right 36*0Sstevel@tonic-gate * is granted directly or by implication, estoppel or otherwise; 37*0Sstevel@tonic-gate * 38*0Sstevel@tonic-gate * The above copyright and patent license is granted only if the following 39*0Sstevel@tonic-gate * conditions are met: 40*0Sstevel@tonic-gate * 41*0Sstevel@tonic-gate * 3. Conditions 42*0Sstevel@tonic-gate * 43*0Sstevel@tonic-gate * 3.1. Redistribution of Source with Rights to Further Distribute Source. 44*0Sstevel@tonic-gate * Redistribution of source code of any substantial portion of the Covered 45*0Sstevel@tonic-gate * Code or modification with rights to further distribute source must include 46*0Sstevel@tonic-gate * the above Copyright Notice, the above License, this list of Conditions, 47*0Sstevel@tonic-gate * and the following Disclaimer and Export Compliance provision. In addition, 48*0Sstevel@tonic-gate * Licensee must cause all Covered Code to which Licensee contributes to 49*0Sstevel@tonic-gate * contain a file documenting the changes Licensee made to create that Covered 50*0Sstevel@tonic-gate * Code and the date of any change. Licensee must include in that file the 51*0Sstevel@tonic-gate * documentation of any changes made by any predecessor Licensee. Licensee 52*0Sstevel@tonic-gate * must include a prominent statement that the modification is derived, 53*0Sstevel@tonic-gate * directly or indirectly, from Original Intel Code. 54*0Sstevel@tonic-gate * 55*0Sstevel@tonic-gate * 3.2. Redistribution of Source with no Rights to Further Distribute Source. 56*0Sstevel@tonic-gate * Redistribution of source code of any substantial portion of the Covered 57*0Sstevel@tonic-gate * Code or modification without rights to further distribute source must 58*0Sstevel@tonic-gate * include the following Disclaimer and Export Compliance provision in the 59*0Sstevel@tonic-gate * documentation and/or other materials provided with distribution. In 60*0Sstevel@tonic-gate * addition, Licensee may not authorize further sublicense of source of any 61*0Sstevel@tonic-gate * portion of the Covered Code, and must include terms to the effect that the 62*0Sstevel@tonic-gate * license from Licensee to its licensee is limited to the intellectual 63*0Sstevel@tonic-gate * property embodied in the software Licensee provides to its licensee, and 64*0Sstevel@tonic-gate * not to intellectual property embodied in modifications its licensee may 65*0Sstevel@tonic-gate * make. 66*0Sstevel@tonic-gate * 67*0Sstevel@tonic-gate * 3.3. Redistribution of Executable. Redistribution in executable form of any 68*0Sstevel@tonic-gate * substantial portion of the Covered Code or modification must reproduce the 69*0Sstevel@tonic-gate * above Copyright Notice, and the following Disclaimer and Export Compliance 70*0Sstevel@tonic-gate * provision in the documentation and/or other materials provided with the 71*0Sstevel@tonic-gate * distribution. 72*0Sstevel@tonic-gate * 73*0Sstevel@tonic-gate * 3.4. Intel retains all right, title, and interest in and to the Original 74*0Sstevel@tonic-gate * Intel Code. 75*0Sstevel@tonic-gate * 76*0Sstevel@tonic-gate * 3.5. Neither the name Intel nor any other trademark owned or controlled by 77*0Sstevel@tonic-gate * Intel shall be used in advertising or otherwise to promote the sale, use or 78*0Sstevel@tonic-gate * other dealings in products derived from or relating to the Covered Code 79*0Sstevel@tonic-gate * without prior written authorization from Intel. 80*0Sstevel@tonic-gate * 81*0Sstevel@tonic-gate * 4. Disclaimer and Export Compliance 82*0Sstevel@tonic-gate * 83*0Sstevel@tonic-gate * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED 84*0Sstevel@tonic-gate * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE 85*0Sstevel@tonic-gate * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE, 86*0Sstevel@tonic-gate * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY 87*0Sstevel@tonic-gate * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY 88*0Sstevel@tonic-gate * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A 89*0Sstevel@tonic-gate * PARTICULAR PURPOSE. 90*0Sstevel@tonic-gate * 91*0Sstevel@tonic-gate * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES 92*0Sstevel@tonic-gate * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR 93*0Sstevel@tonic-gate * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT, 94*0Sstevel@tonic-gate * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY 95*0Sstevel@tonic-gate * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL 96*0Sstevel@tonic-gate * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS 97*0Sstevel@tonic-gate * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY 98*0Sstevel@tonic-gate * LIMITED REMEDY. 99*0Sstevel@tonic-gate * 100*0Sstevel@tonic-gate * 4.3. Licensee shall not export, either directly or indirectly, any of this 101*0Sstevel@tonic-gate * software or system incorporating such software without first obtaining any 102*0Sstevel@tonic-gate * required license or other approval from the U. S. Department of Commerce or 103*0Sstevel@tonic-gate * any other agency or department of the United States Government. In the 104*0Sstevel@tonic-gate * event Licensee exports any such software from the United States or 105*0Sstevel@tonic-gate * re-exports any such software from a foreign destination, Licensee shall 106*0Sstevel@tonic-gate * ensure that the distribution and export/re-export of the software is in 107*0Sstevel@tonic-gate * compliance with all laws, regulations, orders, or other restrictions of the 108*0Sstevel@tonic-gate * U.S. Export Administration Regulations. Licensee agrees that neither it nor 109*0Sstevel@tonic-gate * any of its subsidiaries will export/re-export any technical data, process, 110*0Sstevel@tonic-gate * software, or service, directly or indirectly, to any country for which the 111*0Sstevel@tonic-gate * United States government or any agency thereof requires an export license, 112*0Sstevel@tonic-gate * other governmental approval, or letter of assurance, without first obtaining 113*0Sstevel@tonic-gate * such license, approval or letter. 114*0Sstevel@tonic-gate * 115*0Sstevel@tonic-gate *****************************************************************************/ 116*0Sstevel@tonic-gate 117*0Sstevel@tonic-gate #ifndef __ACTBL1_H__ 118*0Sstevel@tonic-gate #define __ACTBL1_H__ 119*0Sstevel@tonic-gate 120*0Sstevel@tonic-gate #pragma pack(1) 121*0Sstevel@tonic-gate 122*0Sstevel@tonic-gate /* 123*0Sstevel@tonic-gate * ACPI 1.0 Root System Description Table (RSDT) 124*0Sstevel@tonic-gate */ 125*0Sstevel@tonic-gate typedef struct rsdt_descriptor_rev1 126*0Sstevel@tonic-gate { 127*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 128*0Sstevel@tonic-gate UINT32 TableOffsetEntry [1]; /* Array of pointers to other */ 129*0Sstevel@tonic-gate /* ACPI tables */ 130*0Sstevel@tonic-gate } RSDT_DESCRIPTOR_REV1; 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate 133*0Sstevel@tonic-gate /* 134*0Sstevel@tonic-gate * ACPI 1.0 Firmware ACPI Control Structure (FACS) 135*0Sstevel@tonic-gate */ 136*0Sstevel@tonic-gate typedef struct facs_descriptor_rev1 137*0Sstevel@tonic-gate { 138*0Sstevel@tonic-gate char Signature[4]; /* ACPI Signature */ 139*0Sstevel@tonic-gate UINT32 Length; /* Length of structure, in bytes */ 140*0Sstevel@tonic-gate UINT32 HardwareSignature; /* Hardware configuration signature */ 141*0Sstevel@tonic-gate UINT32 FirmwareWakingVector; /* ACPI OS waking vector */ 142*0Sstevel@tonic-gate UINT32 GlobalLock; /* Global Lock */ 143*0Sstevel@tonic-gate UINT32_BIT S4Bios_f : 1; /* Indicates if S4BIOS support is present */ 144*0Sstevel@tonic-gate UINT32_BIT Reserved1 : 31; /* Must be 0 */ 145*0Sstevel@tonic-gate UINT8 Resverved3 [40]; /* Reserved - must be zero */ 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate } FACS_DESCRIPTOR_REV1; 148*0Sstevel@tonic-gate 149*0Sstevel@tonic-gate 150*0Sstevel@tonic-gate /* 151*0Sstevel@tonic-gate * ACPI 1.0 Fixed ACPI Description Table (FADT) 152*0Sstevel@tonic-gate */ 153*0Sstevel@tonic-gate typedef struct fadt_descriptor_rev1 154*0Sstevel@tonic-gate { 155*0Sstevel@tonic-gate ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 156*0Sstevel@tonic-gate UINT32 FirmwareCtrl; /* Physical address of FACS */ 157*0Sstevel@tonic-gate UINT32 Dsdt; /* Physical address of DSDT */ 158*0Sstevel@tonic-gate UINT8 Model; /* System Interrupt Model */ 159*0Sstevel@tonic-gate UINT8 Reserved1; /* Reserved */ 160*0Sstevel@tonic-gate UINT16 SciInt; /* System vector of SCI interrupt */ 161*0Sstevel@tonic-gate UINT32 SmiCmd; /* Port address of SMI command port */ 162*0Sstevel@tonic-gate UINT8 AcpiEnable; /* Value to write to smi_cmd to enable ACPI */ 163*0Sstevel@tonic-gate UINT8 AcpiDisable; /* Value to write to smi_cmd to disable ACPI */ 164*0Sstevel@tonic-gate UINT8 S4BiosReq; /* Value to write to SMI CMD to enter S4BIOS state */ 165*0Sstevel@tonic-gate UINT8 Reserved2; /* Reserved - must be zero */ 166*0Sstevel@tonic-gate UINT32 Pm1aEvtBlk; /* Port address of Power Mgt 1a AcpiEvent Reg Blk */ 167*0Sstevel@tonic-gate UINT32 Pm1bEvtBlk; /* Port address of Power Mgt 1b AcpiEvent Reg Blk */ 168*0Sstevel@tonic-gate UINT32 Pm1aCntBlk; /* Port address of Power Mgt 1a Control Reg Blk */ 169*0Sstevel@tonic-gate UINT32 Pm1bCntBlk; /* Port address of Power Mgt 1b Control Reg Blk */ 170*0Sstevel@tonic-gate UINT32 Pm2CntBlk; /* Port address of Power Mgt 2 Control Reg Blk */ 171*0Sstevel@tonic-gate UINT32 PmTmrBlk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ 172*0Sstevel@tonic-gate UINT32 Gpe0Blk; /* Port addr of General Purpose AcpiEvent 0 Reg Blk */ 173*0Sstevel@tonic-gate UINT32 Gpe1Blk; /* Port addr of General Purpose AcpiEvent 1 Reg Blk */ 174*0Sstevel@tonic-gate UINT8 Pm1EvtLen; /* Byte Length of ports at pm1X_evt_blk */ 175*0Sstevel@tonic-gate UINT8 Pm1CntLen; /* Byte Length of ports at pm1X_cnt_blk */ 176*0Sstevel@tonic-gate UINT8 Pm2CntLen; /* Byte Length of ports at pm2_cnt_blk */ 177*0Sstevel@tonic-gate UINT8 PmTmLen; /* Byte Length of ports at pm_tm_blk */ 178*0Sstevel@tonic-gate UINT8 Gpe0BlkLen; /* Byte Length of ports at gpe0_blk */ 179*0Sstevel@tonic-gate UINT8 Gpe1BlkLen; /* Byte Length of ports at gpe1_blk */ 180*0Sstevel@tonic-gate UINT8 Gpe1Base; /* Offset in gpe model where gpe1 events start */ 181*0Sstevel@tonic-gate UINT8 Reserved3; /* Reserved */ 182*0Sstevel@tonic-gate UINT16 Plvl2Lat; /* Worst case HW latency to enter/exit C2 state */ 183*0Sstevel@tonic-gate UINT16 Plvl3Lat; /* Worst case HW latency to enter/exit C3 state */ 184*0Sstevel@tonic-gate UINT16 FlushSize; /* Size of area read to flush caches */ 185*0Sstevel@tonic-gate UINT16 FlushStride; /* Stride used in flushing caches */ 186*0Sstevel@tonic-gate UINT8 DutyOffset; /* Bit location of duty cycle field in p_cnt reg */ 187*0Sstevel@tonic-gate UINT8 DutyWidth; /* Bit width of duty cycle field in p_cnt reg */ 188*0Sstevel@tonic-gate UINT8 DayAlrm; /* Index to day-of-month alarm in RTC CMOS RAM */ 189*0Sstevel@tonic-gate UINT8 MonAlrm; /* Index to month-of-year alarm in RTC CMOS RAM */ 190*0Sstevel@tonic-gate UINT8 Century; /* Index to century in RTC CMOS RAM */ 191*0Sstevel@tonic-gate UINT8 Reserved4; /* Reserved */ 192*0Sstevel@tonic-gate UINT8 Reserved4a; /* Reserved */ 193*0Sstevel@tonic-gate UINT8 Reserved4b; /* Reserved */ 194*0Sstevel@tonic-gate UINT32_BIT WbInvd : 1; /* The wbinvd instruction works properly */ 195*0Sstevel@tonic-gate UINT32_BIT WbInvdFlush : 1; /* The wbinvd flushes but does not invalidate */ 196*0Sstevel@tonic-gate UINT32_BIT ProcC1 : 1; /* All processors support C1 state */ 197*0Sstevel@tonic-gate UINT32_BIT Plvl2Up : 1; /* C2 state works on MP system */ 198*0Sstevel@tonic-gate UINT32_BIT PwrButton : 1; /* Power button is handled as a generic feature */ 199*0Sstevel@tonic-gate UINT32_BIT SleepButton : 1; /* Sleep button is handled as a generic feature, or not present */ 200*0Sstevel@tonic-gate UINT32_BIT FixedRTC : 1; /* RTC wakeup stat not in fixed register space */ 201*0Sstevel@tonic-gate UINT32_BIT Rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ 202*0Sstevel@tonic-gate UINT32_BIT TmrValExt : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */ 203*0Sstevel@tonic-gate UINT32_BIT Reserved5 : 23; /* Reserved - must be zero */ 204*0Sstevel@tonic-gate 205*0Sstevel@tonic-gate } FADT_DESCRIPTOR_REV1; 206*0Sstevel@tonic-gate 207*0Sstevel@tonic-gate #pragma pack() 208*0Sstevel@tonic-gate 209*0Sstevel@tonic-gate #endif /* __ACTBL1_H__ */ 210*0Sstevel@tonic-gate 211*0Sstevel@tonic-gate 212