1*1709Smlf /* 2*1709Smlf * CDDL HEADER START 3*1709Smlf * 4*1709Smlf * The contents of this file are subject to the terms of the 5*1709Smlf * Common Development and Distribution License (the "License"). 6*1709Smlf * You may not use this file except in compliance with the License. 7*1709Smlf * 8*1709Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*1709Smlf * or http://www.opensolaris.org/os/licensing. 10*1709Smlf * See the License for the specific language governing permissions 11*1709Smlf * and limitations under the License. 12*1709Smlf * 13*1709Smlf * When distributing Covered Code, include this CDDL HEADER in each 14*1709Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*1709Smlf * If applicable, add the following below this CDDL HEADER, with the 16*1709Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17*1709Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18*1709Smlf * 19*1709Smlf * CDDL HEADER END 20*1709Smlf */ 21*1709Smlf 22*1709Smlf /* 23*1709Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*1709Smlf * Use is subject to license terms. 25*1709Smlf */ 26*1709Smlf 27*1709Smlf #ifndef _SIL3XXX_H 28*1709Smlf #define _SIL3XXX_H 29*1709Smlf 30*1709Smlf #pragma ident "%Z%%M% %I% %E% SMI" 31*1709Smlf 32*1709Smlf #ifdef __cplusplus 33*1709Smlf extern "C" { 34*1709Smlf #endif 35*1709Smlf 36*1709Smlf /* 37*1709Smlf * PCI IDs 38*1709Smlf */ 39*1709Smlf #define SILICON_IMAGE_VENDOR_ID 0x1095 40*1709Smlf #define SIL3112_DEVICE_ID 0x3112 41*1709Smlf #define SIL3114_DEVICE_ID 0x3114 42*1709Smlf #define SIL3512_DEVICE_ID 0x3512 43*1709Smlf 44*1709Smlf /* Base Register 5 Indirect Address Offset */ 45*1709Smlf 46*1709Smlf #define PCI_CONF_BA5_IND_ADDRESS 0xc0 47*1709Smlf #define PCI_CONF_BA5_IND_ACCESS 0xc4 48*1709Smlf 49*1709Smlf /* 50*1709Smlf * FIS Configuration channel offsets 51*1709Smlf * Sil3114 has 4 channels 52*1709Smlf * Sil3112 has 2 channels 53*1709Smlf * Sil3512 has 2 channels 54*1709Smlf */ 55*1709Smlf #define SFISCFG_0 0x14c /* SFISCfg Channel 0 */ 56*1709Smlf #define SFISCFG_1 0x1cc /* SFISCfg Channel 1 */ 57*1709Smlf #define SFISCFG_2 0x34c /* SFISCfg Channel 2 */ 58*1709Smlf #define SFISCFG_3 0x3cc /* SFISCfg Channel 3 */ 59*1709Smlf 60*1709Smlf /* 61*1709Smlf * FIFO count and contrl offsets for channel 0-4 62*1709Smlf */ 63*1709Smlf #define FIFO_CNTCTL_0 0x40 64*1709Smlf #define FIFO_CNTCTL_1 0x44 65*1709Smlf #define FIFO_CNTCTL_2 0x240 66*1709Smlf #define FIFO_CNTCTL_3 0x244 67*1709Smlf 68*1709Smlf /* 69*1709Smlf * Errata Sil-AN-0028-C (Sil3512 Rev 0.3) 70*1709Smlf * Errata Sil-AN-0109-B2 (Sil3114 Rev 0.3) 71*1709Smlf * To prevent erroneous ERR set for queued DMA transfers 72*1709Smlf * greater then 8k, FIS reception for FIS0cfg needs to be set 73*1709Smlf * to Accept FIS without Interlock 74*1709Smlf * Default SFISCfg value of 0x10401555 in channel SFISCfg 75*1709Smlf * register need to be changed to 0x10401554. 76*1709Smlf */ 77*1709Smlf #define SFISCFG_ERRATA 0x10401554 78*1709Smlf 79*1709Smlf 80*1709Smlf #define PUT_BAR5_INDIRECT(handle, address, value) \ 81*1709Smlf {\ 82*1709Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 83*1709Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ACCESS, value); \ 84*1709Smlf } 85*1709Smlf 86*1709Smlf #define GET_BAR5_INDIRECT(handle, address, rval) \ 87*1709Smlf {\ 88*1709Smlf pci_config_put32(handle, PCI_CONF_BA5_IND_ADDRESS, address); \ 89*1709Smlf rval = pci_config_get32(handle, PCI_CONF_BA5_IND_ACCESS); \ 90*1709Smlf } 91*1709Smlf 92*1709Smlf uint_t sil3xxx_init_controller(dev_info_t *, ushort_t, ushort_t); 93*1709Smlf 94*1709Smlf #ifdef __cplusplus 95*1709Smlf } 96*1709Smlf #endif 97*1709Smlf 98*1709Smlf #endif /* _SIL3XXX_H */ 99