1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 #include <sys/cpu.h> 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 50 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 51 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 52 void *a, void *v); 53 static uint_t ata_intr(caddr_t arg); 54 55 /* 56 * GHD Entry points 57 */ 58 59 static int ata_get_status(void *hba_handle, void *intr_status); 60 static void ata_process_intr(void *hba_handle, void *intr_status); 61 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 62 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 63 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 64 gtgt_t *gtgtp, gact_t action, int calltype); 65 66 /* 67 * Local Function Prototypes 68 */ 69 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 70 uint_t flags, char *name, int defvalue); 71 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 72 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 73 int *DoneFlgp); 74 static void ata_destroy_controller(dev_info_t *dip); 75 static int ata_drive_type(uchar_t drvhd, 76 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 77 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 78 struct ata_id *ata_id_bufp); 79 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 80 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 81 uchar_t targ, uchar_t lun); 82 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 83 dev_info_t *tdip); 84 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 85 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 86 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 87 static int ata_setup_ioaddr(dev_info_t *dip, 88 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 89 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 90 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 91 static int ata_software_reset(ata_ctl_t *ata_ctlp); 92 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 93 ata_pkt_t *ata_pktp); 94 static int ata_strncmp(char *p1, char *p2, int cnt); 95 static void ata_uninit_drive(ata_drv_t *ata_drvp); 96 97 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 98 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 99 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 100 static int ata_spec_init_controller(dev_info_t *dip); 101 102 103 /* 104 * Local static data 105 */ 106 static void *ata_state; 107 108 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 109 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 110 111 int ata_hba_start_watchdog = 1000; 112 int ata_process_intr_watchdog = 1000; 113 int ata_reset_bus_watchdog = 1000; 114 115 116 /* 117 * number of seconds to wait during various operations 118 */ 119 int ata_flush_delay = 5 * 1000000; 120 uint_t ata_set_feature_wait = 4 * 1000000; 121 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 122 123 /* 124 * Change this for SFF-8070i support. Currently SFF-8070i is 125 * using a field in the IDENTIFY PACKET DEVICE response which 126 * already seems to be in use by some vendor's drives. I suspect 127 * SFF will either move their laslun field or provide a reliable 128 * way to validate it. 129 */ 130 int ata_enable_atapi_luns = FALSE; 131 132 /* 133 * set this to disable all DMA requests 134 */ 135 int ata_dma_disabled = FALSE; 136 137 /* 138 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 139 * "ata" or "atapi" property. 140 */ 141 int ata_id_debug = FALSE; 142 143 /* 144 * set this to TRUE to enable logging device-capability data 145 */ 146 int ata_capability_data = FALSE; 147 148 /* 149 * DMA selection message pointers 150 */ 151 char *ata_cntrl_DMA_sel_msg; 152 char *ata_dev_DMA_sel_msg; 153 154 /* 155 * bus nexus operations 156 */ 157 static struct bus_ops ata_bus_ops; 158 static struct bus_ops *scsa_bus_ops_p; 159 160 /* ARGSUSED */ 161 static int 162 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 163 { 164 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 165 return (ENXIO); 166 167 return (0); 168 } 169 170 /* 171 * The purpose of this function is to pass the ioaddress of the controller 172 * to the caller, specifically used for upgrade from pre-pciide 173 * to pciide nodes 174 */ 175 /* ARGSUSED */ 176 static int 177 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 178 { 179 ata_ctl_t *ata_ctlp; 180 char buf[18]; 181 long len; 182 183 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 184 185 if (ata_ctlp == NULL) 186 return (ENXIO); 187 188 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 189 190 len = strlen(buf) - uio_p->uio_offset; 191 len = min(uio_p->uio_resid, len); 192 if (len <= 0) 193 return (0); 194 195 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 196 UIO_READ, uio_p)); 197 } 198 199 int 200 ata_devo_reset( 201 dev_info_t *dip, 202 ddi_reset_cmd_t cmd) 203 { 204 ata_ctl_t *ata_ctlp; 205 ata_drv_t *ata_drvp; 206 int instance; 207 int i; 208 int rc; 209 int flush_okay; 210 211 if (cmd != DDI_RESET_FORCE) 212 return (0); 213 214 instance = ddi_get_instance(dip); 215 ata_ctlp = ddi_get_soft_state(ata_state, instance); 216 217 if (!ata_ctlp) 218 return (0); 219 220 /* 221 * reset ATA drives and flush the write cache of any drives 222 */ 223 flush_okay = TRUE; 224 for (i = 0; i < ATA_MAXTARG; i++) { 225 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 226 continue; 227 /* Don't revert to defaults for certain IBM drives */ 228 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 229 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 230 /* Enable revert to defaults when reset */ 231 (void) ata_set_feature(ata_ctlp, ata_drvp, 0xCC, 0); 232 } 233 234 /* 235 * skip flush cache if device type is cdrom 236 * 237 * notes: the structure definitions for ata_drvp->ad_id are 238 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 239 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 240 */ 241 if (!IS_CDROM(ata_drvp)) { 242 243 /* 244 * Try the ATA/ATAPI flush write cache command 245 */ 246 rc = ata_flush_cache(ata_ctlp, ata_drvp); 247 ADBG_WARN(("ata_flush_cache %s\n", 248 rc ? "okay" : "failed")); 249 250 if (!rc) 251 flush_okay = FALSE; 252 } 253 254 255 /* 256 * do something else if flush cache not supported 257 */ 258 } 259 260 /* 261 * just busy wait if any drive doesn't support FLUSH CACHE 262 */ 263 if (!flush_okay) 264 drv_usecwait(ata_flush_delay); 265 return (0); 266 } 267 268 269 static struct cb_ops ata_cb_ops = { 270 ata_open, /* open */ 271 nulldev, /* close */ 272 nodev, /* strategy */ 273 nodev, /* print */ 274 nodev, /* dump */ 275 ata_read, /* read */ 276 nodev, /* write */ 277 nodev, /* ioctl */ 278 nodev, /* devmap */ 279 nodev, /* mmap */ 280 nodev, /* segmap */ 281 nochpoll, /* chpoll */ 282 ddi_prop_op, /* prop_op */ 283 NULL, /* stream info */ 284 D_MP, /* driver compatibility flag */ 285 CB_REV, /* cb_ops revision */ 286 nodev, /* aread */ 287 nodev /* awrite */ 288 }; 289 290 static struct dev_ops ata_ops = { 291 DEVO_REV, /* devo_rev, */ 292 0, /* refcnt */ 293 ddi_getinfo_1to1, /* info */ 294 nulldev, /* identify */ 295 NULL, /* probe */ 296 ata_attach, /* attach */ 297 ata_detach, /* detach */ 298 ata_devo_reset, /* reset */ 299 &ata_cb_ops, /* driver operations */ 300 NULL /* bus operations */ 301 }; 302 303 /* driver loadable module wrapper */ 304 static struct modldrv modldrv = { 305 &mod_driverops, /* Type of module. This one is a driver */ 306 "ATA AT-bus attachment disk controller Driver", /* module name */ 307 &ata_ops, /* driver ops */ 308 }; 309 310 static struct modlinkage modlinkage = { 311 MODREV_1, (void *)&modldrv, NULL 312 }; 313 314 #ifdef ATA_DEBUG 315 int ata_debug_init = FALSE; 316 int ata_debug_attach = FALSE; 317 318 int ata_debug = ADBG_FLAG_ERROR 319 /* | ADBG_FLAG_ARQ */ 320 /* | ADBG_FLAG_INIT */ 321 /* | ADBG_FLAG_TRACE */ 322 /* | ADBG_FLAG_TRANSPORT */ 323 /* | ADBG_FLAG_WARN */ 324 ; 325 #endif 326 327 int 328 _init(void) 329 { 330 int err; 331 332 #ifdef ATA_DEBUG 333 if (ata_debug_init) 334 debug_enter("\nATA _INIT\n"); 335 #endif 336 337 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 338 return (err); 339 340 if ((err = scsi_hba_init(&modlinkage)) != 0) { 341 ddi_soft_state_fini(&ata_state); 342 return (err); 343 } 344 345 /* save pointer to SCSA provided bus_ops struct */ 346 scsa_bus_ops_p = ata_ops.devo_bus_ops; 347 348 /* make a copy of SCSA bus_ops */ 349 ata_bus_ops = *(ata_ops.devo_bus_ops); 350 351 /* 352 * Modify our bus_ops to call our routines. Our implementation 353 * will determine if the device is ATA or ATAPI/SCSA and react 354 * accordingly. 355 */ 356 ata_bus_ops.bus_ctl = ata_bus_ctl; 357 358 /* patch our bus_ops into the dev_ops struct */ 359 ata_ops.devo_bus_ops = &ata_bus_ops; 360 361 if ((err = mod_install(&modlinkage)) != 0) { 362 scsi_hba_fini(&modlinkage); 363 ddi_soft_state_fini(&ata_state); 364 } 365 366 /* 367 * Initialize the per driver timer info. 368 */ 369 370 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 371 372 return (err); 373 } 374 375 int 376 _fini(void) 377 { 378 int err; 379 380 if ((err = mod_remove(&modlinkage)) == 0) { 381 ghd_timer_fini(&ata_timer_conf); 382 scsi_hba_fini(&modlinkage); 383 ddi_soft_state_fini(&ata_state); 384 } 385 386 return (err); 387 } 388 389 int 390 _info(struct modinfo *modinfop) 391 { 392 return (mod_info(&modlinkage, modinfop)); 393 } 394 395 396 /* 397 * 398 * driver attach entry point 399 * 400 */ 401 402 static int 403 ata_attach( 404 dev_info_t *dip, 405 ddi_attach_cmd_t cmd) 406 { 407 ata_ctl_t *ata_ctlp; 408 ata_drv_t *ata_drvp; 409 ata_drv_t *first_drvp = NULL; 410 uchar_t targ; 411 uchar_t lun; 412 uchar_t lastlun; 413 int atapi_count = 0; 414 int disk_count = 0; 415 416 ADBG_TRACE(("ata_attach entered\n")); 417 #ifdef ATA_DEBUG 418 if (ata_debug_attach) 419 debug_enter("\nATA_ATTACH\n\n"); 420 #endif 421 422 if (cmd != DDI_ATTACH) 423 return (DDI_FAILURE); 424 425 /* initialize controller */ 426 ata_ctlp = ata_init_controller(dip); 427 428 if (ata_ctlp == NULL) 429 goto errout; 430 431 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 432 433 /* initialize drives */ 434 435 for (targ = 0; targ < ATA_MAXTARG; targ++) { 436 437 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 438 if (ata_drvp == NULL) 439 continue; 440 441 if (first_drvp == NULL) 442 first_drvp = ata_drvp; 443 444 if (ATAPIDRV(ata_drvp)) { 445 atapi_count++; 446 lastlun = ata_drvp->ad_id.ai_lastlun; 447 } else { 448 disk_count++; 449 lastlun = 0; 450 } 451 452 /* 453 * LUN support is currently disabled. Check with SFF-8070i 454 * before enabling. 455 */ 456 if (!ata_enable_atapi_luns) 457 lastlun = 0; 458 459 /* Initialize higher LUNs, if there are any */ 460 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 461 if ((ata_drvp = 462 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 463 ata_show_transfer_mode(ata_ctlp, ata_drvp); 464 } 465 } 466 } 467 468 if ((atapi_count == 0) && (disk_count == 0)) { 469 ADBG_WARN(("ata_attach: no drives detected\n")); 470 goto errout1; 471 } 472 473 /* 474 * Always make certain that a valid drive is selected so 475 * that routines which poll the status register don't get 476 * confused by non-existent drives. 477 */ 478 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 479 first_drvp->ad_drive_bits); 480 ata_nsecwait(400); 481 482 /* 483 * make certain the drive selected 484 */ 485 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 486 0, ATS_BSY, 5000000)) { 487 ADBG_ERROR(("ata_attach: select failed\n")); 488 } 489 490 /* 491 * initialize atapi/ata_dsk modules if we have at least 492 * one drive of that type. 493 */ 494 495 if (atapi_count) { 496 if (!atapi_attach(ata_ctlp)) 497 goto errout1; 498 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 499 } 500 501 if (disk_count) { 502 if (!ata_disk_attach(ata_ctlp)) 503 goto errout1; 504 ata_ctlp->ac_flags |= AC_DISK_INIT; 505 } 506 507 /* 508 * make certain the interrupt and error latches are clear 509 */ 510 if (ata_ctlp->ac_pciide) { 511 512 int instance = ddi_get_instance(dip); 513 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 514 DDI_PSEUDO, 0) != DDI_SUCCESS) { 515 goto errout1; 516 } 517 518 (void) ata_pciide_status_clear(ata_ctlp); 519 520 } 521 522 /* 523 * enable the interrupt handler and drop the mutex 524 */ 525 ata_ctlp->ac_flags |= AC_ATTACHED; 526 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 527 528 ddi_report_dev(dip); 529 return (DDI_SUCCESS); 530 531 errout1: 532 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 533 errout: 534 (void) ata_detach(dip, DDI_DETACH); 535 return (DDI_FAILURE); 536 } 537 538 /* driver detach entry point */ 539 540 static int 541 ata_detach( 542 dev_info_t *dip, 543 ddi_detach_cmd_t cmd) 544 { 545 ata_ctl_t *ata_ctlp; 546 ata_drv_t *ata_drvp; 547 int instance; 548 int i; 549 int j; 550 551 ADBG_TRACE(("ata_detach entered\n")); 552 553 if (cmd != DDI_DETACH) 554 return (DDI_FAILURE); 555 556 instance = ddi_get_instance(dip); 557 ata_ctlp = ddi_get_soft_state(ata_state, instance); 558 559 if (!ata_ctlp) 560 return (DDI_SUCCESS); 561 562 ata_ctlp->ac_flags &= ~AC_ATTACHED; 563 564 /* destroy ata module */ 565 if (ata_ctlp->ac_flags & AC_DISK_INIT) 566 ata_disk_detach(ata_ctlp); 567 568 /* destroy atapi module */ 569 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 570 atapi_detach(ata_ctlp); 571 572 ddi_remove_minor_node(dip, NULL); 573 574 /* destroy drives */ 575 for (i = 0; i < ATA_MAXTARG; i++) { 576 for (j = 0; j < ATA_MAXLUN; j++) { 577 ata_drvp = CTL2DRV(ata_ctlp, i, j); 578 if (ata_drvp != NULL) 579 ata_uninit_drive(ata_drvp); 580 } 581 } 582 583 if (ata_ctlp->ac_iohandle1) 584 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 585 if (ata_ctlp->ac_iohandle2) 586 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 587 if (ata_ctlp->ac_bmhandle) 588 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 589 590 /* destroy controller */ 591 ata_destroy_controller(dip); 592 593 ddi_prop_remove_all(dip); 594 595 return (DDI_SUCCESS); 596 } 597 598 /* 599 * Nexus driver bus_ctl entry point 600 */ 601 /*ARGSUSED*/ 602 static int 603 ata_bus_ctl( 604 dev_info_t *d, 605 dev_info_t *r, 606 ddi_ctl_enum_t o, 607 void *a, 608 void *v) 609 { 610 dev_info_t *tdip; 611 int target_type; 612 int rc; 613 char *bufp; 614 615 ADBG_TRACE(("ata_bus_ctl entered\n")); 616 617 switch (o) { 618 619 case DDI_CTLOPS_SIDDEV: 620 return (DDI_FAILURE); 621 622 case DDI_CTLOPS_IOMIN: 623 624 /* 625 * Since we use PIO, we return a minimum I/O size of 626 * one byte. This will need to be updated when we 627 * implement DMA support 628 */ 629 630 *((int *)v) = 1; 631 return (DDI_SUCCESS); 632 633 case DDI_CTLOPS_DMAPMAPC: 634 case DDI_CTLOPS_REPORTINT: 635 case DDI_CTLOPS_REGSIZE: 636 case DDI_CTLOPS_NREGS: 637 case DDI_CTLOPS_SLAVEONLY: 638 case DDI_CTLOPS_AFFINITY: 639 case DDI_CTLOPS_POKE: 640 case DDI_CTLOPS_PEEK: 641 642 /* These ops shouldn't be called by a target driver */ 643 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 644 ddi_driver_name(d), ddi_get_instance(d), o, 645 ddi_driver_name(r), ddi_get_instance(r))); 646 647 return (DDI_FAILURE); 648 649 case DDI_CTLOPS_REPORTDEV: 650 case DDI_CTLOPS_INITCHILD: 651 case DDI_CTLOPS_UNINITCHILD: 652 653 /* these require special handling below */ 654 break; 655 656 default: 657 return (ddi_ctlops(d, r, o, a, v)); 658 } 659 660 /* get targets dip */ 661 662 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 663 tdip = (dev_info_t *)a; 664 else 665 tdip = r; 666 667 /* 668 * XXX - Get class of target 669 * Before the "class" entry in a conf file becomes 670 * a real property, we use an additional property 671 * tentatively called "class_prop". We will require that 672 * new classes (ie. direct) export "class_prop". 673 * SCSA target drivers will not have this property, so 674 * no property implies SCSA. 675 */ 676 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 677 "class", &bufp) == DDI_PROP_SUCCESS) || 678 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 679 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 680 if (strcmp(bufp, "dada") == 0) 681 target_type = ATA_DEV_DISK; 682 else if (strcmp(bufp, "scsi") == 0) 683 target_type = ATA_DEV_ATAPI; 684 else { 685 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 686 bufp)); 687 ddi_prop_free(bufp); 688 return (DDI_FAILURE); 689 } 690 ddi_prop_free(bufp); 691 } else { 692 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 693 } 694 695 if (o == DDI_CTLOPS_INITCHILD) { 696 int instance = ddi_get_instance(d); 697 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 698 ata_drv_t *ata_drvp; 699 int targ; 700 int lun; 701 int drive_type; 702 char *disk_prop; 703 char *class_prop; 704 705 if (ata_ctlp == NULL) { 706 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 707 return (DDI_FAILURE); 708 } 709 710 /* get (target,lun) of child device */ 711 712 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 713 "target", -1); 714 if (targ == -1) { 715 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 716 return (DDI_FAILURE); 717 } 718 719 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 720 "lun", 0); 721 722 if ((targ < 0) || (targ >= ATA_MAXTARG) || 723 (lun < 0) || (lun >= ATA_MAXLUN)) { 724 return (DDI_FAILURE); 725 } 726 727 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 728 729 if (ata_drvp == NULL) 730 return (DDI_FAILURE); /* no drive */ 731 732 /* get type of device */ 733 734 if (ATAPIDRV(ata_drvp)) 735 drive_type = ATA_DEV_ATAPI; 736 else 737 drive_type = ATA_DEV_DISK; 738 739 /* 740 * Check for special handling when child driver is 741 * cmdk (which morphs to the correct interface) 742 */ 743 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 744 745 if ((target_type == ATA_DEV_DISK) && 746 (target_type != drive_type)) 747 return (DDI_FAILURE); 748 749 target_type = drive_type; 750 751 if (drive_type == ATA_DEV_ATAPI) { 752 class_prop = "scsi"; 753 } else { 754 disk_prop = "dadk"; 755 class_prop = "dada"; 756 757 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 758 "disk", disk_prop) != DDI_PROP_SUCCESS) { 759 ADBG_WARN(("ata_bus_ctl: failed to " 760 "create disk prop\n")); 761 return (DDI_FAILURE); 762 } 763 } 764 765 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 766 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 767 ADBG_WARN(("ata_bus_ctl: failed to " 768 "create class prop\n")); 769 return (DDI_FAILURE); 770 } 771 } 772 773 /* Check that target class matches the device */ 774 775 if (target_type != drive_type) 776 return (DDI_FAILURE); 777 778 /* save pointer to drive struct for ata_disk_bus_ctl */ 779 ddi_set_driver_private(tdip, ata_drvp); 780 781 /* 782 * Determine whether to enable DMA support for this drive. This 783 * check is deferred to this point so that the various dma 784 * properties could reside on the devinfo node should finer 785 * grained dma control be required. 786 */ 787 ata_drvp->ad_pciide_dma = ata_init_drive_pcidma(ata_ctlp, 788 ata_drvp, tdip); 789 ata_show_transfer_mode(ata_ctlp, ata_drvp); 790 } 791 792 if (target_type == ATA_DEV_ATAPI) { 793 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 794 } else { 795 rc = ata_disk_bus_ctl(d, r, o, a, v); 796 } 797 798 return (rc); 799 } 800 801 /* 802 * 803 * GHD ccc_hba_complete callback 804 * 805 */ 806 807 /* ARGSUSED */ 808 static void 809 ata_hba_complete( 810 void *hba_handle, 811 gcmd_t *gcmdp, 812 int do_callback) 813 { 814 ata_drv_t *ata_drvp; 815 ata_pkt_t *ata_pktp; 816 817 ADBG_TRACE(("ata_hba_complete entered\n")); 818 819 ata_drvp = GCMD2DRV(gcmdp); 820 ata_pktp = GCMD2APKT(gcmdp); 821 if (ata_pktp->ap_complete) 822 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 823 do_callback); 824 } 825 826 /* GHD ccc_timeout_func callback */ 827 828 /* ARGSUSED */ 829 static int 830 ata_timeout_func( 831 void *hba_handle, 832 gcmd_t *gcmdp, 833 gtgt_t *gtgtp, 834 gact_t action, 835 int calltype) 836 { 837 ata_ctl_t *ata_ctlp; 838 ata_pkt_t *ata_pktp; 839 840 ADBG_TRACE(("ata_timeout_func entered\n")); 841 842 ata_ctlp = (ata_ctl_t *)hba_handle; 843 844 if (gcmdp != NULL) 845 ata_pktp = GCMD2APKT(gcmdp); 846 else 847 ata_pktp = NULL; 848 849 switch (action) { 850 case GACTION_EARLY_ABORT: 851 /* abort before request was started */ 852 if (ata_pktp != NULL) { 853 ata_pktp->ap_flags |= AP_ABORT; 854 } 855 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 856 return (TRUE); 857 858 case GACTION_EARLY_TIMEOUT: 859 /* timeout before request was started */ 860 if (ata_pktp != NULL) { 861 ata_pktp->ap_flags |= AP_TIMEOUT; 862 } 863 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 864 return (TRUE); 865 866 case GACTION_RESET_TARGET: 867 /* 868 * Reset a device is not supported. Resetting a specific 869 * device can't be done at all to an ATA device and if 870 * you send a RESET to an ATAPI device you have to 871 * reset the whole bus to make certain both devices 872 * on the bus stay in sync regarding which device is 873 * the currently selected one. 874 */ 875 return (FALSE); 876 877 case GACTION_RESET_BUS: 878 /* 879 * Issue bus reset and reinitialize both drives. 880 * But only if this is a timed-out request. Target 881 * driver reset requests are ignored because ATA 882 * and ATAPI devices shouldn't be gratuitously reset. 883 */ 884 if (gcmdp == NULL) 885 break; 886 return (ata_reset_bus(ata_ctlp)); 887 default: 888 break; 889 } 890 return (FALSE); 891 } 892 893 /* 894 * 895 * Initialize controller's soft-state structure 896 * 897 */ 898 899 static ata_ctl_t * 900 ata_init_controller( 901 dev_info_t *dip) 902 { 903 ata_ctl_t *ata_ctlp; 904 int instance; 905 caddr_t ioaddr1; 906 caddr_t ioaddr2; 907 908 ADBG_TRACE(("ata_init_controller entered\n")); 909 910 instance = ddi_get_instance(dip); 911 912 /* allocate controller structure */ 913 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 914 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 915 return (NULL); 916 } 917 918 ata_ctlp = ddi_get_soft_state(ata_state, instance); 919 920 if (ata_ctlp == NULL) { 921 ADBG_WARN(("ata_init_controller: failed to find " 922 "controller struct\n")); 923 return (NULL); 924 } 925 926 /* 927 * initialize per-controller data 928 */ 929 ata_ctlp->ac_dip = dip; 930 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 931 932 /* 933 * map the device registers 934 */ 935 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 936 &ata_ctlp->ac_iohandle2, &ioaddr2, 937 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 938 (void) ata_detach(dip, DDI_DETACH); 939 return (NULL); 940 } 941 942 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 943 ioaddr1, ioaddr2)); 944 945 /* 946 * Do ARQ setup 947 */ 948 atapi_init_arq(ata_ctlp); 949 950 /* 951 * Do PCI-IDE setup 952 */ 953 ata_init_pciide(dip, ata_ctlp); 954 955 /* 956 * port addresses associated with ioaddr1 957 */ 958 ata_ctlp->ac_ioaddr1 = ioaddr1; 959 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 960 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 961 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 962 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 963 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 964 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 965 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 966 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 967 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 968 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 969 970 /* 971 * port addresses associated with ioaddr2 972 */ 973 ata_ctlp->ac_ioaddr2 = ioaddr2; 974 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 975 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 976 977 /* 978 * If AC_BSY_WAIT needs to be set for laptops that do 979 * suspend/resume but do not correctly wait for the busy bit to 980 * drop after a resume. 981 */ 982 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 983 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 984 /* 985 * get max transfer size, default to 256 sectors 986 */ 987 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 988 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 989 if (ata_ctlp->ac_max_transfer < 1) 990 ata_ctlp->ac_max_transfer = 1; 991 if (ata_ctlp->ac_max_transfer > 0x100) 992 ata_ctlp->ac_max_transfer = 0x100; 993 994 /* 995 * Get the standby timer value 996 */ 997 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 998 dip, DDI_PROP_DONTPASS, "standby", -1); 999 1000 /* 1001 * If this is a /pci/pci-ide instance check to see if 1002 * it's supposed to be attached as an /isa/ata 1003 */ 1004 if (ata_ctlp->ac_pciide) { 1005 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1006 int addr1 = (intptr_t)ioaddr1; 1007 1008 1009 if (addr1 < 0 || addr1 > 0xffff) { 1010 (void) ata_detach(dip, DDI_DETACH); 1011 return (NULL); 1012 } 1013 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1014 addr1); 1015 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1016 DDI_PROP_DONTPASS, prop_buf)) { 1017 (void) ata_detach(dip, DDI_DETACH); 1018 return (NULL); 1019 } 1020 } 1021 1022 /* Init controller specific stuff */ 1023 (void) ata_spec_init_controller(dip); 1024 1025 /* 1026 * initialize GHD 1027 */ 1028 1029 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1030 1031 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1032 atapi_ccballoc, atapi_ccbfree, 1033 ata_pciide_dma_sg_func, ata_hba_start, 1034 ata_hba_complete, ata_intr, 1035 ata_get_status, ata_process_intr, ata_timeout_func, 1036 &ata_timer_conf, NULL)) { 1037 (void) ata_detach(dip, DDI_DETACH); 1038 return (NULL); 1039 } 1040 1041 ata_ctlp->ac_flags |= AC_GHD_INIT; 1042 return (ata_ctlp); 1043 } 1044 1045 /* destroy a controller */ 1046 1047 static void 1048 ata_destroy_controller( 1049 dev_info_t *dip) 1050 { 1051 ata_ctl_t *ata_ctlp; 1052 int instance; 1053 1054 ADBG_TRACE(("ata_destroy_controller entered\n")); 1055 1056 instance = ddi_get_instance(dip); 1057 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1058 1059 if (ata_ctlp == NULL) 1060 return; 1061 1062 /* destroy ghd */ 1063 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1064 ghd_unregister(&ata_ctlp->ac_ccc); 1065 1066 /* free the pciide buffer (if any) */ 1067 ata_pciide_free(ata_ctlp); 1068 1069 /* destroy controller struct */ 1070 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1071 ddi_soft_state_free(ata_state, instance); 1072 1073 } 1074 1075 1076 /* 1077 * 1078 * initialize a drive 1079 * 1080 */ 1081 1082 static ata_drv_t * 1083 ata_init_drive( 1084 ata_ctl_t *ata_ctlp, 1085 uchar_t targ, 1086 uchar_t lun) 1087 { 1088 static char nec_260[] = "NEC CD-ROM DRIVE"; 1089 ata_drv_t *ata_drvp; 1090 struct ata_id *aidp; 1091 char buf[80]; 1092 int drive_type; 1093 int i; 1094 int valid_version = 0; 1095 1096 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1097 targ, lun)); 1098 1099 /* check if device already exists */ 1100 1101 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1102 1103 if (ata_drvp != NULL) 1104 return (ata_drvp); 1105 1106 /* allocate new device structure */ 1107 1108 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1109 aidp = &ata_drvp->ad_id; 1110 1111 /* 1112 * set up drive struct 1113 */ 1114 ata_drvp->ad_ctlp = ata_ctlp; 1115 ata_drvp->ad_targ = targ; 1116 ata_drvp->ad_drive_bits = 1117 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1118 /* 1119 * Add the LUN for SFF-8070i support 1120 */ 1121 ata_drvp->ad_lun = lun; 1122 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1123 1124 /* 1125 * get drive type, side effect is to collect 1126 * IDENTIFY DRIVE data 1127 */ 1128 1129 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1130 ata_ctlp->ac_iohandle1, 1131 ata_ctlp->ac_ioaddr1, 1132 ata_ctlp->ac_iohandle2, 1133 ata_ctlp->ac_ioaddr2, 1134 aidp); 1135 1136 switch (drive_type) { 1137 case ATA_DEV_NONE: 1138 /* no drive found */ 1139 goto errout; 1140 case ATA_DEV_ATAPI: 1141 ata_drvp->ad_flags |= AD_ATAPI; 1142 break; 1143 case ATA_DEV_DISK: 1144 ata_drvp->ad_flags |= AD_DISK; 1145 break; 1146 } 1147 1148 /* 1149 * swap bytes of all text fields 1150 */ 1151 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1152 swab(aidp->ai_drvser, aidp->ai_drvser, 1153 sizeof (aidp->ai_drvser)); 1154 swab(aidp->ai_fw, aidp->ai_fw, 1155 sizeof (aidp->ai_fw)); 1156 swab(aidp->ai_model, aidp->ai_model, 1157 sizeof (aidp->ai_model)); 1158 } 1159 1160 /* 1161 * Check if this drive has the Single Sector bug 1162 */ 1163 1164 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1165 ata_drvp->ad_flags |= AD_1SECTOR; 1166 else 1167 ata_drvp->ad_flags &= ~AD_1SECTOR; 1168 1169 /* Check if this drive has the "revert to defaults" bug */ 1170 if (!ata_check_revert_to_defaults(ata_drvp)) 1171 ata_drvp->ad_flags |= AD_NORVRT; 1172 1173 /* Dump the drive info */ 1174 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1175 buf[sizeof (aidp->ai_model)-1] = '\0'; 1176 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1177 buf[i] = '\0'; 1178 1179 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1180 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1181 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1182 1183 ATAPRT(("?\tmodel %s\n", buf)); 1184 1185 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1186 for (i = 14; i >= 2; i--) { 1187 if (aidp->ai_majorversion & (1 << i)) { 1188 valid_version = i; 1189 break; 1190 } 1191 } 1192 ATAPRT(( 1193 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1194 valid_version, 1195 aidp->ai_majorversion, 1196 aidp->ai_minorversion)); 1197 } 1198 1199 if (ata_capability_data) { 1200 1201 ATAPRT(("?\t\tstat %x, err %x\n", 1202 ddi_get8(ata_ctlp->ac_iohandle2, 1203 ata_ctlp->ac_altstatus), 1204 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1205 1206 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1207 aidp->ai_config, 1208 aidp->ai_cap)); 1209 1210 /* 1211 * Be aware that ATA-6 and later drives may not provide valid 1212 * geometry information and other obsoleted info. 1213 * Select what is printed based on supported ATA model (skip 1214 * anything below ATA/ATAPI-3) 1215 */ 1216 1217 if (valid_version == 0 || aidp->ai_majorversion < 1218 ATAC_MAJVER_6) { 1219 /* 1220 * Supported version less then ATA-6 1221 */ 1222 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1223 aidp->ai_fixcyls, 1224 aidp->ai_heads, 1225 aidp->ai_sectors)); 1226 } 1227 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1228 aidp->ai_mult1, 1229 aidp->ai_mult2)); 1230 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1231 ATAPRT(( 1232 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1233 aidp->ai_piomode, 1234 aidp->ai_dmamode, 1235 aidp->ai_advpiomode)); 1236 } else { 1237 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1238 aidp->ai_advpiomode)); 1239 } 1240 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1241 aidp->ai_minpio, 1242 aidp->ai_minpioflow)); 1243 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1244 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1245 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1246 aidp->ai_dworddma, 1247 aidp->ai_ultradma)); 1248 } else { 1249 ATAPRT(("?\t\tdwdma 0x%x\n", 1250 aidp->ai_dworddma)); 1251 } 1252 } 1253 1254 if (ATAPIDRV(ata_drvp)) { 1255 if (!atapi_init_drive(ata_drvp)) 1256 goto errout; 1257 } else { 1258 if (!ata_disk_init_drive(ata_drvp)) 1259 goto errout; 1260 } 1261 1262 /* 1263 * store pointer in controller struct 1264 */ 1265 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1266 1267 /* 1268 * lock the drive's current settings in case I have to 1269 * reset the drive due to some sort of error 1270 */ 1271 (void) ata_set_feature(ata_ctlp, ata_drvp, 0x66, 0); 1272 1273 return (ata_drvp); 1274 1275 errout: 1276 ata_uninit_drive(ata_drvp); 1277 return (NULL); 1278 } 1279 1280 /* destroy a drive */ 1281 1282 static void 1283 ata_uninit_drive( 1284 ata_drv_t *ata_drvp) 1285 { 1286 #if 0 1287 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1288 #endif 1289 1290 ADBG_TRACE(("ata_uninit_drive entered\n")); 1291 1292 #if 0 1293 /* 1294 * DON'T DO THIS. disabling interrupts floats the IRQ line 1295 * which generates spurious interrupts 1296 */ 1297 1298 /* 1299 * Select the correct drive 1300 */ 1301 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1302 ata_drvp->ad_drive_bits); 1303 ata_nsecwait(400); 1304 1305 /* 1306 * Disable interrupts from the drive 1307 */ 1308 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1309 (ATDC_D3 | ATDC_NIEN)); 1310 #endif 1311 1312 /* interface specific clean-ups */ 1313 1314 if (ata_drvp->ad_flags & AD_ATAPI) 1315 atapi_uninit_drive(ata_drvp); 1316 else if (ata_drvp->ad_flags & AD_DISK) 1317 ata_disk_uninit_drive(ata_drvp); 1318 1319 /* free drive struct */ 1320 1321 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1322 } 1323 1324 1325 /* 1326 * ata_drive_type() 1327 * 1328 * The timeout values and exact sequence of checking is critical 1329 * especially for atapi device detection, and should not be changed lightly. 1330 * 1331 */ 1332 static int 1333 ata_drive_type( 1334 uchar_t drvhd, 1335 ddi_acc_handle_t io_hdl1, 1336 caddr_t ioaddr1, 1337 ddi_acc_handle_t io_hdl2, 1338 caddr_t ioaddr2, 1339 struct ata_id *ata_id_bufp) 1340 { 1341 uchar_t status; 1342 1343 ADBG_TRACE(("ata_drive_type entered\n")); 1344 1345 /* 1346 * select the appropriate drive and LUN 1347 */ 1348 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1349 ata_nsecwait(400); 1350 1351 /* 1352 * make certain the drive is selected, and wait for not busy 1353 */ 1354 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1355 5 * 1000000); 1356 1357 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1358 1359 if (status & ATS_BSY) { 1360 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1361 return (ATA_DEV_NONE); 1362 } 1363 1364 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1365 return (ATA_DEV_DISK); 1366 1367 /* 1368 * No disk, check for atapi unit. 1369 */ 1370 if (!atapi_signature(io_hdl1, ioaddr1)) { 1371 #ifndef ATA_DISABLE_ATAPI_1_7 1372 /* 1373 * Check for old (but prevalent) atapi 1.7B 1374 * spec device, the only known example is the 1375 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1376 * compliant). This device has no signature 1377 * and requires conversion from hex to BCD 1378 * for some scsi audio commands. 1379 */ 1380 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1381 return (ATA_DEV_ATAPI); 1382 } 1383 #endif 1384 return (ATA_DEV_NONE); 1385 } 1386 1387 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1388 return (ATA_DEV_ATAPI); 1389 } 1390 1391 return (ATA_DEV_NONE); 1392 1393 } 1394 1395 /* 1396 * nsec-granularity time delay function 1397 */ 1398 void 1399 ata_nsecwait(clock_t count) 1400 { 1401 extern int tsc_gethrtime_initted; 1402 1403 if (tsc_gethrtime_initted) { 1404 hrtime_t end = gethrtime() + count; 1405 1406 while (gethrtime() < end) { 1407 SMT_PAUSE(); 1408 } 1409 } else { 1410 drv_usecwait(1 + (count / 1000)); 1411 } 1412 } 1413 1414 1415 /* 1416 * Wait for a register of a controller to achieve a specific state. 1417 * To return normally, all the bits in the first sub-mask must be ON, 1418 * all the bits in the second sub-mask must be OFF. 1419 * If timeout_usec microseconds pass without the controller achieving 1420 * the desired bit configuration, we return TRUE, else FALSE. 1421 */ 1422 1423 int ata_usec_delay = 10; 1424 1425 int 1426 ata_wait( 1427 ddi_acc_handle_t io_hdl, 1428 caddr_t ioaddr, 1429 uchar_t onbits, 1430 uchar_t offbits, 1431 uint_t timeout_usec) 1432 { 1433 ushort_t val; 1434 hrtime_t deadline = gethrtime() + 1435 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1436 1437 1438 do { 1439 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1440 if ((val & onbits) == onbits && (val & offbits) == 0) 1441 return (TRUE); 1442 drv_usecwait(ata_usec_delay); 1443 } while (gethrtime() < deadline); 1444 1445 return (FALSE); 1446 } 1447 1448 1449 /* 1450 * 1451 * This is a slightly more complicated version that checks 1452 * for error conditions and bails-out rather than looping 1453 * until the timeout expires 1454 */ 1455 int 1456 ata_wait3( 1457 ddi_acc_handle_t io_hdl, 1458 caddr_t ioaddr, 1459 uchar_t onbits1, 1460 uchar_t offbits1, 1461 uchar_t failure_onbits2, 1462 uchar_t failure_offbits2, 1463 uchar_t failure_onbits3, 1464 uchar_t failure_offbits3, 1465 uint_t timeout_usec) 1466 { 1467 ushort_t val; 1468 hrtime_t deadline = gethrtime() + 1469 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1470 1471 do { 1472 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1473 1474 /* 1475 * check for expected condition 1476 */ 1477 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1478 return (TRUE); 1479 1480 /* 1481 * check for error conditions 1482 */ 1483 if ((val & failure_onbits2) == failure_onbits2 && 1484 (val & failure_offbits2) == 0) { 1485 return (FALSE); 1486 } 1487 1488 if ((val & failure_onbits3) == failure_onbits3 && 1489 (val & failure_offbits3) == 0) { 1490 return (FALSE); 1491 } 1492 1493 drv_usecwait(ata_usec_delay); 1494 } while (gethrtime() < deadline); 1495 1496 return (FALSE); 1497 } 1498 1499 1500 /* 1501 * 1502 * low level routine for ata_disk_id() and atapi_id() 1503 * 1504 */ 1505 1506 int 1507 ata_id_common( 1508 uchar_t id_cmd, 1509 int expect_drdy, 1510 ddi_acc_handle_t io_hdl1, 1511 caddr_t ioaddr1, 1512 ddi_acc_handle_t io_hdl2, 1513 caddr_t ioaddr2, 1514 struct ata_id *aidp) 1515 { 1516 uchar_t status; 1517 1518 ADBG_TRACE(("ata_id_common entered\n")); 1519 1520 bzero(aidp, sizeof (struct ata_id)); 1521 1522 /* 1523 * clear the features register 1524 */ 1525 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1526 1527 /* 1528 * Disable interrupts from the device. When the ata 1529 * hardware is sharing its interrupt with another 1530 * device, the shared interrupt might have already been 1531 * unmasked in the interrupt controller and 1532 * triggering ata device interrupts will result in an 1533 * interrupt storm and a hung system. 1534 */ 1535 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1536 1537 /* 1538 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1539 */ 1540 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1541 1542 /* wait for the busy bit to settle */ 1543 ata_nsecwait(400); 1544 1545 /* 1546 * read alternate status and check for conditions which 1547 * may indicate the drive is not present, to prevent getting 1548 * stuck in ata_wait3() below. 1549 */ 1550 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1551 1552 /* 1553 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1554 */ 1555 if ((status == 0x0) || (status == 0x7f) || 1556 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1557 /* invalid status, can't be an ATA or ATAPI device */ 1558 return (FALSE); 1559 } 1560 1561 /* 1562 * According to the ATA specification, some drives may have 1563 * to read the media to complete this command. We need to 1564 * make sure we give them enough time to respond. 1565 */ 1566 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1567 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1568 1569 /* 1570 * read the status byte and clear the pending interrupt 1571 */ 1572 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1573 1574 /* 1575 * this happens if there's no drive present 1576 */ 1577 if (status == 0xff || status == 0x7f) { 1578 /* invalid status, can't be an ATA or ATAPI device */ 1579 return (FALSE); 1580 } 1581 1582 if (status & ATS_BSY) { 1583 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1584 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1585 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1586 return (FALSE); 1587 } 1588 1589 if (!(status & ATS_DRQ)) { 1590 if (status & (ATS_ERR | ATS_DF)) { 1591 return (FALSE); 1592 } 1593 /* 1594 * Give the drive another second to assert DRQ. Some older 1595 * drives de-assert BSY before asserting DRQ. 1596 */ 1597 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1598 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1599 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1600 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1601 return (FALSE); 1602 } 1603 } 1604 1605 /* 1606 * transfer the data 1607 */ 1608 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1609 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1610 1611 /* wait for the busy bit to settle */ 1612 ata_nsecwait(400); 1613 1614 1615 /* 1616 * Wait for the drive to recognize I've read all the data. 1617 * Some drives have been observed to take as much as 3msec to 1618 * deassert DRQ after reading the data; allow 10 msec just in case. 1619 * 1620 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1621 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1622 * safely ignore the DRDY bit since the ATAPI Packet command 1623 * actually doesn't require it to ever be asserted. 1624 * 1625 */ 1626 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1627 (ATS_BSY | ATS_DRQ), 1000000)) { 1628 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1629 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1630 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1631 return (FALSE); 1632 } 1633 1634 /* 1635 * Check to see if the command aborted. This happens if 1636 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1637 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1638 * (non-PACKET) device. 1639 */ 1640 if (status & (ATS_DF | ATS_ERR)) { 1641 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1642 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1643 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1644 return (FALSE); 1645 } 1646 return (TRUE); 1647 } 1648 1649 1650 /* 1651 * Low level routine to issue a non-data command and busy wait for 1652 * the completion status. 1653 */ 1654 1655 int 1656 ata_command( 1657 ata_ctl_t *ata_ctlp, 1658 ata_drv_t *ata_drvp, 1659 int expect_drdy, 1660 int silent, 1661 uint_t busy_wait, 1662 uchar_t cmd, 1663 uchar_t feature, 1664 uchar_t count, 1665 uchar_t sector, 1666 uchar_t head, 1667 uchar_t cyl_low, 1668 uchar_t cyl_hi) 1669 { 1670 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1671 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1672 uchar_t status; 1673 1674 /* select the drive */ 1675 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1676 ata_nsecwait(400); 1677 1678 /* make certain the drive selected */ 1679 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1680 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1681 ATS_BSY, busy_wait)) { 1682 ADBG_ERROR(("ata_command: select failed " 1683 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1684 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1685 expect_drdy, cmd, feature, count, 1686 sector, head, cyl_low, cyl_hi)); 1687 return (FALSE); 1688 } 1689 1690 /* 1691 * set all the regs 1692 */ 1693 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1694 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1695 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1696 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1697 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1698 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1699 1700 /* send the command */ 1701 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1702 1703 /* wait for the busy bit to settle */ 1704 ata_nsecwait(400); 1705 1706 /* wait for not busy */ 1707 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1708 ADBG_ERROR(("ata_command: BSY too long!" 1709 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1710 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1711 expect_drdy, cmd, feature, count, 1712 sector, head, cyl_low, cyl_hi)); 1713 return (FALSE); 1714 } 1715 1716 /* 1717 * wait for DRDY before continuing 1718 */ 1719 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1720 ATS_DRDY, ATS_BSY, /* okay */ 1721 ATS_ERR, ATS_BSY, /* cmd failed */ 1722 ATS_DF, ATS_BSY, /* drive failed */ 1723 busy_wait); 1724 1725 /* read status to clear IRQ, and check for error */ 1726 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1727 1728 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1729 return (TRUE); 1730 1731 if (!silent) { 1732 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1733 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1734 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1735 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1736 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1737 expect_drdy, cmd, feature, count, 1738 sector, head, cyl_low, cyl_hi)); 1739 } 1740 return (FALSE); 1741 } 1742 1743 1744 1745 /* 1746 * 1747 * Issue a SET FEATURES command 1748 * 1749 */ 1750 1751 int 1752 ata_set_feature( 1753 ata_ctl_t *ata_ctlp, 1754 ata_drv_t *ata_drvp, 1755 uchar_t feature, 1756 uchar_t value) 1757 { 1758 int rc; 1759 1760 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1761 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1762 /* feature, count, sector, head, cyl_low, cyl_hi */ 1763 1764 if (rc) { 1765 return (TRUE); 1766 } 1767 1768 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1769 return (FALSE); 1770 } 1771 1772 1773 1774 /* 1775 * 1776 * Issue a FLUSH CACHE command 1777 * 1778 */ 1779 1780 static int 1781 ata_flush_cache( 1782 ata_ctl_t *ata_ctlp, 1783 ata_drv_t *ata_drvp) 1784 { 1785 /* this command is optional so fail silently */ 1786 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1787 ata_flush_cache_wait, 1788 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1789 } 1790 1791 /* 1792 * ata_setup_ioaddr() 1793 * 1794 * Map the device registers and return the handles. 1795 * 1796 * If this is a ISA-ATA controller then only two handles are 1797 * initialized and returned. 1798 * 1799 * If this is a PCI-IDE controller than a third handle (for the 1800 * PCI-IDE Bus Mastering registers) is initialized and returned. 1801 * 1802 */ 1803 1804 static int 1805 ata_setup_ioaddr( 1806 dev_info_t *dip, 1807 ddi_acc_handle_t *handle1p, 1808 caddr_t *addr1p, 1809 ddi_acc_handle_t *handle2p, 1810 caddr_t *addr2p, 1811 ddi_acc_handle_t *bm_hdlp, 1812 caddr_t *bm_addrp) 1813 { 1814 ddi_device_acc_attr_t dev_attr; 1815 char *bufp; 1816 int rnumber; 1817 int rc; 1818 off_t regsize; 1819 1820 /* 1821 * Make certain the controller is enabled and its regs are map-able 1822 * 1823 */ 1824 rc = ddi_dev_regsize(dip, 0, ®size); 1825 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1826 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1827 rc, (long long)regsize)); 1828 return (FALSE); 1829 } 1830 1831 rc = ddi_dev_regsize(dip, 1, ®size); 1832 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1833 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1834 rc, (long long)regsize)); 1835 return (FALSE); 1836 } 1837 1838 /* 1839 * setup the device attribute structure for little-endian, 1840 * strict ordering access. 1841 */ 1842 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1843 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1844 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1845 1846 *handle1p = NULL; 1847 *handle2p = NULL; 1848 *bm_hdlp = NULL; 1849 1850 /* 1851 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1852 */ 1853 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1854 /* it's PNP-ISA, skip over the extra reg tuple */ 1855 rnumber = 1; 1856 goto not_pciide; 1857 } 1858 1859 /* else, it's ISA or PCI-IDE, check further */ 1860 rnumber = 0; 1861 1862 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 1863 DDI_PROP_DONTPASS, "device_type", &bufp); 1864 if (rc != DDI_PROP_SUCCESS) { 1865 ADBG_ERROR(("ata_setup_ioaddr !device_type\n")); 1866 goto not_pciide; 1867 } 1868 1869 if (strcmp(bufp, "pci-ide") != 0) { 1870 /* 1871 * If it's not a PCI-IDE, there are only two reg tuples 1872 * and the first one contains the I/O base (170 or 1f0) 1873 * rather than the controller instance number. 1874 */ 1875 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1876 ddi_prop_free(bufp); 1877 goto not_pciide; 1878 } 1879 ddi_prop_free(bufp); 1880 1881 1882 /* 1883 * Map the correct half of the PCI-IDE Bus Master registers. 1884 * There's a single BAR that maps these registers for both 1885 * controller's in a dual-controller chip and it's upto my 1886 * parent nexus, pciide, to adjust which (based on my instance 1887 * number) half this call maps. 1888 */ 1889 rc = ddi_dev_regsize(dip, 2, ®size); 1890 if (rc != DDI_SUCCESS || regsize < 8) { 1891 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1892 rc, (long long)regsize)); 1893 goto not_pciide; 1894 } 1895 1896 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1897 1898 if (rc != DDI_SUCCESS) { 1899 /* map failed, try to use in non-pci-ide mode */ 1900 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1901 rc)); 1902 *bm_hdlp = NULL; 1903 } 1904 1905 not_pciide: 1906 /* 1907 * map the lower command block registers 1908 */ 1909 1910 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1911 handle1p); 1912 1913 if (rc != DDI_SUCCESS) { 1914 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1915 goto out1; 1916 } 1917 1918 /* 1919 * If the controller is being used in compatibility mode 1920 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1921 * will specify zeros for the I/O ports for the PCI 1922 * instance. 1923 */ 1924 if (*addr1p == 0) { 1925 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1926 goto out2; 1927 } 1928 1929 /* 1930 * map the upper control block registers 1931 */ 1932 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1933 handle2p); 1934 if (rc == DDI_SUCCESS) 1935 return (TRUE); 1936 1937 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1938 1939 out2: 1940 if (*handle1p != NULL) { 1941 ddi_regs_map_free(handle1p); 1942 *handle1p = NULL; 1943 } 1944 1945 out1: 1946 if (*bm_hdlp != NULL) { 1947 ddi_regs_map_free(bm_hdlp); 1948 *bm_hdlp = NULL; 1949 } 1950 return (FALSE); 1951 1952 } 1953 1954 /* 1955 * 1956 * Currently, the only supported controllers are ones which 1957 * support the SFF-8038 Bus Mastering spec. 1958 * 1959 * Check the parent node's IEEE 1275 class-code property to 1960 * determine if it's an PCI-IDE instance which supports SFF-8038 1961 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 1962 * that doesn't do Bus Mastering. In that case, my interrupt handler 1963 * only uses the interrupt latch bit in PCI-IDE status register. 1964 * The assumption is that the programming interface byte of the 1965 * class-code property reflects the bus master DMA capability of 1966 * the controller. 1967 * 1968 * Whether the drive support supports the DMA option still needs 1969 * to be checked later. Each individual request also has to be 1970 * checked for alignment and size to decide whether to use the 1971 * DMA transfer mode. 1972 */ 1973 1974 static void 1975 ata_init_pciide( 1976 dev_info_t *dip, 1977 ata_ctl_t *ata_ctlp) 1978 { 1979 uint_t class_code; 1980 uchar_t status; 1981 1982 ata_cntrl_DMA_sel_msg = NULL; 1983 1984 if (ata_ctlp->ac_bmhandle == NULL) { 1985 ata_ctlp->ac_pciide = FALSE; 1986 ata_ctlp->ac_pciide_bm = FALSE; 1987 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 1988 return; 1989 } 1990 1991 /* 1992 * check if it's a known bogus PCI-IDE chip 1993 */ 1994 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 1995 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 1996 ata_ctlp->ac_pciide = FALSE; 1997 ata_ctlp->ac_pciide_bm = FALSE; 1998 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 1999 return; 2000 } 2001 ata_ctlp->ac_pciide = TRUE; 2002 2003 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2004 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2005 } 2006 2007 /* 2008 * check for a PCI-IDE chip with a broken DMA engine 2009 */ 2010 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2011 ata_ctlp->ac_pciide_bm = FALSE; 2012 ata_cntrl_DMA_sel_msg = 2013 "cntrl blacklisted/DMA engine broken"; 2014 return; 2015 } 2016 2017 /* 2018 * Check the Programming Interface register to determine 2019 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2020 * devices don't support Bus Mastering or DMA. 2021 * Since we are dealing with pre-qualified pci-ide controller, 2022 * check programming interface byte only. 2023 */ 2024 2025 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2026 DDI_PROP_DONTPASS, "class-code", 0); 2027 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2028 ata_ctlp->ac_pciide_bm = FALSE; 2029 ata_cntrl_DMA_sel_msg = 2030 "cntrl not Bus Master DMA capable"; 2031 return; 2032 } 2033 2034 /* 2035 * Avoid doing DMA on "simplex" chips which share hardware 2036 * between channels 2037 */ 2038 status = ddi_get8(ata_ctlp->ac_bmhandle, 2039 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2040 /* 2041 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2042 * In such a mode, the simplex bit is asserted, but in fact testing 2043 * on such a motherboard has shown that the devices are not simplex 2044 * -- DMA can be used on both channels concurrently with no special 2045 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2046 * flag set to indicate that the value of the simplex bit can be 2047 * ignored. 2048 */ 2049 2050 if (status & PCIIDE_BMISX_SIMPLEX) { 2051 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2052 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2053 2054 } else { 2055 2056 int simplex_dma_channel, *rp, proplen, channel; 2057 int dma_on = FALSE; 2058 2059 /* 2060 * By default,use DMA on channel 0 and PIO on channel 2061 * 1. This can be switched by setting 2062 * ata-simplex-dma-channel to: 2063 * 0 DMA on channel 0 (default without this 2064 * property) 2065 * 1 DMA on channel 1 2066 * any other value: DMA off on both channels. 2067 */ 2068 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2069 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2070 2071 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2072 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2073 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2074 2075 channel = *rp; 2076 ddi_prop_free(rp); 2077 2078 if (simplex_dma_channel == channel) { 2079 cmn_err(CE_NOTE, "?ata: simplex " 2080 "controller. DMA on channel" 2081 " %d PIO on channel %d\n", 2082 channel, channel ? 0:1); 2083 dma_on = TRUE; 2084 } else { 2085 ata_cntrl_DMA_sel_msg = 2086 "simplex controller"; 2087 } 2088 } 2089 2090 if (dma_on == FALSE) { 2091 ata_ctlp->ac_pciide_bm = FALSE; 2092 2093 return; 2094 } 2095 } 2096 } 2097 2098 /* 2099 * It's a compatible PCI-IDE Bus Mastering controller, 2100 * allocate and map the DMA Scatter/Gather list (PRDE table). 2101 */ 2102 if (ata_pciide_alloc(dip, ata_ctlp)) 2103 ata_ctlp->ac_pciide_bm = TRUE; 2104 else { 2105 ata_ctlp->ac_pciide_bm = FALSE; 2106 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2107 } 2108 } 2109 2110 /* 2111 * 2112 * Determine whether to enable DMA support for this drive. 2113 * The controller and the drive both have to support DMA. 2114 * The controller's capabilities were already checked in 2115 * ata_init_pciide(), now just check the drive's capabilities. 2116 * 2117 */ 2118 2119 static int 2120 ata_init_drive_pcidma( 2121 ata_ctl_t *ata_ctlp, 2122 ata_drv_t *ata_drvp, 2123 dev_info_t *tdip) 2124 { 2125 boolean_t dma; 2126 boolean_t cd_dma; 2127 boolean_t disk_dma; 2128 boolean_t atapi_dma; 2129 int ata_options; 2130 2131 ata_dev_DMA_sel_msg = NULL; 2132 2133 if (ata_ctlp->ac_pciide_bm != TRUE) { 2134 ata_dev_DMA_sel_msg = 2135 "controller is not Bus Master capable"; 2136 2137 return (ATA_DMA_OFF); 2138 } 2139 2140 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2141 0, "ata-options", 0); 2142 2143 if (!(ata_options & ATA_OPTIONS_DMA)) { 2144 /* 2145 * Either the ata-options property was not found or 2146 * DMA is not enabled by this property 2147 */ 2148 ata_dev_DMA_sel_msg = 2149 "disabled by \"ata-options\" property"; 2150 2151 return (ATA_DMA_OFF); 2152 } 2153 2154 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2155 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2156 2157 return (ATA_DMA_OFF); 2158 } 2159 2160 /* 2161 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2162 * optional on ATA-2 (or older) drives. 2163 * 2164 * On ATA-2 drives the ai_majorversion word will probably 2165 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2166 * the capabilities word instead. The order of these tests 2167 * is important since an ATA-3 drive doesn't have to set 2168 * the DMA bit in the capabilities word. 2169 * 2170 */ 2171 2172 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2173 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2174 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2175 ata_dev_DMA_sel_msg = "device not DMA capable"; 2176 2177 return (ATA_DMA_OFF); 2178 } 2179 2180 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2181 0, "ata-dma-enabled", TRUE); 2182 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2183 0, "ata-disk-dma-enabled", TRUE); 2184 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2185 0, "atapi-cd-dma-enabled", FALSE); 2186 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2187 0, "atapi-other-dma-enabled", TRUE); 2188 2189 if (dma == FALSE) { 2190 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2191 "DMA disabled by \"ata-dma-enabled\" property"); 2192 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2193 2194 return (ATA_DMA_OFF); 2195 } 2196 2197 if (IS_CDROM(ata_drvp) == TRUE) { 2198 if (cd_dma == FALSE) { 2199 ata_dev_DMA_sel_msg = 2200 "disabled. Control with \"atapi-cd-dma-enabled\"" 2201 " property"; 2202 2203 return (ATA_DMA_OFF); 2204 } 2205 2206 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2207 if (disk_dma == FALSE) { 2208 ata_dev_DMA_sel_msg = 2209 "disabled by \"ata-disk-dma-enabled\" property"; 2210 2211 return (ATA_DMA_OFF); 2212 } 2213 2214 } else if (atapi_dma == FALSE) { 2215 ata_dev_DMA_sel_msg = 2216 "disabled by \"atapi-other-dma-enabled\" property"; 2217 2218 return (ATA_DMA_OFF); 2219 } 2220 2221 return (ATA_DMA_ON); 2222 } 2223 2224 2225 2226 /* 2227 * this compare routine squeezes out extra blanks and 2228 * returns TRUE if p1 matches the leftmost substring of p2 2229 */ 2230 2231 static int 2232 ata_strncmp( 2233 char *p1, 2234 char *p2, 2235 int cnt) 2236 { 2237 2238 for (;;) { 2239 /* 2240 * skip over any extra blanks in both strings 2241 */ 2242 while (*p1 != '\0' && *p1 == ' ') 2243 p1++; 2244 2245 while (cnt != 0 && *p2 == ' ') { 2246 p2++; 2247 cnt--; 2248 } 2249 2250 /* 2251 * compare the two strings 2252 */ 2253 2254 if (cnt == 0 || *p1 != *p2) 2255 break; 2256 2257 while (cnt > 0 && *p1 == *p2) { 2258 p1++; 2259 p2++; 2260 cnt--; 2261 } 2262 2263 } 2264 2265 /* return TRUE if both strings ended at same point */ 2266 return ((*p1 == '\0') ? TRUE : FALSE); 2267 } 2268 2269 /* 2270 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2271 * on the target's dev_info node. Currently, the sd target driver 2272 * is the only driver which refers to this property. 2273 * 2274 * If the flag ata_id_debug is set also create the 2275 * the "ata" or "atapi" property on the target's dev_info node 2276 * 2277 */ 2278 2279 int 2280 ata_prop_create( 2281 dev_info_t *tgt_dip, 2282 ata_drv_t *ata_drvp, 2283 char *name) 2284 { 2285 int rc; 2286 2287 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2288 2289 if (strcmp("atapi", name) == 0) { 2290 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2291 "variant", name); 2292 if (rc != DDI_PROP_SUCCESS) 2293 return (FALSE); 2294 } 2295 2296 if (!ata_id_debug) 2297 return (TRUE); 2298 2299 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2300 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2301 if (rc != DDI_PROP_SUCCESS) { 2302 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2303 } 2304 return (TRUE); 2305 } 2306 2307 2308 /* *********************************************************************** */ 2309 /* *********************************************************************** */ 2310 /* *********************************************************************** */ 2311 2312 /* 2313 * This state machine doesn't implement the ATAPI Optional Overlap 2314 * feature. You need that feature to efficiently support ATAPI 2315 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2316 * for an example of how to add the necessary additional NextActions 2317 * and NextStates to this FSM and the atapi_fsm, in order to support 2318 * the Overlap Feature. 2319 */ 2320 2321 2322 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2323 /* --------------------- next action --------------------- | - current - */ 2324 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2325 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2326 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2327 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2328 }; 2329 2330 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2331 2332 /* --------------------- next state --------------------- | - current - */ 2333 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2334 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2335 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2336 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2337 }; 2338 2339 2340 static int 2341 ata_ctlr_fsm( 2342 uchar_t fsm_func, 2343 ata_ctl_t *ata_ctlp, 2344 ata_drv_t *ata_drvp, 2345 ata_pkt_t *ata_pktp, 2346 int *DoneFlgp) 2347 { 2348 uchar_t action; 2349 uchar_t current_state; 2350 uchar_t next_state; 2351 int rc; 2352 2353 current_state = ata_ctlp->ac_state; 2354 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2355 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2356 2357 /* 2358 * Set the controller's new state 2359 */ 2360 ata_ctlp->ac_state = next_state; 2361 switch (action) { 2362 2363 case AC_BUSY: 2364 return (ATA_FSM_RC_BUSY); 2365 2366 case AC_NADA: 2367 return (ATA_FSM_RC_OKAY); 2368 2369 case AC_START: 2370 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2371 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2372 2373 ata_ctlp->ac_active_pktp = ata_pktp; 2374 ata_ctlp->ac_active_drvp = ata_drvp; 2375 2376 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2377 2378 if (rc == ATA_FSM_RC_BUSY) { 2379 /* the request didn't start, GHD will requeue it */ 2380 ata_ctlp->ac_state = AS_IDLE; 2381 ata_ctlp->ac_active_pktp = NULL; 2382 ata_ctlp->ac_active_drvp = NULL; 2383 } 2384 return (rc); 2385 2386 case AC_INTR: 2387 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2388 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2389 2390 ata_drvp = ata_ctlp->ac_active_drvp; 2391 ata_pktp = ata_ctlp->ac_active_pktp; 2392 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2393 2394 case AC_RESET_A: /* Reset, controller active */ 2395 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2396 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2397 2398 /* clean up the active request */ 2399 ata_pktp = ata_ctlp->ac_active_pktp; 2400 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2401 2402 /* halt the DMA engine */ 2403 if (ata_pktp->ap_pciide_dma) { 2404 ata_pciide_dma_stop(ata_ctlp); 2405 (void) ata_pciide_status_clear(ata_ctlp); 2406 } 2407 2408 /* Do a Software Reset to unwedge the bus */ 2409 if (!ata_software_reset(ata_ctlp)) { 2410 return (ATA_FSM_RC_BUSY); 2411 } 2412 2413 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2414 atapi_fsm_reset(ata_ctlp); 2415 return (ATA_FSM_RC_FINI); 2416 2417 case AC_RESET_I: /* Reset, controller idle */ 2418 /* Do a Software Reset to unwedge the bus */ 2419 if (!ata_software_reset(ata_ctlp)) { 2420 return (ATA_FSM_RC_BUSY); 2421 } 2422 2423 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2424 atapi_fsm_reset(ata_ctlp); 2425 return (ATA_FSM_RC_OKAY); 2426 2427 case AC_FINI: 2428 break; 2429 } 2430 2431 /* 2432 * AC_FINI, check ARQ needs to be started or finished 2433 */ 2434 2435 ASSERT(action == AC_FINI); 2436 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2437 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2438 2439 /* 2440 * The active request is done now. 2441 * Disconnect the request from the controller and 2442 * add it to the done queue. 2443 */ 2444 ata_drvp = ata_ctlp->ac_active_drvp; 2445 ata_pktp = ata_ctlp->ac_active_pktp; 2446 2447 /* 2448 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2449 */ 2450 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2451 ata_pkt_t *arq_pktp; 2452 2453 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2454 2455 arq_pktp = ata_pktp; 2456 ata_pktp = ata_ctlp->ac_fault_pktp; 2457 ata_ctlp->ac_fault_pktp = NULL; 2458 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2459 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2460 else 2461 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2462 goto all_done; 2463 } 2464 2465 2466 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2467 2468 /* 2469 * Start ARQ pkt if necessary 2470 */ 2471 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2472 (ata_pktp->ap_status & ATS_ERR)) { 2473 2474 /* set controller state back to active */ 2475 ata_ctlp->ac_state = current_state; 2476 2477 /* try to start the ARQ pkt */ 2478 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2479 2480 if (rc == ATA_FSM_RC_BUSY) { 2481 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2482 /* let the target driver handle the problem */ 2483 ata_ctlp->ac_state = AS_IDLE; 2484 ata_ctlp->ac_active_pktp = NULL; 2485 ata_ctlp->ac_active_drvp = NULL; 2486 ata_ctlp->ac_fault_pktp = NULL; 2487 goto all_done; 2488 } 2489 2490 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2491 return (rc); 2492 } 2493 2494 /* 2495 * Normal completion, no error status, and not an ARQ pkt, 2496 * just fall through. 2497 */ 2498 2499 all_done: 2500 2501 /* 2502 * wrap everything up and tie a ribbon around it 2503 */ 2504 ata_ctlp->ac_active_pktp = NULL; 2505 ata_ctlp->ac_active_drvp = NULL; 2506 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2507 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2508 if (DoneFlgp) 2509 *DoneFlgp = TRUE; 2510 } 2511 2512 return (ATA_FSM_RC_OKAY); 2513 } 2514 2515 2516 static int 2517 ata_start_arq( 2518 ata_ctl_t *ata_ctlp, 2519 ata_drv_t *ata_drvp, 2520 ata_pkt_t *ata_pktp) 2521 { 2522 ata_pkt_t *arq_pktp; 2523 int bytes; 2524 uint_t senselen; 2525 2526 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2527 2528 /* 2529 * Determine just the size of the Request Sense Data buffer within 2530 * the scsi_arq_status structure. 2531 */ 2532 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2533 - sizeof (struct scsi_extended_sense)) 2534 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2535 ASSERT(senselen > 0); 2536 2537 2538 /* save ptr to original pkt */ 2539 ata_ctlp->ac_fault_pktp = ata_pktp; 2540 2541 /* switch the controller's active pkt to the ARQ pkt */ 2542 arq_pktp = ata_ctlp->ac_arq_pktp; 2543 ata_ctlp->ac_active_pktp = arq_pktp; 2544 2545 /* finish initializing the ARQ CDB */ 2546 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2547 ata_ctlp->ac_arq_cdb[4] = senselen; 2548 2549 /* finish initializing the ARQ pkt */ 2550 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2551 2552 arq_pktp->ap_resid = senselen; 2553 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2554 arq_pktp->ap_cdb_pad = 2555 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2556 2557 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2558 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2559 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2560 2561 /* 2562 * This packet is shared by all drives on this controller 2563 * therefore we need to init the drive number on every ARQ. 2564 */ 2565 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2566 2567 /* start it up */ 2568 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2569 } 2570 2571 /* 2572 * 2573 * reset the bus 2574 * 2575 */ 2576 2577 static int 2578 ata_reset_bus( 2579 ata_ctl_t *ata_ctlp) 2580 { 2581 int watchdog; 2582 uchar_t drive; 2583 int rc = FALSE; 2584 uchar_t fsm_func; 2585 int DoneFlg = FALSE; 2586 2587 /* 2588 * Do a Software Reset to unwedge the bus, and send 2589 * ATAPI DEVICE RESET to each ATAPI drive. 2590 */ 2591 fsm_func = ATA_FSM_RESET; 2592 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2593 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2594 &DoneFlg)) { 2595 case ATA_FSM_RC_OKAY: 2596 rc = TRUE; 2597 goto fsm_done; 2598 2599 case ATA_FSM_RC_BUSY: 2600 return (FALSE); 2601 2602 case ATA_FSM_RC_INTR: 2603 fsm_func = ATA_FSM_INTR; 2604 rc = TRUE; 2605 continue; 2606 2607 case ATA_FSM_RC_FINI: 2608 fsm_func = ATA_FSM_FINI; 2609 rc = TRUE; 2610 continue; 2611 } 2612 } 2613 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2614 2615 fsm_done: 2616 2617 /* 2618 * Reinitialize the ATA drives 2619 */ 2620 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2621 ata_drv_t *ata_drvp; 2622 2623 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2624 continue; 2625 2626 if (ATAPIDRV(ata_drvp)) 2627 continue; 2628 2629 /* 2630 * Reprogram the Read/Write Multiple block factor 2631 * and current geometry into the drive. 2632 */ 2633 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2634 rc = FALSE; 2635 } 2636 2637 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2638 /* has been already called. In this case ignore any errors and */ 2639 /* return TRUE to the caller, otherwise return the value of rc */ 2640 /* to the caller */ 2641 if (DoneFlg) 2642 return (TRUE); 2643 else 2644 return (rc); 2645 } 2646 2647 2648 /* 2649 * 2650 * Low level routine to toggle the Software Reset bit 2651 * 2652 */ 2653 2654 static int 2655 ata_software_reset( 2656 ata_ctl_t *ata_ctlp) 2657 { 2658 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2659 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2660 hrtime_t deadline; 2661 uint_t usecs_left; 2662 2663 ADBG_TRACE(("ata_reset_bus entered\n")); 2664 2665 /* disable interrupts and turn the software reset bit on */ 2666 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2667 2668 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2669 drv_usecwait(30000); 2670 2671 /* turn the software reset bit back off */ 2672 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2673 2674 /* 2675 * Wait for the controller to assert BUSY status. 2676 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2677 * spec says 400 nsecs, (and 2 msecs if device 2678 * was in sleep mode; but we don't put drives to sleep 2679 * so it probably doesn't matter). 2680 */ 2681 drv_usecwait(300000); 2682 2683 /* 2684 * If drive 0 exists the test for completion is simple 2685 */ 2686 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2687 2688 if (CTL2DRV(ata_ctlp, 0, 0)) { 2689 goto wait_for_not_busy; 2690 } 2691 2692 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2693 2694 /* 2695 * This must be a single device configuration, with drive 1 2696 * only. This complicates the test for completion because 2697 * issuing the software reset just caused drive 1 to 2698 * deselect. With drive 1 deselected, if I just read the 2699 * status register to test the BSY bit I get garbage, but 2700 * I can't re-select drive 1 until I'm certain the BSY bit 2701 * is de-asserted. Catch-22. 2702 * 2703 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2704 * this situation like this: 2705 */ 2706 2707 /* give up if the drive doesn't settle within 31 seconds */ 2708 while (gethrtime() < deadline) { 2709 /* 2710 * delay 10msec each time around the loop 2711 */ 2712 drv_usecwait(10000); 2713 2714 /* 2715 * try to select drive 1 2716 */ 2717 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2718 2719 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2720 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2721 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2722 continue; 2723 2724 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2725 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2726 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2727 continue; 2728 2729 goto wait_for_not_busy; 2730 } 2731 return (FALSE); 2732 2733 wait_for_not_busy: 2734 2735 /* 2736 * Now wait up to 31 seconds for BUSY to clear. 2737 */ 2738 usecs_left = (deadline - gethrtime()) / 1000; 2739 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2740 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2741 2742 return (TRUE); 2743 } 2744 2745 /* 2746 * 2747 * DDI interrupt handler 2748 * 2749 */ 2750 2751 static uint_t 2752 ata_intr( 2753 caddr_t arg) 2754 { 2755 ata_ctl_t *ata_ctlp; 2756 int one_shot = 1; 2757 2758 ata_ctlp = (ata_ctl_t *)arg; 2759 2760 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2761 } 2762 2763 2764 /* 2765 * 2766 * GHD ccc_get_status callback 2767 * 2768 */ 2769 2770 static int 2771 ata_get_status( 2772 void *hba_handle, 2773 void *intr_status) 2774 { 2775 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2776 uchar_t status; 2777 2778 ADBG_TRACE(("ata_get_status entered\n")); 2779 2780 /* 2781 * ignore interrupts before ata_attach completes 2782 */ 2783 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2784 return (FALSE); 2785 2786 /* 2787 * can't be interrupt pending if nothing active 2788 */ 2789 switch (ata_ctlp->ac_state) { 2790 case AS_IDLE: 2791 return (FALSE); 2792 case AS_ACTIVE0: 2793 case AS_ACTIVE1: 2794 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2795 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2796 break; 2797 } 2798 2799 /* 2800 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2801 * interrupt status latch. But don't clear it yet. 2802 * 2803 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2804 * CMD chips with device id 0x646. Since the interrupt bit on 2805 * Bus master IDE register is not usable when in PIO mode, 2806 * this chip is treated as a legacy device for interrupt 2807 * indication. The following code for CMD 2808 * chips may need to be revisited when we enable support for dma. 2809 * 2810 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2811 * checked only if there was DMA used or BM intr is useable on PIO, 2812 * else treat it as before - as legacy device. 2813 */ 2814 2815 if ((ata_ctlp->ac_pciide) && 2816 ((ata_ctlp->ac_pciide_bm != FALSE) && 2817 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2818 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2819 2820 if (!ata_pciide_status_pending(ata_ctlp)) 2821 return (FALSE); 2822 } else { 2823 /* 2824 * Interrupts from legacy ATA/IDE controllers are 2825 * edge-triggered but the dumb legacy ATA/IDE controllers 2826 * and drives don't have an interrupt status bit. 2827 * 2828 * Use a one_shot variable to make sure we only return 2829 * one status per interrupt. 2830 */ 2831 if (intr_status != NULL) { 2832 int *one_shot = (int *)intr_status; 2833 2834 if (*one_shot == 1) 2835 *one_shot = 0; 2836 else 2837 return (FALSE); 2838 } 2839 } 2840 2841 /* check if device is still busy */ 2842 2843 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2844 if (status & ATS_BSY) 2845 return (FALSE); 2846 return (TRUE); 2847 } 2848 2849 2850 /* 2851 * 2852 * get the current status and clear the IRQ 2853 * 2854 */ 2855 2856 int 2857 ata_get_status_clear_intr( 2858 ata_ctl_t *ata_ctlp, 2859 ata_pkt_t *ata_pktp) 2860 { 2861 uchar_t status; 2862 2863 /* 2864 * Here's where we clear the PCI-IDE interrupt latch. If this 2865 * request used DMA mode then we also have to check and clear 2866 * the DMA error latch at the same time. 2867 */ 2868 2869 if (ata_pktp->ap_pciide_dma) { 2870 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2871 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2872 } else if ((ata_ctlp->ac_pciide) && 2873 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2874 /* 2875 * Some requests don't use DMA mode and therefore won't 2876 * set the DMA error latch, but we still have to clear 2877 * the interrupt latch. 2878 * Controllers with broken BM intr in PIO mode do not go 2879 * through this path. 2880 */ 2881 (void) ata_pciide_status_clear(ata_ctlp); 2882 } 2883 2884 /* 2885 * this clears the drive's interrupt 2886 */ 2887 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2888 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2889 return (status); 2890 } 2891 2892 2893 2894 /* 2895 * 2896 * GHD interrupt handler 2897 * 2898 */ 2899 2900 /* ARGSUSED */ 2901 static void 2902 ata_process_intr( 2903 void *hba_handle, 2904 void *intr_status) 2905 { 2906 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2907 int watchdog; 2908 uchar_t fsm_func; 2909 int rc; 2910 2911 ADBG_TRACE(("ata_process_intr entered\n")); 2912 2913 /* 2914 * process the ATA or ATAPI interrupt 2915 */ 2916 2917 fsm_func = ATA_FSM_INTR; 2918 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2919 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2920 2921 switch (rc) { 2922 case ATA_FSM_RC_OKAY: 2923 return; 2924 2925 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2926 return; 2927 2928 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2929 fsm_func = ATA_FSM_INTR; 2930 break; 2931 2932 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2933 fsm_func = ATA_FSM_FINI; 2934 break; 2935 } 2936 } 2937 ADBG_WARN(("ata_process_intr: watchdog\n")); 2938 } 2939 2940 2941 2942 /* 2943 * 2944 * GHD ccc_hba_start callback 2945 * 2946 */ 2947 2948 static int 2949 ata_hba_start( 2950 void *hba_handle, 2951 gcmd_t *gcmdp) 2952 { 2953 ata_ctl_t *ata_ctlp; 2954 ata_drv_t *ata_drvp; 2955 ata_pkt_t *ata_pktp; 2956 uchar_t fsm_func; 2957 int request_started; 2958 int watchdog; 2959 2960 ADBG_TRACE(("ata_hba_start entered\n")); 2961 2962 ata_ctlp = (ata_ctl_t *)hba_handle; 2963 2964 if (ata_ctlp->ac_active_drvp != NULL) { 2965 ADBG_WARN(("ata_hba_start drvp not null\n")); 2966 return (FALSE); 2967 } 2968 if (ata_ctlp->ac_active_pktp != NULL) { 2969 ADBG_WARN(("ata_hba_start pktp not null\n")); 2970 return (FALSE); 2971 } 2972 2973 ata_pktp = GCMD2APKT(gcmdp); 2974 ata_drvp = GCMD2DRV(gcmdp); 2975 2976 /* 2977 * which drive? 2978 */ 2979 if (ata_drvp->ad_targ == 0) 2980 fsm_func = ATA_FSM_START0; 2981 else 2982 fsm_func = ATA_FSM_START1; 2983 2984 /* 2985 * start the request 2986 */ 2987 request_started = FALSE; 2988 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 2989 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 2990 NULL)) { 2991 case ATA_FSM_RC_OKAY: 2992 request_started = TRUE; 2993 goto fsm_done; 2994 2995 case ATA_FSM_RC_BUSY: 2996 /* if first time, tell GHD to requeue the request */ 2997 goto fsm_done; 2998 2999 case ATA_FSM_RC_INTR: 3000 /* 3001 * The start function polled for the next 3002 * bus phase, now fake an interrupt to process 3003 * the next action. 3004 */ 3005 request_started = TRUE; 3006 fsm_func = ATA_FSM_INTR; 3007 ata_drvp = NULL; 3008 ata_pktp = NULL; 3009 break; 3010 3011 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3012 request_started = TRUE; 3013 fsm_func = ATA_FSM_FINI; 3014 ata_drvp = NULL; 3015 ata_pktp = NULL; 3016 break; 3017 } 3018 } 3019 ADBG_WARN(("ata_hba_start: watchdog\n")); 3020 3021 fsm_done: 3022 return (request_started); 3023 3024 } 3025 3026 static int 3027 ata_check_pciide_blacklist( 3028 dev_info_t *dip, 3029 uint_t flags) 3030 { 3031 ushort_t vendorid; 3032 ushort_t deviceid; 3033 pcibl_t *blp; 3034 int *propp; 3035 uint_t count; 3036 int rc; 3037 3038 3039 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3040 DDI_PROP_DONTPASS, "vendor-id", 0); 3041 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3042 DDI_PROP_DONTPASS, "device-id", 0); 3043 3044 /* 3045 * first check for a match in the "pci-ide-blacklist" property 3046 */ 3047 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3048 "pci-ide-blacklist", &propp, &count); 3049 3050 if (rc == DDI_PROP_SUCCESS) { 3051 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3052 blp = (pcibl_t *)propp; 3053 while (count--) { 3054 /* check for matching ID */ 3055 if ((vendorid & blp->b_vmask) 3056 != (blp->b_vendorid & blp->b_vmask)) { 3057 blp++; 3058 continue; 3059 } 3060 if ((deviceid & blp->b_dmask) 3061 != (blp->b_deviceid & blp->b_dmask)) { 3062 blp++; 3063 continue; 3064 } 3065 3066 /* got a match */ 3067 if (blp->b_flags & flags) { 3068 ddi_prop_free(propp); 3069 return (TRUE); 3070 } else { 3071 ddi_prop_free(propp); 3072 return (FALSE); 3073 } 3074 } 3075 ddi_prop_free(propp); 3076 } 3077 3078 /* 3079 * then check the built-in blacklist 3080 */ 3081 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3082 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3083 continue; 3084 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3085 continue; 3086 if (!(blp->b_flags & flags)) 3087 continue; 3088 return (TRUE); 3089 } 3090 return (FALSE); 3091 } 3092 3093 int 3094 ata_check_drive_blacklist( 3095 struct ata_id *aidp, 3096 uint_t flags) 3097 { 3098 atabl_t *blp; 3099 3100 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3101 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3102 sizeof (aidp->ai_model))) 3103 continue; 3104 if (blp->b_flags & flags) 3105 return (TRUE); 3106 return (FALSE); 3107 } 3108 return (FALSE); 3109 } 3110 3111 /* 3112 * Queue a request to perform some sort of internally 3113 * generated command. When this request packet reaches 3114 * the front of the queue (*func)() is invoked. 3115 * 3116 */ 3117 3118 int 3119 ata_queue_cmd( 3120 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3121 void *arg, 3122 ata_ctl_t *ata_ctlp, 3123 ata_drv_t *ata_drvp, 3124 gtgt_t *gtgtp) 3125 { 3126 ata_pkt_t *ata_pktp; 3127 gcmd_t *gcmdp; 3128 int rc; 3129 3130 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3131 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3132 return (FALSE); 3133 } 3134 3135 3136 /* set the back ptr from the ata_pkt to the gcmd_t */ 3137 ata_pktp = GCMD2APKT(gcmdp); 3138 ata_pktp->ap_gcmdp = gcmdp; 3139 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3140 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3141 3142 /* 3143 * over-ride the default start function 3144 */ 3145 ata_pktp = GCMD2APKT(gcmdp); 3146 ata_pktp->ap_start = func; 3147 ata_pktp->ap_complete = NULL; 3148 ata_pktp->ap_v_addr = (caddr_t)arg; 3149 3150 /* 3151 * add it to the queue, when it gets to the front the 3152 * ap_start function is called. 3153 */ 3154 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3155 0, TRUE, NULL); 3156 3157 if (rc != TRAN_ACCEPT) { 3158 /* this should never, ever happen */ 3159 return (FALSE); 3160 } 3161 3162 if (ata_pktp->ap_flags & AP_ERROR) 3163 return (FALSE); 3164 return (TRUE); 3165 } 3166 3167 /* 3168 * Check if this drive has the "revert to defaults" bug 3169 * PSARC 2001/500 and 2001/xxx - check for the properties 3170 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3171 * examining the blacklist. 3172 * <diskmodel> is made from the model number reported by Identify Drive 3173 * with uppercase letters converted to lowercase and all characters 3174 * except letters, digits, ".", "_", and "-" deleted. 3175 * Return value: 3176 * TRUE: enable revert to defaults 3177 * FALSE: disable revert to defaults 3178 * 3179 * NOTE: revert to power on defaults that includes reverting to MDMA 3180 * mode is allowed by ATA-6 & ATA-7 specs. 3181 * Therefore drives exhibiting this behaviour are not violating the spec. 3182 * Furthermore, the spec explicitly says that after the soft reset 3183 * host should check the current setting of the device features. 3184 * Correctly working BIOS would therefore reprogram either the drive 3185 * and/or the host controller to match transfer modes. 3186 * Devices with ATA_BL_NORVRT flag will be removed from 3187 * the ata_blacklist. 3188 * The default behaviour will be - no revert to power-on defaults 3189 * for all devices. The property is retained in case the user 3190 * explicitly requests revert-to-defaults before reboot. 3191 */ 3192 3193 #define ATA_REVERT_PROP_PREFIX "revert-" 3194 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3195 /* room for prefix + model number + terminating NUL character */ 3196 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3197 sizeof (aidp->ai_model) + 1) 3198 #define PROP_LEN_MAX (31) 3199 3200 static int 3201 ata_check_revert_to_defaults( 3202 ata_drv_t *ata_drvp) 3203 { 3204 struct ata_id *aidp = &ata_drvp->ad_id; 3205 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3206 char prop_buf[PROP_BUF_SIZE]; 3207 int i, j; 3208 int propval; 3209 3210 /* put prefix into the buffer */ 3211 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3212 j = strlen(prop_buf); 3213 3214 /* append the model number, leaving out invalid characters */ 3215 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3216 char c = aidp->ai_model[i]; 3217 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3218 c = c - 'A' + 'a'; 3219 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3220 c == '.' || c == '_' || c == '-') 3221 prop_buf[j++] = c; 3222 if (c == '\0') 3223 break; 3224 } 3225 3226 /* make sure there's a terminating NUL character */ 3227 if (j >= PROP_LEN_MAX) 3228 j = PROP_LEN_MAX; 3229 prop_buf[j] = '\0'; 3230 3231 /* look for a disk-specific "revert" property" */ 3232 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3233 DDI_PROP_DONTPASS, prop_buf, -1); 3234 if (propval == 0) 3235 return (FALSE); 3236 else if (propval != -1) 3237 return (TRUE); 3238 3239 /* look for a global "revert" property" */ 3240 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3241 0, ATA_REVERT_PROP_GLOBAL, -1); 3242 if (propval == 0) 3243 return (FALSE); 3244 else if (propval != -1) 3245 return (TRUE); 3246 3247 return (FALSE); 3248 } 3249 3250 void 3251 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3252 { 3253 int i; 3254 3255 if (ata_ctlp->ac_pciide_bm == FALSE || 3256 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3257 if (ata_cntrl_DMA_sel_msg) { 3258 ATAPRT(( 3259 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3260 } else if (ata_dev_DMA_sel_msg) { 3261 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3262 } 3263 ATAPRT(("?\tPIO mode %d selected\n", 3264 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3265 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3266 } else { 3267 /* Using DMA */ 3268 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3269 /* 3270 * Rely on the fact that either dwdma or udma is 3271 * selected, not both. 3272 */ 3273 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3274 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3275 ATAC_MDMA_2_SEL ? 2 : 3276 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3277 ATAC_MDMA_1_SEL ? 1 : 0)); 3278 } else { 3279 for (i = 0; i <= 6; i++) { 3280 if (ata_drvp->ad_id.ai_ultradma & 3281 (1 << (i + 8))) { 3282 ATAPRT(( 3283 "?\tUltraDMA mode %d selected\n", 3284 i)); 3285 break; 3286 } 3287 } 3288 } 3289 } 3290 } 3291 3292 /* 3293 * Controller-specific operation pointers. 3294 * Should be extended as needed - init only for now 3295 */ 3296 struct ata_ctl_spec_ops { 3297 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3298 }; 3299 3300 3301 struct ata_ctl_spec { 3302 ushort_t cs_vendor_id; 3303 ushort_t cs_device_id; 3304 struct ata_ctl_spec_ops *cs_ops; 3305 }; 3306 3307 /* Sil3XXX-specific functions (init only for now) */ 3308 struct ata_ctl_spec_ops sil3xxx_ops = { 3309 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3310 }; 3311 3312 3313 struct ata_ctl_spec ata_cntrls_spec[] = { 3314 {0x1095, 0x3114, &sil3xxx_ops}, 3315 {0x1095, 0x3512, &sil3xxx_ops}, 3316 {0x1095, 0x3112, &sil3xxx_ops}, 3317 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3318 }; 3319 3320 /* 3321 * Do controller specific initialization if necessary. 3322 * Pick-up controller specific functions. 3323 */ 3324 3325 int 3326 ata_spec_init_controller(dev_info_t *dip) 3327 { 3328 ushort_t vendor_id; 3329 ushort_t device_id; 3330 struct ata_ctl_spec *ctlsp; 3331 3332 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3333 DDI_PROP_DONTPASS, "vendor-id", 0); 3334 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3335 DDI_PROP_DONTPASS, "device-id", 0); 3336 3337 /* Locate controller specific ops, if they exist */ 3338 ctlsp = ata_cntrls_spec; 3339 while (ctlsp->cs_ops != NULL) { 3340 if (ctlsp->cs_vendor_id == vendor_id && 3341 ctlsp->cs_device_id == device_id) 3342 break; 3343 ctlsp++; 3344 } 3345 3346 if (ctlsp->cs_ops != NULL) { 3347 if (ctlsp->cs_ops->cs_init != NULL) { 3348 /* Initialize controller */ 3349 if ((*(ctlsp->cs_ops->cs_init)) 3350 (dip, vendor_id, device_id) != TRUE) { 3351 cmn_err(CE_WARN, 3352 "pci%4x,%4x cntrl specific " 3353 "initialization failed", 3354 vendor_id, device_id); 3355 return (FALSE); 3356 } 3357 } 3358 } 3359 return (TRUE); 3360 } 3361 3362 /* 3363 * this routine works like ddi_prop_get_int, except that it works on 3364 * a string property that contains ascii representations 3365 * of an integer. 3366 * If the property is not found, the default value is returned. 3367 */ 3368 static int 3369 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3370 uint_t flags, char *name, int defvalue) 3371 { 3372 3373 char *bufp, *cp; 3374 int rc = defvalue; 3375 int proprc; 3376 3377 proprc = ddi_prop_lookup_string(match_dev, dip, 3378 flags, name, &bufp); 3379 3380 if (proprc == DDI_PROP_SUCCESS) { 3381 cp = bufp; 3382 rc = stoi(&cp); 3383 ddi_prop_free(bufp); 3384 } else { 3385 /* 3386 * see if property is encoded as an int instead of string. 3387 */ 3388 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3389 } 3390 3391 return (rc); 3392 } 3393