1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 #include <sys/systm.h> 29 #include <sys/conf.h> 30 #include <sys/modctl.h> 31 #include <sys/file.h> 32 #include <sys/stat.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/modctl.h> 36 #include <sys/sunldi.h> 37 #include <sys/pci.h> 38 #include <sys/agpgart.h> 39 #include <sys/agp/agpdefs.h> 40 #include <sys/agp/agptarget_io.h> 41 42 int agptarget_debug_var = 0; 43 #define TARGETDB_PRINT2(fmt) if (agptarget_debug_var >= 1) cmn_err fmt 44 #define INST2NODENUM(inst) (inst) 45 #define DEV2INST(dev) (getminor(dev)) 46 47 typedef struct agp_target_softstate { 48 dev_info_t *tsoft_dip; 49 ddi_acc_handle_t tsoft_pcihdl; 50 uint32_t tsoft_devid; 51 /* The offset of the ACAPID register */ 52 off_t tsoft_acaptr; 53 kmutex_t tsoft_lock; 54 int tsoft_gms_off; /* GMS offset in config */ 55 uint32_t tsoft_gms; 56 }agp_target_softstate_t; 57 58 /* 59 * To get the pre-allocated graphics mem size using Graphics Mode Select 60 * (GMS) value. 61 */ 62 typedef struct gms_mode { 63 uint32_t gm_devid; /* bridge vendor + device id */ 64 off_t gm_regoff; /* mode selection register offset */ 65 uint32_t gm_mask; /* GMS mask */ 66 uint32_t gm_num; /* number of modes in gm_vec */ 67 int *gm_vec; /* modes array */ 68 } gms_mode_t; 69 70 static void *agptarget_glob_soft_handle; 71 72 #define GETSOFTC(instance) ((agp_target_softstate_t *) \ 73 ddi_get_soft_state(agptarget_glob_soft_handle, instance)); 74 75 /* 76 * The AMD8151 bridge is the only supported 64 bit hardware 77 */ 78 static int 79 is_64bit_aper(agp_target_softstate_t *softstate) 80 { 81 return (softstate->tsoft_devid == AMD_BR_8151); 82 } 83 84 /* 85 * Check if it is an intel bridge 86 */ 87 static int 88 is_intel_br(agp_target_softstate_t *softstate) 89 { 90 return ((softstate->tsoft_devid & VENDOR_ID_MASK) == 91 INTEL_VENDOR_ID); 92 } 93 94 /* 95 * agp_target_cap_find() 96 * 97 * Description: 98 * This function searches the linked capability list to find the offset 99 * of the AGP capability register. When it was not found, return 0. 100 * This works for standard AGP chipsets, but not for some Intel chipsets, 101 * like the I830M/I830MP/I852PM/I852GME/I855GME. It will return 0 for 102 * these chipsets even if AGP is supported. So the offset of acapid 103 * should be set manually in thoses cases. 104 * 105 * Arguments: 106 * pci_handle ddi acc handle of pci config 107 * 108 * Returns: 109 * 0 No capability pointer register found 110 * nexcap The AGP capability pointer register offset 111 */ 112 static off_t 113 agp_target_cap_find(ddi_acc_handle_t pci_handle) 114 { 115 off_t nextcap = 0; 116 uint32_t ncapid = 0; 117 uint8_t value = 0; 118 119 /* Check if this device supports the capability pointer */ 120 value = (uint8_t)(pci_config_get16(pci_handle, PCI_CONF_STAT) 121 & PCI_CONF_CAP_MASK); 122 123 if (!value) 124 return (0); 125 /* Get the offset of the first capability pointer from CAPPTR */ 126 nextcap = (off_t)(pci_config_get8(pci_handle, AGP_CONF_CAPPTR)); 127 128 /* Check the AGP capability from the first capability pointer */ 129 while (nextcap) { 130 ncapid = pci_config_get32(pci_handle, nextcap); 131 /* 132 * AGP3.0 rev1.0 127 the capid was assigned by the PCI SIG, 133 * 845 data sheet page 69 134 */ 135 if ((ncapid & PCI_CONF_CAPID_MASK) == 136 AGP_CAP_ID) /* The AGP cap was found */ 137 break; 138 139 nextcap = (off_t)((ncapid & PCI_CONF_NCAPID_MASK) >> 8); 140 } 141 142 return (nextcap); 143 144 } 145 146 /* 147 * agp_target_get_aperbase() 148 * 149 * Description: 150 * This function gets the AGP aperture base address from the AGP target 151 * register, the AGP aperture base register was programmed by the BIOS. 152 * 153 * Arguments: 154 * softstate driver soft state pointer 155 * 156 * Returns: 157 * aper_base AGP aperture base address 158 * 159 * Notes: 160 * If a 64bit bridge device is available, the AGP aperture base address 161 * can be 64 bit. 162 */ 163 static uint64_t 164 agp_target_get_apbase(agp_target_softstate_t *softstate) 165 { 166 uint64_t aper_base; 167 168 if (is_intel_br(softstate)) { 169 aper_base = pci_config_get32(softstate->tsoft_pcihdl, 170 AGP_CONF_APERBASE) & AGP_32_APERBASE_MASK; 171 } else if (is_64bit_aper(softstate)) { 172 aper_base = pci_config_get64(softstate->tsoft_pcihdl, 173 AGP_CONF_APERBASE); 174 /* 32-bit or 64-bit aperbase base pointer */ 175 if ((aper_base & AGP_APER_TYPE_MASK) == 0) 176 aper_base &= AGP_32_APERBASE_MASK; 177 else 178 aper_base &= AGP_64_APERBASE_MASK; 179 } 180 181 return (aper_base); 182 } 183 184 /* 185 * agp_target_get_apsize() 186 * 187 * Description: 188 * This function gets the AGP aperture size by reading the AGP aperture 189 * size register. 190 * Arguments: 191 * softstate driver soft state pointer 192 * 193 * Return: 194 * size The AGP aperture size in megabytes 195 * 0 an unexpected error 196 */ 197 static size_t 198 agp_target_get_apsize(agp_target_softstate_t *softstate) 199 { 200 off_t cap; 201 uint16_t value; 202 size_t size, regsize; 203 204 ASSERT(softstate->tsoft_acaptr); 205 cap = softstate->tsoft_acaptr; 206 207 if (is_intel_br(softstate)) { 208 /* extend this value to 16 bit for later tests */ 209 value = (uint16_t)pci_config_get8(softstate->tsoft_pcihdl, 210 cap + AGP_CONF_APERSIZE) | AGP_APER_SIZE_MASK; 211 } else if (is_64bit_aper(softstate)) { 212 value = pci_config_get16(softstate->tsoft_pcihdl, 213 cap + AGP_CONF_APERSIZE); 214 } 215 216 if (value & AGP_APER_128M_MASK) { 217 switch (value & AGP_APER_128M_MASK) { 218 case AGP_APER_4M: 219 size = 4; /* 4M */ 220 break; 221 case AGP_APER_8M: 222 size = 8; /* 8M */ 223 break; 224 case AGP_APER_16M: 225 size = 16; /* 16M */ 226 break; 227 case AGP_APER_32M: 228 size = 32; /* 32M */ 229 break; 230 case AGP_APER_64M: 231 size = 64; /* 64M */ 232 break; 233 case AGP_APER_128M: 234 size = 128; /* 128M */ 235 break; 236 default: 237 size = 0; /* not true */ 238 } 239 } else { 240 switch (value & AGP_APER_4G_MASK) { 241 case AGP_APER_256M: 242 size = 256; /* 256 M */ 243 break; 244 case AGP_APER_512M: 245 size = 512; /* 512 M */ 246 break; 247 case AGP_APER_1024M: 248 size = 1024; /* 1024 M */ 249 break; 250 case AGP_APER_2048M: 251 size = 2048; /* 2048 M */ 252 break; 253 case AGP_APER_4G: 254 size = 4096; /* 4096 M */ 255 break; 256 default: 257 size = 0; /* not true */ 258 } 259 } 260 /* 261 * In some cases, there is no APSIZE register, so the size value 262 * of 256M could be wrong. Check the value by reading the size of 263 * the first register which was set in the PCI configuration space. 264 */ 265 if (size == 256) { 266 if (ddi_dev_regsize(softstate->tsoft_dip, 267 AGP_TARGET_BAR1, (off_t *)®size) == DDI_FAILURE) 268 return (0); 269 270 if (MB2BYTES(size) != regsize) { 271 TARGETDB_PRINT2((CE_WARN, 272 "APSIZE 256M doesn't match regsize %lx", 273 regsize)); 274 TARGETDB_PRINT2((CE_WARN, "Use regsize instead")); 275 size = BYTES2MB(regsize); 276 } 277 } 278 279 return (size); 280 } 281 282 static void 283 agp_target_set_gartaddr(agp_target_softstate_t *softstate, uint32_t gartaddr) 284 { 285 ASSERT(softstate->tsoft_acaptr); 286 287 /* Disable the GTLB for Intel chipsets */ 288 pci_config_put16(softstate->tsoft_pcihdl, 289 softstate->tsoft_acaptr + AGP_CONF_CONTROL, 0x0000); 290 291 pci_config_put32(softstate->tsoft_pcihdl, 292 softstate->tsoft_acaptr + AGP_CONF_ATTBASE, 293 gartaddr & AGP_ATTBASE_MASK); 294 } 295 296 /* 297 * Pre-allocated graphics memory for every type of Intel north bridge, mem size 298 * are specified in kbytes. 299 */ 300 #define GMS_MB(n) ((n) * 1024) 301 #define GMS_SHIFT 4 302 #define GMS_SIZE(a) (sizeof (a) / sizeof (int)) 303 304 /* 305 * Since value zero always means "No memory pre-allocated", value of (GMS - 1) 306 * is used to index these arrays, i.e. gms_xxx[1] contains the mem size (in kb) 307 * that GMS value 0x1 corresponding to. 308 * 309 * Assuming all "reserved" GMS value as zero bytes of pre-allocated graphics 310 * memory, unless some special BIOS settings exist. 311 */ 312 static int gms_810[12] = {0, 0, 0, 0, 0, 0, 0, 512, 0, 0, 0, GMS_MB(1)}; 313 static int gms_830_845[4] = {0, 512, GMS_MB(1), GMS_MB(8)}; 314 static int gms_855GM[5] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 315 GMS_MB(32)}; 316 /* There is no modes for 16M in datasheet, but some BIOS add it. */ 317 static int gms_865_915GM[4] = {GMS_MB(1), 0, GMS_MB(8), GMS_MB(16)}; 318 static int gms_915_945_965[3] = {GMS_MB(1), 0, GMS_MB(8)}; 319 static int gms_965GM[7] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 320 GMS_MB(32), GMS_MB(48), GMS_MB(64)}; 321 static int gms_X33[9] = {GMS_MB(1), GMS_MB(4), GMS_MB(8), GMS_MB(16), 322 GMS_MB(32), GMS_MB(48), GMS_MB(64), GMS_MB(128), GMS_MB(256)}; 323 324 static gms_mode_t gms_modes[] = { 325 {INTEL_BR_810, I810_CONF_SMRAM, I810_GMS_MASK, 326 GMS_SIZE(gms_810), gms_810}, 327 {INTEL_BR_810DC, I810_CONF_SMRAM, I810_GMS_MASK, 328 GMS_SIZE(gms_810), gms_810}, 329 {INTEL_BR_810E, I810_CONF_SMRAM, I810_GMS_MASK, 330 GMS_SIZE(gms_810), gms_810}, 331 {INTEL_BR_830M, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 332 GMS_SIZE(gms_830_845), gms_830_845}, 333 {INTEL_BR_845, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 334 GMS_SIZE(gms_830_845), gms_830_845}, 335 {INTEL_BR_855GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 336 GMS_SIZE(gms_855GM), gms_855GM}, 337 {INTEL_BR_865, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 338 GMS_SIZE(gms_865_915GM), gms_865_915GM}, 339 {INTEL_BR_915GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 340 GMS_SIZE(gms_865_915GM), gms_865_915GM}, 341 {INTEL_BR_915, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 342 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 343 {INTEL_BR_945, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 344 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 345 {INTEL_BR_945GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 346 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 347 {INTEL_BR_946GZ, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 348 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 349 {INTEL_BR_965G1, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 350 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 351 {INTEL_BR_965G2, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 352 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 353 {INTEL_BR_965Q, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 354 GMS_SIZE(gms_915_945_965), gms_915_945_965}, 355 {INTEL_BR_965GM, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 356 GMS_SIZE(gms_965GM), gms_965GM}, 357 {INTEL_BR_965GME, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 358 GMS_SIZE(gms_965GM), gms_965GM}, 359 {INTEL_BR_Q35, I8XX_CONF_GC, IX33_GC_MODE_MASK, 360 GMS_SIZE(gms_X33), gms_X33}, 361 {INTEL_BR_G33, I8XX_CONF_GC, IX33_GC_MODE_MASK, 362 GMS_SIZE(gms_X33), gms_X33}, 363 {INTEL_BR_Q33, I8XX_CONF_GC, IX33_GC_MODE_MASK, 364 GMS_SIZE(gms_X33), gms_X33}, 365 {INTEL_BR_GM45, I8XX_CONF_GC, I8XX_GC_MODE_MASK, 366 GMS_SIZE(gms_965GM), gms_965GM} 367 }; 368 static int 369 get_chip_gms(uint32_t devid) 370 { 371 int num_modes; 372 int i; 373 374 num_modes = (sizeof (gms_modes) / sizeof (gms_mode_t)); 375 376 for (i = 0; i < num_modes; i++) { 377 if (gms_modes[i].gm_devid == devid) 378 break; 379 } 380 381 return ((i == num_modes) ? -1 : i); 382 } 383 384 /* Returns the size (kbytes) of pre-allocated graphics memory */ 385 static size_t 386 i8xx_biosmem_detect(agp_target_softstate_t *softstate) 387 { 388 uint8_t memval; 389 size_t kbytes; 390 int gms_off; 391 392 kbytes = 0; 393 gms_off = softstate->tsoft_gms_off; 394 395 /* fetch the GMS value from DRAM controller */ 396 memval = pci_config_get8(softstate->tsoft_pcihdl, 397 gms_modes[gms_off].gm_regoff); 398 TARGETDB_PRINT2((CE_NOTE, "i8xx_biosmem_detect: memval = %x", memval)); 399 memval = (memval & gms_modes[gms_off].gm_mask) >> GMS_SHIFT; 400 /* assuming zero byte for 0 or "reserved" GMS values */ 401 if (memval == 0 || memval > gms_modes[gms_off].gm_num) { 402 TARGETDB_PRINT2((CE_WARN, "i8xx_biosmem_detect: " 403 "devid = %x, GMS = %x. assuming zero byte of " 404 "pre-allocated memory", 405 gms_modes[gms_off].gm_devid, memval)); 406 goto done; 407 } 408 memval--; /* use (GMS_value - 1) as index */ 409 kbytes = (gms_modes[gms_off].gm_vec)[memval]; 410 411 done: 412 TARGETDB_PRINT2((CE_NOTE, 413 "i8xx_biosmem_detect: %ldKB BIOS pre-allocated memory detected", 414 kbytes)); 415 return (kbytes); 416 } 417 418 /*ARGSUSED*/ 419 static int agptarget_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, 420 void *arg, void **resultp) 421 { 422 agp_target_softstate_t *st; 423 int instance, rval = DDI_FAILURE; 424 dev_t dev; 425 426 switch (cmd) { 427 case DDI_INFO_DEVT2DEVINFO: 428 dev = (dev_t)arg; 429 instance = DEV2INST(dev); 430 st = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 431 if (st != NULL) { 432 mutex_enter(&st->tsoft_lock); 433 *resultp = st->tsoft_dip; 434 mutex_exit(&st->tsoft_lock); 435 rval = DDI_SUCCESS; 436 } else 437 *resultp = NULL; 438 439 break; 440 case DDI_INFO_DEVT2INSTANCE: 441 dev = (dev_t)arg; 442 instance = DEV2INST(dev); 443 *resultp = (void *)(uintptr_t)instance; 444 rval = DDI_SUCCESS; 445 default: 446 break; 447 } 448 449 return (rval); 450 } 451 452 static int 453 intel_br_resume(agp_target_softstate_t *softstate) 454 { 455 int gms_off; 456 457 gms_off = softstate->tsoft_gms_off; 458 459 /* 460 * We recover the gmch graphics control register here 461 */ 462 pci_config_put16(softstate->tsoft_pcihdl, 463 gms_modes[gms_off].gm_regoff, softstate->tsoft_gms); 464 465 return (DDI_SUCCESS); 466 } 467 static int 468 intel_br_suspend(agp_target_softstate_t *softstate) 469 { 470 int gms_off; 471 472 gms_off = softstate->tsoft_gms_off; 473 softstate->tsoft_gms = pci_config_get16(softstate->tsoft_pcihdl, 474 gms_modes[gms_off].gm_regoff); 475 476 return (DDI_SUCCESS); 477 } 478 479 static int 480 agp_target_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 481 { 482 agp_target_softstate_t *softstate; 483 int instance; 484 int status; 485 486 instance = ddi_get_instance(dip); 487 488 switch (cmd) { 489 case DDI_ATTACH: 490 break; 491 case DDI_RESUME: 492 softstate = 493 ddi_get_soft_state(agptarget_glob_soft_handle, instance); 494 return (intel_br_resume(softstate)); 495 default: 496 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 497 "only attach and resume ops are supported")); 498 return (DDI_FAILURE); 499 } 500 501 if (ddi_soft_state_zalloc(agptarget_glob_soft_handle, 502 instance) != DDI_SUCCESS) { 503 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 504 "soft state zalloc failed")); 505 return (DDI_FAILURE); 506 } 507 508 softstate = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 509 mutex_init(&softstate->tsoft_lock, NULL, MUTEX_DRIVER, NULL); 510 softstate->tsoft_dip = dip; 511 status = pci_config_setup(dip, &softstate->tsoft_pcihdl); 512 if (status != DDI_SUCCESS) { 513 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 514 "pci config setup failed")); 515 ddi_soft_state_free(agptarget_glob_soft_handle, 516 instance); 517 return (DDI_FAILURE); 518 } 519 520 softstate->tsoft_devid = pci_config_get32(softstate->tsoft_pcihdl, 521 PCI_CONF_VENID); 522 softstate->tsoft_gms_off = get_chip_gms(softstate->tsoft_devid); 523 if (softstate->tsoft_gms_off < 0) { 524 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 525 "read gms offset failed")); 526 pci_config_teardown(&softstate->tsoft_pcihdl); 527 ddi_soft_state_free(agptarget_glob_soft_handle, 528 instance); 529 return (DDI_FAILURE); 530 } 531 softstate->tsoft_acaptr = agp_target_cap_find(softstate->tsoft_pcihdl); 532 if (softstate->tsoft_acaptr == 0) { 533 /* Make a correction for some Intel chipsets */ 534 if (is_intel_br(softstate)) 535 softstate->tsoft_acaptr = AGP_CAP_OFF_DEF; 536 else { 537 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 538 "Not a supposed corretion")); 539 pci_config_teardown(&softstate->tsoft_pcihdl); 540 ddi_soft_state_free(agptarget_glob_soft_handle, 541 instance); 542 return (DDI_FAILURE); 543 } 544 } 545 546 status = ddi_create_minor_node(dip, AGPTARGET_NAME, S_IFCHR, 547 INST2NODENUM(instance), DDI_NT_AGP_TARGET, 0); 548 549 if (status != DDI_SUCCESS) { 550 TARGETDB_PRINT2((CE_WARN, "agp_target_attach:" 551 "Create minor node failed")); 552 pci_config_teardown(&softstate->tsoft_pcihdl); 553 ddi_soft_state_free(agptarget_glob_soft_handle, instance); 554 return (DDI_FAILURE); 555 } 556 557 return (DDI_SUCCESS); 558 } 559 560 /*ARGSUSED*/ 561 static int 562 agp_target_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 563 { 564 int instance; 565 agp_target_softstate_t *softstate; 566 567 instance = ddi_get_instance(dip); 568 softstate = ddi_get_soft_state(agptarget_glob_soft_handle, instance); 569 570 if (cmd == DDI_SUSPEND) { 571 /* get GMS modes list entry */ 572 return (intel_br_suspend(softstate)); 573 } 574 575 if (cmd != DDI_DETACH) { 576 TARGETDB_PRINT2((CE_WARN, "agp_target_detach:" 577 "only detach and suspend ops are supported")); 578 return (DDI_FAILURE); 579 } 580 581 ddi_remove_minor_node(dip, AGPTARGET_NAME); 582 pci_config_teardown(&softstate->tsoft_pcihdl); 583 mutex_destroy(&softstate->tsoft_lock); 584 ddi_soft_state_free(agptarget_glob_soft_handle, instance); 585 return (DDI_SUCCESS); 586 } 587 588 /*ARGSUSED*/ 589 static int 590 agp_target_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 591 cred_t *cred, int *rval) 592 { 593 int instance = DEV2INST(dev); 594 agp_target_softstate_t *st; 595 static char kernel_only[] = 596 "amd64_gart_ioctl: is a kernel only ioctl"; 597 598 if (!(mode & FKIOCTL)) { 599 TARGETDB_PRINT2((CE_CONT, kernel_only)); 600 return (ENXIO); 601 } 602 st = GETSOFTC(instance); 603 604 if (st == NULL) 605 return (ENXIO); 606 607 mutex_enter(&st->tsoft_lock); 608 609 switch (cmd) { 610 case CHIP_DETECT: 611 { 612 int type = 0; 613 614 if (is_intel_br(st)) 615 type = CHIP_IS_INTEL; 616 else if (is_64bit_aper(st)) 617 type = CHIP_IS_AMD; 618 else { 619 type = 0; 620 TARGETDB_PRINT2((CE_WARN, "Unknown bridge!")); 621 } 622 623 if (ddi_copyout(&type, (void *)data, sizeof (int), mode)) { 624 mutex_exit(&st->tsoft_lock); 625 return (EFAULT); 626 } 627 628 break; 629 } 630 case I8XX_GET_PREALLOC_SIZE: 631 { 632 size_t prealloc_size; 633 634 if (!is_intel_br(st)) { 635 mutex_exit(&st->tsoft_lock); 636 return (EINVAL); 637 } 638 639 prealloc_size = i8xx_biosmem_detect(st); 640 if (ddi_copyout(&prealloc_size, (void *)data, 641 sizeof (size_t), mode)) { 642 mutex_exit(&st->tsoft_lock); 643 return (EFAULT); 644 } 645 646 break; 647 } 648 case AGP_TARGET_GETINFO: 649 { 650 i_agp_info_t info; 651 uint32_t value; 652 off_t cap; 653 654 ASSERT(st->tsoft_acaptr); 655 656 cap = st->tsoft_acaptr; 657 value = pci_config_get32(st->tsoft_pcihdl, cap); 658 info.iagp_ver.agpv_major = (uint16_t)((value >> 20) & 0xf); 659 info.iagp_ver.agpv_minor = (uint16_t)((value >> 16) & 0xf); 660 info.iagp_devid = st->tsoft_devid; 661 info.iagp_mode = pci_config_get32(st->tsoft_pcihdl, 662 cap + AGP_CONF_STATUS); 663 info.iagp_aperbase = agp_target_get_apbase(st); 664 info.iagp_apersize = agp_target_get_apsize(st); 665 666 if (ddi_copyout(&info, (void *)data, 667 sizeof (i_agp_info_t), mode)) { 668 mutex_exit(&st->tsoft_lock); 669 return (EFAULT); 670 } 671 break; 672 673 } 674 /* 675 * This ioctl is only for Intel AGP chipsets. 676 * It is not necessary for the AMD8151 AGP bridge, because 677 * this register in the AMD8151 does not control any hardware. 678 * It is only provided for compatibility with an Intel AGP bridge. 679 * Please refer to the <<AMD8151 data sheet>> page 24, 680 * AGP device GART pointer. 681 */ 682 case AGP_TARGET_SET_GATTADDR: 683 { 684 uint32_t gartaddr; 685 686 if (ddi_copyin((void *)data, &gartaddr, 687 sizeof (uint32_t), mode)) { 688 mutex_exit(&st->tsoft_lock); 689 return (EFAULT); 690 } 691 692 agp_target_set_gartaddr(st, gartaddr); 693 break; 694 } 695 case AGP_TARGET_SETCMD: 696 { 697 uint32_t command; 698 699 if (ddi_copyin((void *)data, &command, 700 sizeof (uint32_t), mode)) { 701 mutex_exit(&st->tsoft_lock); 702 return (EFAULT); 703 } 704 705 ASSERT(st->tsoft_acaptr); 706 707 pci_config_put32(st->tsoft_pcihdl, 708 st->tsoft_acaptr + AGP_CONF_COMMAND, 709 command); 710 break; 711 712 } 713 case AGP_TARGET_FLUSH_GTLB: 714 { 715 uint16_t value; 716 717 ASSERT(st->tsoft_acaptr); 718 719 value = pci_config_get16(st->tsoft_pcihdl, 720 st->tsoft_acaptr + AGP_CONF_CONTROL); 721 value &= ~AGPCTRL_GTLBEN; 722 pci_config_put16(st->tsoft_pcihdl, 723 st->tsoft_acaptr + AGP_CONF_CONTROL, value); 724 value |= AGPCTRL_GTLBEN; 725 pci_config_put16(st->tsoft_pcihdl, 726 st->tsoft_acaptr + AGP_CONF_CONTROL, value); 727 728 break; 729 } 730 case AGP_TARGET_CONFIGURE: 731 { 732 uint8_t value; 733 734 ASSERT(st->tsoft_acaptr); 735 736 /* 737 * In Intel agp bridges, agp misc register offset 738 * is indexed from 0 instead of capability register. 739 * AMD agp bridges have no such misc register 740 * to control the aperture access, and they have 741 * similar regsiters in CPU gart devices instead. 742 */ 743 744 if (is_intel_br(st)) { 745 value = pci_config_get8(st->tsoft_pcihdl, 746 st->tsoft_acaptr + AGP_CONF_MISC); 747 value |= AGP_MISC_APEN; 748 pci_config_put8(st->tsoft_pcihdl, 749 st->tsoft_acaptr + AGP_CONF_MISC, value); 750 } 751 break; 752 753 } 754 case AGP_TARGET_UNCONFIG: 755 { 756 uint32_t value1; 757 uint8_t value2; 758 759 ASSERT(st->tsoft_acaptr); 760 761 pci_config_put16(st->tsoft_pcihdl, 762 st->tsoft_acaptr + AGP_CONF_CONTROL, 0x0); 763 764 if (is_intel_br(st)) { 765 value2 = pci_config_get8(st->tsoft_pcihdl, 766 st->tsoft_acaptr + AGP_CONF_MISC); 767 value2 &= ~AGP_MISC_APEN; 768 pci_config_put8(st->tsoft_pcihdl, 769 st->tsoft_acaptr + AGP_CONF_MISC, value2); 770 } 771 772 value1 = pci_config_get32(st->tsoft_pcihdl, 773 st->tsoft_acaptr + AGP_CONF_COMMAND); 774 value1 &= ~AGPCMD_AGPEN; 775 pci_config_put32(st->tsoft_pcihdl, 776 st->tsoft_acaptr + AGP_CONF_COMMAND, 777 value1); 778 779 pci_config_put32(st->tsoft_pcihdl, 780 st->tsoft_acaptr + AGP_CONF_ATTBASE, 0x0); 781 782 break; 783 } 784 785 default: 786 mutex_exit(&st->tsoft_lock); 787 return (ENXIO); 788 } /* end switch */ 789 790 mutex_exit(&st->tsoft_lock); 791 792 return (0); 793 } 794 795 /*ARGSUSED*/ 796 static int 797 agp_target_open(dev_t *devp, int flag, int otyp, cred_t *cred) 798 { 799 int instance = DEV2INST(*devp); 800 agp_target_softstate_t *st; 801 802 if (!(flag & FKLYR)) 803 return (ENXIO); 804 805 st = GETSOFTC(instance); 806 807 if (st == NULL) 808 return (ENXIO); 809 810 return (0); 811 } 812 813 /*ARGSUSED*/ 814 static int 815 agp_target_close(dev_t dev, int flag, int otyp, cred_t *cred) 816 { 817 int instance = DEV2INST(dev); 818 agp_target_softstate_t *st; 819 820 st = GETSOFTC(instance); 821 822 if (st == NULL) 823 return (ENXIO); 824 825 return (0); 826 } 827 828 static struct cb_ops agp_target_cb_ops = { 829 agp_target_open, /* cb_open */ 830 agp_target_close, /* cb_close */ 831 nodev, /* cb_strategy */ 832 nodev, /* cb_print */ 833 nodev, /* cb_dump */ 834 nodev, /* cb_read() */ 835 nodev, /* cb_write() */ 836 agp_target_ioctl, /* cb_ioctl */ 837 nodev, /* cb_devmap */ 838 nodev, /* cb_mmap */ 839 nodev, /* cb_segmap */ 840 nochpoll, /* cb_chpoll */ 841 ddi_prop_op, /* cb_prop_op */ 842 0, /* cb_stream */ 843 D_NEW | D_MP, /* cb_flag */ 844 CB_REV, /* cb_ops version? */ 845 nodev, /* cb_aread() */ 846 nodev, /* cb_awrite() */ 847 }; 848 849 /* device operations */ 850 static struct dev_ops agp_target_ops = { 851 DEVO_REV, /* devo_rev */ 852 0, /* devo_refcnt */ 853 agptarget_getinfo, /* devo_getinfo */ 854 nulldev, /* devo_identify */ 855 nulldev, /* devo_probe */ 856 agp_target_attach, /* devo_attach */ 857 agp_target_detach, /* devo_detach */ 858 nodev, /* devo_reset */ 859 &agp_target_cb_ops, /* devo_cb_ops */ 860 0, /* devo_bus_ops */ 861 0, /* devo_power */ 862 ddi_quiesce_not_supported, /* devo_quiesce */ 863 }; 864 865 static struct modldrv modldrv = { 866 &mod_driverops, 867 "AGP target driver", 868 &agp_target_ops, 869 }; 870 871 static struct modlinkage modlinkage = { 872 MODREV_1, /* MODREV_1 is indicated by manual */ 873 {&modldrv, NULL, NULL, NULL} 874 }; 875 876 int 877 _init(void) 878 { 879 int ret; 880 881 ret = ddi_soft_state_init(&agptarget_glob_soft_handle, 882 sizeof (agp_target_softstate_t), 1); 883 884 if (ret) 885 goto err1; 886 887 if ((ret = mod_install(&modlinkage)) != 0) { 888 goto err2; 889 } 890 891 return (DDI_SUCCESS); 892 err2: 893 ddi_soft_state_fini(&agptarget_glob_soft_handle); 894 err1: 895 return (ret); 896 } 897 898 int 899 _info(struct modinfo *modinfop) 900 { 901 return (mod_info(&modlinkage, modinfop)); 902 } 903 904 int 905 _fini(void) 906 { 907 int ret; 908 909 if ((ret = mod_remove(&modlinkage)) == 0) { 910 ddi_soft_state_fini(&agptarget_glob_soft_handle); 911 } 912 return (ret); 913 } 914