1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*0Sstevel@tonic-gate 29*0Sstevel@tonic-gate /* 30*0Sstevel@tonic-gate * x86-specific routines used by the CPU Performance counter driver. 31*0Sstevel@tonic-gate */ 32*0Sstevel@tonic-gate 33*0Sstevel@tonic-gate #include <sys/types.h> 34*0Sstevel@tonic-gate #include <sys/time.h> 35*0Sstevel@tonic-gate #include <sys/atomic.h> 36*0Sstevel@tonic-gate #include <sys/regset.h> 37*0Sstevel@tonic-gate #include <sys/privregs.h> 38*0Sstevel@tonic-gate #include <sys/x86_archext.h> 39*0Sstevel@tonic-gate #include <sys/cpuvar.h> 40*0Sstevel@tonic-gate #include <sys/machcpuvar.h> 41*0Sstevel@tonic-gate #include <sys/archsystm.h> 42*0Sstevel@tonic-gate #include <sys/cpc_pcbe.h> 43*0Sstevel@tonic-gate #include <sys/cpc_impl.h> 44*0Sstevel@tonic-gate #include <sys/x_call.h> 45*0Sstevel@tonic-gate #include <sys/cmn_err.h> 46*0Sstevel@tonic-gate #include <sys/chip.h> 47*0Sstevel@tonic-gate #include <sys/spl.h> 48*0Sstevel@tonic-gate #include <io/pcplusmp/apic.h> 49*0Sstevel@tonic-gate 50*0Sstevel@tonic-gate static const uint64_t allstopped = 0; 51*0Sstevel@tonic-gate static kcpc_ctx_t *(*overflow_intr_handler)(caddr_t); 52*0Sstevel@tonic-gate 53*0Sstevel@tonic-gate int kcpc_hw_overflow_intr_installed; /* set by APIC code */ 54*0Sstevel@tonic-gate extern kcpc_ctx_t *kcpc_overflow_intr(caddr_t arg, uint64_t bitmap); 55*0Sstevel@tonic-gate 56*0Sstevel@tonic-gate extern int kcpc_counts_include_idle; /* Project Private /etc/system variable */ 57*0Sstevel@tonic-gate 58*0Sstevel@tonic-gate void (*kcpc_hw_enable_cpc_intr)(void); /* set by APIC code */ 59*0Sstevel@tonic-gate 60*0Sstevel@tonic-gate int 61*0Sstevel@tonic-gate kcpc_hw_add_ovf_intr(kcpc_ctx_t *(*handler)(caddr_t)) 62*0Sstevel@tonic-gate { 63*0Sstevel@tonic-gate if (x86_type != X86_TYPE_P6) 64*0Sstevel@tonic-gate return (0); 65*0Sstevel@tonic-gate overflow_intr_handler = handler; 66*0Sstevel@tonic-gate return (ipltospl(APIC_PCINT_IPL)); 67*0Sstevel@tonic-gate } 68*0Sstevel@tonic-gate 69*0Sstevel@tonic-gate void 70*0Sstevel@tonic-gate kcpc_hw_rem_ovf_intr(void) 71*0Sstevel@tonic-gate { 72*0Sstevel@tonic-gate overflow_intr_handler = NULL; 73*0Sstevel@tonic-gate } 74*0Sstevel@tonic-gate 75*0Sstevel@tonic-gate /* 76*0Sstevel@tonic-gate * Hook used on P4 systems to catch online/offline events. 77*0Sstevel@tonic-gate */ 78*0Sstevel@tonic-gate /*ARGSUSED*/ 79*0Sstevel@tonic-gate static int 80*0Sstevel@tonic-gate kcpc_cpu_setup(cpu_setup_t what, int cpuid, void *arg) 81*0Sstevel@tonic-gate { 82*0Sstevel@tonic-gate chip_t *chp = cpu[cpuid]->cpu_chip; 83*0Sstevel@tonic-gate 84*0Sstevel@tonic-gate if (what != CPU_ON) 85*0Sstevel@tonic-gate return (0); 86*0Sstevel@tonic-gate 87*0Sstevel@tonic-gate /* 88*0Sstevel@tonic-gate * If any CPU-bound contexts exist, we don't need to invalidate 89*0Sstevel@tonic-gate * anything, as no per-LWP contexts can coexist. 90*0Sstevel@tonic-gate */ 91*0Sstevel@tonic-gate if (kcpc_cpuctx) 92*0Sstevel@tonic-gate return (0); 93*0Sstevel@tonic-gate 94*0Sstevel@tonic-gate /* 95*0Sstevel@tonic-gate * If this chip now has more than 1 active cpu, we must invalidate all 96*0Sstevel@tonic-gate * contexts in the system. 97*0Sstevel@tonic-gate */ 98*0Sstevel@tonic-gate if (chp->chip_ncpu > 1) 99*0Sstevel@tonic-gate kcpc_invalidate_all(); 100*0Sstevel@tonic-gate 101*0Sstevel@tonic-gate return (0); 102*0Sstevel@tonic-gate } 103*0Sstevel@tonic-gate 104*0Sstevel@tonic-gate static kmutex_t cpu_setup_lock; /* protects setup_registered */ 105*0Sstevel@tonic-gate static int setup_registered; 106*0Sstevel@tonic-gate 107*0Sstevel@tonic-gate void 108*0Sstevel@tonic-gate kcpc_hw_init(cpu_t *cp) 109*0Sstevel@tonic-gate { 110*0Sstevel@tonic-gate kthread_t *t = cp->cpu_idle_thread; 111*0Sstevel@tonic-gate 112*0Sstevel@tonic-gate if (x86_feature & X86_HTT) { 113*0Sstevel@tonic-gate mutex_enter(&cpu_setup_lock); 114*0Sstevel@tonic-gate if (setup_registered == 0) { 115*0Sstevel@tonic-gate mutex_enter(&cpu_lock); 116*0Sstevel@tonic-gate register_cpu_setup_func(kcpc_cpu_setup, NULL); 117*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 118*0Sstevel@tonic-gate setup_registered = 1; 119*0Sstevel@tonic-gate } 120*0Sstevel@tonic-gate mutex_exit(&cpu_setup_lock); 121*0Sstevel@tonic-gate } 122*0Sstevel@tonic-gate 123*0Sstevel@tonic-gate mutex_init(&cp->cpu_cpc_ctxlock, "cpu_cpc_ctxlock", MUTEX_DEFAULT, 0); 124*0Sstevel@tonic-gate 125*0Sstevel@tonic-gate if (kcpc_counts_include_idle) 126*0Sstevel@tonic-gate return; 127*0Sstevel@tonic-gate 128*0Sstevel@tonic-gate installctx(t, cp, kcpc_idle_save, kcpc_idle_restore, 129*0Sstevel@tonic-gate NULL, NULL, NULL, NULL); 130*0Sstevel@tonic-gate } 131*0Sstevel@tonic-gate 132*0Sstevel@tonic-gate #define BITS(v, u, l) \ 133*0Sstevel@tonic-gate (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 134*0Sstevel@tonic-gate 135*0Sstevel@tonic-gate #define PCBE_NAMELEN 30 /* Enough Room for pcbe.manuf.model.family.stepping */ 136*0Sstevel@tonic-gate 137*0Sstevel@tonic-gate /* 138*0Sstevel@tonic-gate * Examine the processor and load an appropriate PCBE. 139*0Sstevel@tonic-gate */ 140*0Sstevel@tonic-gate int 141*0Sstevel@tonic-gate kcpc_hw_load_pcbe(void) 142*0Sstevel@tonic-gate { 143*0Sstevel@tonic-gate return (kcpc_pcbe_tryload(cpuid_getvendorstr(CPU), cpuid_getfamily(CPU), 144*0Sstevel@tonic-gate cpuid_getmodel(CPU), cpuid_getstep(CPU))); 145*0Sstevel@tonic-gate } 146*0Sstevel@tonic-gate 147*0Sstevel@tonic-gate static int 148*0Sstevel@tonic-gate kcpc_remotestop_func(void) 149*0Sstevel@tonic-gate { 150*0Sstevel@tonic-gate ASSERT(CPU->cpu_cpc_ctx != NULL); 151*0Sstevel@tonic-gate pcbe_ops->pcbe_allstop(); 152*0Sstevel@tonic-gate atomic_or_uint(&CPU->cpu_cpc_ctx->kc_flags, KCPC_CTX_INVALID_STOPPED); 153*0Sstevel@tonic-gate 154*0Sstevel@tonic-gate return (0); 155*0Sstevel@tonic-gate } 156*0Sstevel@tonic-gate 157*0Sstevel@tonic-gate /* 158*0Sstevel@tonic-gate * Ensure the counters are stopped on the given processor. 159*0Sstevel@tonic-gate * 160*0Sstevel@tonic-gate * Callers must ensure kernel preemption is disabled. 161*0Sstevel@tonic-gate */ 162*0Sstevel@tonic-gate void 163*0Sstevel@tonic-gate kcpc_remote_stop(cpu_t *cp) 164*0Sstevel@tonic-gate { 165*0Sstevel@tonic-gate cpuset_t set; 166*0Sstevel@tonic-gate 167*0Sstevel@tonic-gate CPUSET_ZERO(set); 168*0Sstevel@tonic-gate 169*0Sstevel@tonic-gate CPUSET_ADD(set, cp->cpu_id); 170*0Sstevel@tonic-gate 171*0Sstevel@tonic-gate xc_sync(0, 0, 0, X_CALL_HIPRI, set, (xc_func_t)kcpc_remotestop_func); 172*0Sstevel@tonic-gate } 173*0Sstevel@tonic-gate 174*0Sstevel@tonic-gate /* 175*0Sstevel@tonic-gate * Called by the generic framework to check if it's OK to bind a set to a CPU. 176*0Sstevel@tonic-gate */ 177*0Sstevel@tonic-gate int 178*0Sstevel@tonic-gate kcpc_hw_cpu_hook(processorid_t cpuid, ulong_t *kcpc_cpumap) 179*0Sstevel@tonic-gate { 180*0Sstevel@tonic-gate cpu_t *p, *cpu; 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate if ((x86_feature & X86_HTT) == 0) 183*0Sstevel@tonic-gate return (0); 184*0Sstevel@tonic-gate 185*0Sstevel@tonic-gate /* 186*0Sstevel@tonic-gate * Only one logical CPU on each Pentium 4 HT CPU may be bound to at 187*0Sstevel@tonic-gate * once. 188*0Sstevel@tonic-gate * 189*0Sstevel@tonic-gate * This loop is protected by holding cpu_lock, in order to properly 190*0Sstevel@tonic-gate * access the cpu_t of the desired cpu. This also guarantees that the 191*0Sstevel@tonic-gate * per chip cpu lists will not change whilst we look at them. 192*0Sstevel@tonic-gate */ 193*0Sstevel@tonic-gate mutex_enter(&cpu_lock); 194*0Sstevel@tonic-gate if ((cpu = cpu_get(cpuid)) == NULL) { 195*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 196*0Sstevel@tonic-gate return (-1); 197*0Sstevel@tonic-gate } 198*0Sstevel@tonic-gate 199*0Sstevel@tonic-gate for (p = cpu->cpu_next_chip; p != cpu; p = p->cpu_next_chip) { 200*0Sstevel@tonic-gate if (BT_TEST(kcpc_cpumap, p->cpu_id)) { 201*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 202*0Sstevel@tonic-gate return (-1); 203*0Sstevel@tonic-gate } 204*0Sstevel@tonic-gate } 205*0Sstevel@tonic-gate 206*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 207*0Sstevel@tonic-gate return (0); 208*0Sstevel@tonic-gate } 209*0Sstevel@tonic-gate 210*0Sstevel@tonic-gate /* 211*0Sstevel@tonic-gate * Called by the generic framework to check if it's OK to bind a set to an LWP. 212*0Sstevel@tonic-gate */ 213*0Sstevel@tonic-gate int 214*0Sstevel@tonic-gate kcpc_hw_lwp_hook(void) 215*0Sstevel@tonic-gate { 216*0Sstevel@tonic-gate chip_t *p; 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate if ((x86_feature & X86_HTT) == 0) 219*0Sstevel@tonic-gate return (0); 220*0Sstevel@tonic-gate 221*0Sstevel@tonic-gate /* 222*0Sstevel@tonic-gate * Only one CPU per chip may be online. 223*0Sstevel@tonic-gate */ 224*0Sstevel@tonic-gate mutex_enter(&cpu_lock); 225*0Sstevel@tonic-gate p = CPU->cpu_chip; 226*0Sstevel@tonic-gate do { 227*0Sstevel@tonic-gate if (p->chip_ncpu > 1) { 228*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 229*0Sstevel@tonic-gate return (-1); 230*0Sstevel@tonic-gate } 231*0Sstevel@tonic-gate p = p->chip_next; 232*0Sstevel@tonic-gate } while (p != CPU->cpu_chip); 233*0Sstevel@tonic-gate mutex_exit(&cpu_lock); 234*0Sstevel@tonic-gate return (0); 235*0Sstevel@tonic-gate } 236