1*748Sdmick /*
2*748Sdmick * CDDL HEADER START
3*748Sdmick *
4*748Sdmick * The contents of this file are subject to the terms of the
5*748Sdmick * Common Development and Distribution License, Version 1.0 only
6*748Sdmick * (the "License"). You may not use this file except in compliance
7*748Sdmick * with the License.
8*748Sdmick *
9*748Sdmick * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10*748Sdmick * or http://www.opensolaris.org/os/licensing.
11*748Sdmick * See the License for the specific language governing permissions
12*748Sdmick * and limitations under the License.
13*748Sdmick *
14*748Sdmick * When distributing Covered Code, include this CDDL HEADER in each
15*748Sdmick * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16*748Sdmick * If applicable, add the following below this CDDL HEADER, with the
17*748Sdmick * fields enclosed by brackets "[]" replaced with your own identifying
18*748Sdmick * information: Portions Copyright [yyyy] [name of copyright owner]
19*748Sdmick *
20*748Sdmick * CDDL HEADER END
21*748Sdmick */
22*748Sdmick /*
23*748Sdmick * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24*748Sdmick * Use is subject to license terms.
25*748Sdmick */
26*748Sdmick
27*748Sdmick #pragma ident "%Z%%M% %I% %E% SMI"
28*748Sdmick
29*748Sdmick /*
30*748Sdmick * PCI Mechanism 1 low-level routines
31*748Sdmick */
32*748Sdmick
33*748Sdmick #include <sys/types.h>
34*748Sdmick #include <sys/pci.h>
35*748Sdmick #include <sys/pci_impl.h>
36*748Sdmick #include <sys/sunddi.h>
37*748Sdmick #include <sys/pci_cfgspace_impl.h>
38*748Sdmick
39*748Sdmick /*
40*748Sdmick * Per PCI 2.1 section 3.7.4.1 and PCI-PCI Bridge Architecture 1.0 section
41*748Sdmick * 5.3.1.2: dev=31 func=7 reg=0 means a special cycle. We don't want to
42*748Sdmick * trigger that by accident, so we pretend that dev 31, func 7 doesn't
43*748Sdmick * exist. If we ever want special cycle support, we'll add explicit
44*748Sdmick * special cycle support.
45*748Sdmick */
46*748Sdmick
47*748Sdmick uint8_t
pci_mech1_getb(int bus,int device,int function,int reg)48*748Sdmick pci_mech1_getb(int bus, int device, int function, int reg)
49*748Sdmick {
50*748Sdmick uint8_t val;
51*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
52*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
53*748Sdmick return (0xff);
54*748Sdmick }
55*748Sdmick
56*748Sdmick mutex_enter(&pcicfg_mutex);
57*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
58*748Sdmick val = inb(PCI_CONFDATA | (reg & 0x3));
59*748Sdmick mutex_exit(&pcicfg_mutex);
60*748Sdmick return (val);
61*748Sdmick }
62*748Sdmick
63*748Sdmick uint16_t
pci_mech1_getw(int bus,int device,int function,int reg)64*748Sdmick pci_mech1_getw(int bus, int device, int function, int reg)
65*748Sdmick {
66*748Sdmick uint16_t val;
67*748Sdmick
68*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
69*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
70*748Sdmick return (0xffff);
71*748Sdmick }
72*748Sdmick
73*748Sdmick mutex_enter(&pcicfg_mutex);
74*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
75*748Sdmick val = inw(PCI_CONFDATA | (reg & 0x2));
76*748Sdmick mutex_exit(&pcicfg_mutex);
77*748Sdmick return (val);
78*748Sdmick }
79*748Sdmick
80*748Sdmick uint32_t
pci_mech1_getl(int bus,int device,int function,int reg)81*748Sdmick pci_mech1_getl(int bus, int device, int function, int reg)
82*748Sdmick {
83*748Sdmick uint32_t val;
84*748Sdmick
85*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
86*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
87*748Sdmick return (0xffffffffu);
88*748Sdmick }
89*748Sdmick
90*748Sdmick mutex_enter(&pcicfg_mutex);
91*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
92*748Sdmick val = inl(PCI_CONFDATA);
93*748Sdmick mutex_exit(&pcicfg_mutex);
94*748Sdmick return (val);
95*748Sdmick }
96*748Sdmick
97*748Sdmick void
pci_mech1_putb(int bus,int device,int function,int reg,uint8_t val)98*748Sdmick pci_mech1_putb(int bus, int device, int function, int reg, uint8_t val)
99*748Sdmick {
100*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
101*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
102*748Sdmick return;
103*748Sdmick }
104*748Sdmick
105*748Sdmick mutex_enter(&pcicfg_mutex);
106*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
107*748Sdmick outb(PCI_CONFDATA | (reg & 0x3), val);
108*748Sdmick mutex_exit(&pcicfg_mutex);
109*748Sdmick }
110*748Sdmick
111*748Sdmick void
pci_mech1_putw(int bus,int device,int function,int reg,uint16_t val)112*748Sdmick pci_mech1_putw(int bus, int device, int function, int reg, uint16_t val)
113*748Sdmick {
114*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
115*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
116*748Sdmick return;
117*748Sdmick }
118*748Sdmick
119*748Sdmick mutex_enter(&pcicfg_mutex);
120*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
121*748Sdmick outw(PCI_CONFDATA | (reg & 0x2), val);
122*748Sdmick mutex_exit(&pcicfg_mutex);
123*748Sdmick }
124*748Sdmick
125*748Sdmick void
pci_mech1_putl(int bus,int device,int function,int reg,uint32_t val)126*748Sdmick pci_mech1_putl(int bus, int device, int function, int reg, uint32_t val)
127*748Sdmick {
128*748Sdmick if (device == PCI_MECH1_SPEC_CYCLE_DEV &&
129*748Sdmick function == PCI_MECH1_SPEC_CYCLE_FUNC) {
130*748Sdmick return;
131*748Sdmick }
132*748Sdmick
133*748Sdmick mutex_enter(&pcicfg_mutex);
134*748Sdmick outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg));
135*748Sdmick outl(PCI_CONFDATA, val);
136*748Sdmick mutex_exit(&pcicfg_mutex);
137*748Sdmick }
138