xref: /onnv-gate/usr/src/uts/i86pc/os/intr.c (revision 12825:e35468461453)
10Sstevel@tonic-gate /*
20Sstevel@tonic-gate  * CDDL HEADER START
30Sstevel@tonic-gate  *
40Sstevel@tonic-gate  * The contents of this file are subject to the terms of the
51455Sandrei  * Common Development and Distribution License (the "License").
61455Sandrei  * You may not use this file except in compliance with the License.
70Sstevel@tonic-gate  *
80Sstevel@tonic-gate  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
90Sstevel@tonic-gate  * or http://www.opensolaris.org/os/licensing.
100Sstevel@tonic-gate  * See the License for the specific language governing permissions
110Sstevel@tonic-gate  * and limitations under the License.
120Sstevel@tonic-gate  *
130Sstevel@tonic-gate  * When distributing Covered Code, include this CDDL HEADER in each
140Sstevel@tonic-gate  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
150Sstevel@tonic-gate  * If applicable, add the following below this CDDL HEADER, with the
160Sstevel@tonic-gate  * fields enclosed by brackets "[]" replaced with your own identifying
170Sstevel@tonic-gate  * information: Portions Copyright [yyyy] [name of copyright owner]
180Sstevel@tonic-gate  *
190Sstevel@tonic-gate  * CDDL HEADER END
200Sstevel@tonic-gate  */
215084Sjohnlev 
220Sstevel@tonic-gate /*
23*12825SJimmy.Vetayases@oracle.com  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
240Sstevel@tonic-gate  */
250Sstevel@tonic-gate 
260Sstevel@tonic-gate #include <sys/cpuvar.h>
279637SRandy.Fishel@Sun.COM #include <sys/cpu_event.h>
280Sstevel@tonic-gate #include <sys/regset.h>
290Sstevel@tonic-gate #include <sys/psw.h>
300Sstevel@tonic-gate #include <sys/types.h>
310Sstevel@tonic-gate #include <sys/thread.h>
320Sstevel@tonic-gate #include <sys/systm.h>
330Sstevel@tonic-gate #include <sys/segments.h>
340Sstevel@tonic-gate #include <sys/pcb.h>
350Sstevel@tonic-gate #include <sys/trap.h>
360Sstevel@tonic-gate #include <sys/ftrace.h>
370Sstevel@tonic-gate #include <sys/traptrace.h>
380Sstevel@tonic-gate #include <sys/clock.h>
390Sstevel@tonic-gate #include <sys/panic.h>
400Sstevel@tonic-gate #include <sys/disp.h>
410Sstevel@tonic-gate #include <vm/seg_kp.h>
420Sstevel@tonic-gate #include <sys/stack.h>
430Sstevel@tonic-gate #include <sys/sysmacros.h>
440Sstevel@tonic-gate #include <sys/cmn_err.h>
450Sstevel@tonic-gate #include <sys/kstat.h>
460Sstevel@tonic-gate #include <sys/smp_impldefs.h>
470Sstevel@tonic-gate #include <sys/pool_pset.h>
480Sstevel@tonic-gate #include <sys/zone.h>
490Sstevel@tonic-gate #include <sys/bitmap.h>
503446Smrj #include <sys/archsystm.h>
513446Smrj #include <sys/machsystm.h>
523446Smrj #include <sys/ontrap.h>
533446Smrj #include <sys/x86_archext.h>
543446Smrj #include <sys/promif.h>
554191Sjosephb #include <vm/hat_i86.h>
565084Sjohnlev #if defined(__xpv)
575084Sjohnlev #include <sys/hypervisor.h>
585084Sjohnlev #endif
590Sstevel@tonic-gate 
600Sstevel@tonic-gate 
615084Sjohnlev #if defined(__xpv) && defined(DEBUG)
625084Sjohnlev 
635084Sjohnlev /*
645084Sjohnlev  * This panic message is intended as an aid to interrupt debugging.
655084Sjohnlev  *
665084Sjohnlev  * The associated assertion tests the condition of enabling
675084Sjohnlev  * events when events are already enabled.  The implication
685084Sjohnlev  * being that whatever code the programmer thought was
695084Sjohnlev  * protected by having events disabled until the second
705084Sjohnlev  * enable happened really wasn't protected at all ..
715084Sjohnlev  */
725084Sjohnlev 
735084Sjohnlev int stistipanic = 1;	/* controls the debug panic check */
745084Sjohnlev const char *stistimsg = "stisti";
755084Sjohnlev ulong_t laststi[NCPU];
765084Sjohnlev 
775084Sjohnlev /*
785084Sjohnlev  * This variable tracks the last place events were disabled on each cpu
799637SRandy.Fishel@Sun.COM  * it assists in debugging when asserts that interrupts are enabled trip.
805084Sjohnlev  */
815084Sjohnlev ulong_t lastcli[NCPU];
825084Sjohnlev 
835084Sjohnlev #endif
845084Sjohnlev 
8512683SJimmy.Vetayases@oracle.com void do_interrupt(struct regs *rp, trap_trace_rec_t *ttp);
8612683SJimmy.Vetayases@oracle.com 
8712683SJimmy.Vetayases@oracle.com void (*do_interrupt_common)(struct regs *, trap_trace_rec_t *) = do_interrupt;
8812683SJimmy.Vetayases@oracle.com uintptr_t (*get_intr_handler)(int, short) = NULL;
8912683SJimmy.Vetayases@oracle.com 
900Sstevel@tonic-gate /*
913446Smrj  * Set cpu's base SPL level to the highest active interrupt level
920Sstevel@tonic-gate  */
933446Smrj void
set_base_spl(void)943446Smrj set_base_spl(void)
950Sstevel@tonic-gate {
963446Smrj 	struct cpu *cpu = CPU;
973446Smrj 	uint16_t active = (uint16_t)cpu->cpu_intr_actv;
980Sstevel@tonic-gate 
993446Smrj 	cpu->cpu_base_spl = active == 0 ? 0 : bsrw_insn(active);
1000Sstevel@tonic-gate }
1010Sstevel@tonic-gate 
1020Sstevel@tonic-gate /*
1030Sstevel@tonic-gate  * Do all the work necessary to set up the cpu and thread structures
1040Sstevel@tonic-gate  * to dispatch a high-level interrupt.
1050Sstevel@tonic-gate  *
1060Sstevel@tonic-gate  * Returns 0 if we're -not- already on the high-level interrupt stack,
1070Sstevel@tonic-gate  * (and *must* switch to it), non-zero if we are already on that stack.
1080Sstevel@tonic-gate  *
1090Sstevel@tonic-gate  * Called with interrupts masked.
1100Sstevel@tonic-gate  * The 'pil' is already set to the appropriate level for rp->r_trapno.
1110Sstevel@tonic-gate  */
1123446Smrj static int
hilevel_intr_prolog(struct cpu * cpu,uint_t pil,uint_t oldpil,struct regs * rp)1130Sstevel@tonic-gate hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp)
1140Sstevel@tonic-gate {
1150Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
1160Sstevel@tonic-gate 	uint_t mask;
117590Sesolom 	hrtime_t intrtime;
1183446Smrj 	hrtime_t now = tsc_read();
1190Sstevel@tonic-gate 
1200Sstevel@tonic-gate 	ASSERT(pil > LOCK_LEVEL);
1210Sstevel@tonic-gate 
1220Sstevel@tonic-gate 	if (pil == CBE_HIGH_PIL) {
1230Sstevel@tonic-gate 		cpu->cpu_profile_pil = oldpil;
1240Sstevel@tonic-gate 		if (USERMODE(rp->r_cs)) {
1250Sstevel@tonic-gate 			cpu->cpu_profile_pc = 0;
1260Sstevel@tonic-gate 			cpu->cpu_profile_upc = rp->r_pc;
1278803SJonathan.Haslam@Sun.COM 			cpu->cpu_cpcprofile_pc = 0;
1288803SJonathan.Haslam@Sun.COM 			cpu->cpu_cpcprofile_upc = rp->r_pc;
1290Sstevel@tonic-gate 		} else {
1300Sstevel@tonic-gate 			cpu->cpu_profile_pc = rp->r_pc;
1310Sstevel@tonic-gate 			cpu->cpu_profile_upc = 0;
1328803SJonathan.Haslam@Sun.COM 			cpu->cpu_cpcprofile_pc = rp->r_pc;
1338803SJonathan.Haslam@Sun.COM 			cpu->cpu_cpcprofile_upc = 0;
1340Sstevel@tonic-gate 		}
1350Sstevel@tonic-gate 	}
1360Sstevel@tonic-gate 
1370Sstevel@tonic-gate 	mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
1380Sstevel@tonic-gate 	if (mask != 0) {
1390Sstevel@tonic-gate 		int nestpil;
1400Sstevel@tonic-gate 
1410Sstevel@tonic-gate 		/*
1420Sstevel@tonic-gate 		 * We have interrupted another high-level interrupt.
1430Sstevel@tonic-gate 		 * Load starting timestamp, compute interval, update
1440Sstevel@tonic-gate 		 * cumulative counter.
1450Sstevel@tonic-gate 		 */
1460Sstevel@tonic-gate 		nestpil = bsrw_insn((uint16_t)mask);
1470Sstevel@tonic-gate 		ASSERT(nestpil < pil);
1483446Smrj 		intrtime = now -
1490Sstevel@tonic-gate 		    mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)];
150916Sschwartz 		mcpu->intrstat[nestpil][0] += intrtime;
151590Sesolom 		cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1520Sstevel@tonic-gate 		/*
1530Sstevel@tonic-gate 		 * Another high-level interrupt is active below this one, so
1540Sstevel@tonic-gate 		 * there is no need to check for an interrupt thread.  That
1550Sstevel@tonic-gate 		 * will be done by the lowest priority high-level interrupt
1560Sstevel@tonic-gate 		 * active.
1570Sstevel@tonic-gate 		 */
1580Sstevel@tonic-gate 	} else {
1590Sstevel@tonic-gate 		kthread_t *t = cpu->cpu_thread;
1600Sstevel@tonic-gate 
1610Sstevel@tonic-gate 		/*
1620Sstevel@tonic-gate 		 * See if we are interrupting a low-level interrupt thread.
1630Sstevel@tonic-gate 		 * If so, account for its time slice only if its time stamp
1640Sstevel@tonic-gate 		 * is non-zero.
1650Sstevel@tonic-gate 		 */
1660Sstevel@tonic-gate 		if ((t->t_flag & T_INTR_THREAD) != 0 && t->t_intr_start != 0) {
1673446Smrj 			intrtime = now - t->t_intr_start;
168916Sschwartz 			mcpu->intrstat[t->t_pil][0] += intrtime;
169590Sesolom 			cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
1700Sstevel@tonic-gate 			t->t_intr_start = 0;
1710Sstevel@tonic-gate 		}
1720Sstevel@tonic-gate 	}
1730Sstevel@tonic-gate 
1740Sstevel@tonic-gate 	/*
1750Sstevel@tonic-gate 	 * Store starting timestamp in CPU structure for this PIL.
1760Sstevel@tonic-gate 	 */
1773446Smrj 	mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
1780Sstevel@tonic-gate 
1790Sstevel@tonic-gate 	ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
1800Sstevel@tonic-gate 
1810Sstevel@tonic-gate 	if (pil == 15) {
1820Sstevel@tonic-gate 		/*
1830Sstevel@tonic-gate 		 * To support reentrant level 15 interrupts, we maintain a
1840Sstevel@tonic-gate 		 * recursion count in the top half of cpu_intr_actv.  Only
1850Sstevel@tonic-gate 		 * when this count hits zero do we clear the PIL 15 bit from
1860Sstevel@tonic-gate 		 * the lower half of cpu_intr_actv.
1870Sstevel@tonic-gate 		 */
1880Sstevel@tonic-gate 		uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
1890Sstevel@tonic-gate 		(*refcntp)++;
1900Sstevel@tonic-gate 	}
1910Sstevel@tonic-gate 
1920Sstevel@tonic-gate 	mask = cpu->cpu_intr_actv;
1930Sstevel@tonic-gate 
1940Sstevel@tonic-gate 	cpu->cpu_intr_actv |= (1 << pil);
1950Sstevel@tonic-gate 
1960Sstevel@tonic-gate 	return (mask & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
1970Sstevel@tonic-gate }
1980Sstevel@tonic-gate 
1990Sstevel@tonic-gate /*
2000Sstevel@tonic-gate  * Does most of the work of returning from a high level interrupt.
2010Sstevel@tonic-gate  *
2020Sstevel@tonic-gate  * Returns 0 if there are no more high level interrupts (in which
2030Sstevel@tonic-gate  * case we must switch back to the interrupted thread stack) or
2040Sstevel@tonic-gate  * non-zero if there are more (in which case we should stay on it).
2050Sstevel@tonic-gate  *
2060Sstevel@tonic-gate  * Called with interrupts masked
2070Sstevel@tonic-gate  */
2083446Smrj static int
hilevel_intr_epilog(struct cpu * cpu,uint_t pil,uint_t oldpil,uint_t vecnum)2090Sstevel@tonic-gate hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum)
2100Sstevel@tonic-gate {
2110Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
2120Sstevel@tonic-gate 	uint_t mask;
213590Sesolom 	hrtime_t intrtime;
2143446Smrj 	hrtime_t now = tsc_read();
2150Sstevel@tonic-gate 
2160Sstevel@tonic-gate 	ASSERT(mcpu->mcpu_pri == pil);
2170Sstevel@tonic-gate 
2180Sstevel@tonic-gate 	cpu->cpu_stats.sys.intr[pil - 1]++;
2190Sstevel@tonic-gate 
2200Sstevel@tonic-gate 	ASSERT(cpu->cpu_intr_actv & (1 << pil));
2210Sstevel@tonic-gate 
2220Sstevel@tonic-gate 	if (pil == 15) {
2230Sstevel@tonic-gate 		/*
2240Sstevel@tonic-gate 		 * To support reentrant level 15 interrupts, we maintain a
2250Sstevel@tonic-gate 		 * recursion count in the top half of cpu_intr_actv.  Only
2260Sstevel@tonic-gate 		 * when this count hits zero do we clear the PIL 15 bit from
2270Sstevel@tonic-gate 		 * the lower half of cpu_intr_actv.
2280Sstevel@tonic-gate 		 */
2290Sstevel@tonic-gate 		uint16_t *refcntp = (uint16_t *)&cpu->cpu_intr_actv + 1;
2300Sstevel@tonic-gate 
2310Sstevel@tonic-gate 		ASSERT(*refcntp > 0);
2320Sstevel@tonic-gate 
2330Sstevel@tonic-gate 		if (--(*refcntp) == 0)
2340Sstevel@tonic-gate 			cpu->cpu_intr_actv &= ~(1 << pil);
2350Sstevel@tonic-gate 	} else {
2360Sstevel@tonic-gate 		cpu->cpu_intr_actv &= ~(1 << pil);
2370Sstevel@tonic-gate 	}
2380Sstevel@tonic-gate 
2390Sstevel@tonic-gate 	ASSERT(mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] != 0);
2400Sstevel@tonic-gate 
2413446Smrj 	intrtime = now - mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)];
242916Sschwartz 	mcpu->intrstat[pil][0] += intrtime;
243590Sesolom 	cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
2440Sstevel@tonic-gate 
2450Sstevel@tonic-gate 	/*
2460Sstevel@tonic-gate 	 * Check for lower-pil nested high-level interrupt beneath
2470Sstevel@tonic-gate 	 * current one.  If so, place a starting timestamp in its
2480Sstevel@tonic-gate 	 * pil_high_start entry.
2490Sstevel@tonic-gate 	 */
2500Sstevel@tonic-gate 	mask = cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK;
2510Sstevel@tonic-gate 	if (mask != 0) {
2520Sstevel@tonic-gate 		int nestpil;
2530Sstevel@tonic-gate 
2540Sstevel@tonic-gate 		/*
2550Sstevel@tonic-gate 		 * find PIL of nested interrupt
2560Sstevel@tonic-gate 		 */
2570Sstevel@tonic-gate 		nestpil = bsrw_insn((uint16_t)mask);
2580Sstevel@tonic-gate 		ASSERT(nestpil < pil);
2593446Smrj 		mcpu->pil_high_start[nestpil - (LOCK_LEVEL + 1)] = now;
2600Sstevel@tonic-gate 		/*
2610Sstevel@tonic-gate 		 * (Another high-level interrupt is active below this one,
2620Sstevel@tonic-gate 		 * so there is no need to check for an interrupt
2630Sstevel@tonic-gate 		 * thread.  That will be done by the lowest priority
2640Sstevel@tonic-gate 		 * high-level interrupt active.)
2650Sstevel@tonic-gate 		 */
2660Sstevel@tonic-gate 	} else {
2670Sstevel@tonic-gate 		/*
2680Sstevel@tonic-gate 		 * Check to see if there is a low-level interrupt active.
2690Sstevel@tonic-gate 		 * If so, place a starting timestamp in the thread
2700Sstevel@tonic-gate 		 * structure.
2710Sstevel@tonic-gate 		 */
2720Sstevel@tonic-gate 		kthread_t *t = cpu->cpu_thread;
2730Sstevel@tonic-gate 
2740Sstevel@tonic-gate 		if (t->t_flag & T_INTR_THREAD)
2753446Smrj 			t->t_intr_start = now;
2760Sstevel@tonic-gate 	}
2770Sstevel@tonic-gate 
2780Sstevel@tonic-gate 	mcpu->mcpu_pri = oldpil;
2790Sstevel@tonic-gate 	(void) (*setlvlx)(oldpil, vecnum);
2800Sstevel@tonic-gate 
2810Sstevel@tonic-gate 	return (cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK);
2820Sstevel@tonic-gate }
2830Sstevel@tonic-gate 
2840Sstevel@tonic-gate /*
2850Sstevel@tonic-gate  * Set up the cpu, thread and interrupt thread structures for
2860Sstevel@tonic-gate  * executing an interrupt thread.  The new stack pointer of the
2870Sstevel@tonic-gate  * interrupt thread (which *must* be switched to) is returned.
2880Sstevel@tonic-gate  */
2893446Smrj static caddr_t
intr_thread_prolog(struct cpu * cpu,caddr_t stackptr,uint_t pil)2900Sstevel@tonic-gate intr_thread_prolog(struct cpu *cpu, caddr_t stackptr, uint_t pil)
2910Sstevel@tonic-gate {
2920Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
2930Sstevel@tonic-gate 	kthread_t *t, *volatile it;
2943446Smrj 	hrtime_t now = tsc_read();
2950Sstevel@tonic-gate 
2960Sstevel@tonic-gate 	ASSERT(pil > 0);
2970Sstevel@tonic-gate 	ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
2980Sstevel@tonic-gate 	cpu->cpu_intr_actv |= (1 << pil);
2990Sstevel@tonic-gate 
3000Sstevel@tonic-gate 	/*
3010Sstevel@tonic-gate 	 * Get set to run an interrupt thread.
3020Sstevel@tonic-gate 	 * There should always be an interrupt thread, since we
3030Sstevel@tonic-gate 	 * allocate one for each level on each CPU.
3040Sstevel@tonic-gate 	 *
305989Sesolom 	 * t_intr_start could be zero due to cpu_intr_swtch_enter.
3060Sstevel@tonic-gate 	 */
3070Sstevel@tonic-gate 	t = cpu->cpu_thread;
308989Sesolom 	if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
3093446Smrj 		hrtime_t intrtime = now - t->t_intr_start;
310916Sschwartz 		mcpu->intrstat[t->t_pil][0] += intrtime;
311590Sesolom 		cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
3120Sstevel@tonic-gate 		t->t_intr_start = 0;
3130Sstevel@tonic-gate 	}
3140Sstevel@tonic-gate 
3150Sstevel@tonic-gate 	ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
3160Sstevel@tonic-gate 
3170Sstevel@tonic-gate 	t->t_sp = (uintptr_t)stackptr;	/* mark stack in curthread for resume */
3180Sstevel@tonic-gate 
3190Sstevel@tonic-gate 	/*
3200Sstevel@tonic-gate 	 * unlink the interrupt thread off the cpu
321989Sesolom 	 *
322989Sesolom 	 * Note that the code in kcpc_overflow_intr -relies- on the
323989Sesolom 	 * ordering of events here - in particular that t->t_lwp of
324989Sesolom 	 * the interrupt thread is set to the pinned thread *before*
325989Sesolom 	 * curthread is changed.
3260Sstevel@tonic-gate 	 */
3270Sstevel@tonic-gate 	it = cpu->cpu_intr_thread;
3280Sstevel@tonic-gate 	cpu->cpu_intr_thread = it->t_link;
3290Sstevel@tonic-gate 	it->t_intr = t;
3300Sstevel@tonic-gate 	it->t_lwp = t->t_lwp;
3310Sstevel@tonic-gate 
3320Sstevel@tonic-gate 	/*
3330Sstevel@tonic-gate 	 * (threads on the interrupt thread free list could have state
3340Sstevel@tonic-gate 	 * preset to TS_ONPROC, but it helps in debugging if
3350Sstevel@tonic-gate 	 * they're TS_FREE.)
3360Sstevel@tonic-gate 	 */
3370Sstevel@tonic-gate 	it->t_state = TS_ONPROC;
3380Sstevel@tonic-gate 
3390Sstevel@tonic-gate 	cpu->cpu_thread = it;		/* new curthread on this cpu */
3400Sstevel@tonic-gate 	it->t_pil = (uchar_t)pil;
3410Sstevel@tonic-gate 	it->t_pri = intr_pri + (pri_t)pil;
3423446Smrj 	it->t_intr_start = now;
3430Sstevel@tonic-gate 
3440Sstevel@tonic-gate 	return (it->t_stk);
3450Sstevel@tonic-gate }
3460Sstevel@tonic-gate 
3470Sstevel@tonic-gate 
3480Sstevel@tonic-gate #ifdef DEBUG
3490Sstevel@tonic-gate int intr_thread_cnt;
3500Sstevel@tonic-gate #endif
3510Sstevel@tonic-gate 
3520Sstevel@tonic-gate /*
3530Sstevel@tonic-gate  * Called with interrupts disabled
3540Sstevel@tonic-gate  */
3553446Smrj static void
intr_thread_epilog(struct cpu * cpu,uint_t vec,uint_t oldpil)3560Sstevel@tonic-gate intr_thread_epilog(struct cpu *cpu, uint_t vec, uint_t oldpil)
3570Sstevel@tonic-gate {
3580Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
3590Sstevel@tonic-gate 	kthread_t *t;
3600Sstevel@tonic-gate 	kthread_t *it = cpu->cpu_thread;	/* curthread */
3610Sstevel@tonic-gate 	uint_t pil, basespl;
362590Sesolom 	hrtime_t intrtime;
3633446Smrj 	hrtime_t now = tsc_read();
3640Sstevel@tonic-gate 
3650Sstevel@tonic-gate 	pil = it->t_pil;
3660Sstevel@tonic-gate 	cpu->cpu_stats.sys.intr[pil - 1]++;
3670Sstevel@tonic-gate 
3680Sstevel@tonic-gate 	ASSERT(it->t_intr_start != 0);
3693446Smrj 	intrtime = now - it->t_intr_start;
370916Sschwartz 	mcpu->intrstat[pil][0] += intrtime;
371590Sesolom 	cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
3720Sstevel@tonic-gate 
3730Sstevel@tonic-gate 	ASSERT(cpu->cpu_intr_actv & (1 << pil));
3740Sstevel@tonic-gate 	cpu->cpu_intr_actv &= ~(1 << pil);
3750Sstevel@tonic-gate 
3760Sstevel@tonic-gate 	/*
3770Sstevel@tonic-gate 	 * If there is still an interrupted thread underneath this one
3780Sstevel@tonic-gate 	 * then the interrupt was never blocked and the return is
3790Sstevel@tonic-gate 	 * fairly simple.  Otherwise it isn't.
3800Sstevel@tonic-gate 	 */
3810Sstevel@tonic-gate 	if ((t = it->t_intr) == NULL) {
3820Sstevel@tonic-gate 		/*
3830Sstevel@tonic-gate 		 * The interrupted thread is no longer pinned underneath
3840Sstevel@tonic-gate 		 * the interrupt thread.  This means the interrupt must
3850Sstevel@tonic-gate 		 * have blocked, and the interrupted thread has been
3860Sstevel@tonic-gate 		 * unpinned, and has probably been running around the
3870Sstevel@tonic-gate 		 * system for a while.
3880Sstevel@tonic-gate 		 *
3890Sstevel@tonic-gate 		 * Since there is no longer a thread under this one, put
3900Sstevel@tonic-gate 		 * this interrupt thread back on the CPU's free list and
3910Sstevel@tonic-gate 		 * resume the idle thread which will dispatch the next
3920Sstevel@tonic-gate 		 * thread to run.
3930Sstevel@tonic-gate 		 */
3940Sstevel@tonic-gate #ifdef DEBUG
3950Sstevel@tonic-gate 		intr_thread_cnt++;
3960Sstevel@tonic-gate #endif
3970Sstevel@tonic-gate 		cpu->cpu_stats.sys.intrblk++;
3980Sstevel@tonic-gate 		/*
3990Sstevel@tonic-gate 		 * Set CPU's base SPL based on active interrupts bitmask
4000Sstevel@tonic-gate 		 */
4010Sstevel@tonic-gate 		set_base_spl();
4020Sstevel@tonic-gate 		basespl = cpu->cpu_base_spl;
4030Sstevel@tonic-gate 		mcpu->mcpu_pri = basespl;
4040Sstevel@tonic-gate 		(*setlvlx)(basespl, vec);
4050Sstevel@tonic-gate 		(void) splhigh();
4063446Smrj 		sti();
4070Sstevel@tonic-gate 		it->t_state = TS_FREE;
4080Sstevel@tonic-gate 		/*
4090Sstevel@tonic-gate 		 * Return interrupt thread to pool
4100Sstevel@tonic-gate 		 */
4110Sstevel@tonic-gate 		it->t_link = cpu->cpu_intr_thread;
4120Sstevel@tonic-gate 		cpu->cpu_intr_thread = it;
4130Sstevel@tonic-gate 		swtch();
4143446Smrj 		panic("intr_thread_epilog: swtch returned");
4150Sstevel@tonic-gate 		/*NOTREACHED*/
4160Sstevel@tonic-gate 	}
4170Sstevel@tonic-gate 
4180Sstevel@tonic-gate 	/*
4190Sstevel@tonic-gate 	 * Return interrupt thread to the pool
4200Sstevel@tonic-gate 	 */
4210Sstevel@tonic-gate 	it->t_link = cpu->cpu_intr_thread;
4220Sstevel@tonic-gate 	cpu->cpu_intr_thread = it;
4230Sstevel@tonic-gate 	it->t_state = TS_FREE;
4240Sstevel@tonic-gate 
4250Sstevel@tonic-gate 	basespl = cpu->cpu_base_spl;
4260Sstevel@tonic-gate 	pil = MAX(oldpil, basespl);
4270Sstevel@tonic-gate 	mcpu->mcpu_pri = pil;
4280Sstevel@tonic-gate 	(*setlvlx)(pil, vec);
4293446Smrj 	t->t_intr_start = now;
4300Sstevel@tonic-gate 	cpu->cpu_thread = t;
4310Sstevel@tonic-gate }
4320Sstevel@tonic-gate 
433916Sschwartz /*
4343446Smrj  * intr_get_time() is a resource for interrupt handlers to determine how
4353446Smrj  * much time has been spent handling the current interrupt. Such a function
4363446Smrj  * is needed because higher level interrupts can arrive during the
4373446Smrj  * processing of an interrupt.  intr_get_time() only returns time spent in the
4383446Smrj  * current interrupt handler.
4393446Smrj  *
4403446Smrj  * The caller must be calling from an interrupt handler running at a pil
4413446Smrj  * below or at lock level. Timings are not provided for high-level
4423446Smrj  * interrupts.
4433446Smrj  *
4443446Smrj  * The first time intr_get_time() is called while handling an interrupt,
4453446Smrj  * it returns the time since the interrupt handler was invoked. Subsequent
4463446Smrj  * calls will return the time since the prior call to intr_get_time(). Time
4475084Sjohnlev  * is returned as ticks. Use scalehrtimef() to convert ticks to nsec.
4483446Smrj  *
4493446Smrj  * Theory Of Intrstat[][]:
4503446Smrj  *
4513446Smrj  * uint64_t intrstat[pil][0..1] is an array indexed by pil level, with two
4523446Smrj  * uint64_ts per pil.
4533446Smrj  *
4543446Smrj  * intrstat[pil][0] is a cumulative count of the number of ticks spent
4553446Smrj  * handling all interrupts at the specified pil on this CPU. It is
4563446Smrj  * exported via kstats to the user.
4573446Smrj  *
4583446Smrj  * intrstat[pil][1] is always a count of ticks less than or equal to the
4593446Smrj  * value in [0]. The difference between [1] and [0] is the value returned
4603446Smrj  * by a call to intr_get_time(). At the start of interrupt processing,
4613446Smrj  * [0] and [1] will be equal (or nearly so). As the interrupt consumes
4623446Smrj  * time, [0] will increase, but [1] will remain the same. A call to
4633446Smrj  * intr_get_time() will return the difference, then update [1] to be the
4643446Smrj  * same as [0]. Future calls will return the time since the last call.
4653446Smrj  * Finally, when the interrupt completes, [1] is updated to the same as [0].
4663446Smrj  *
4673446Smrj  * Implementation:
4683446Smrj  *
4693446Smrj  * intr_get_time() works much like a higher level interrupt arriving. It
4703446Smrj  * "checkpoints" the timing information by incrementing intrstat[pil][0]
4713446Smrj  * to include elapsed running time, and by setting t_intr_start to rdtsc.
4723446Smrj  * It then sets the return value to intrstat[pil][0] - intrstat[pil][1],
4733446Smrj  * and updates intrstat[pil][1] to be the same as the new value of
4743446Smrj  * intrstat[pil][0].
4753446Smrj  *
4763446Smrj  * In the normal handling of interrupts, after an interrupt handler returns
4773446Smrj  * and the code in intr_thread() updates intrstat[pil][0], it then sets
4783446Smrj  * intrstat[pil][1] to the new value of intrstat[pil][0]. When [0] == [1],
4793446Smrj  * the timings are reset, i.e. intr_get_time() will return [0] - [1] which
4803446Smrj  * is 0.
4813446Smrj  *
4823446Smrj  * Whenever interrupts arrive on a CPU which is handling a lower pil
4833446Smrj  * interrupt, they update the lower pil's [0] to show time spent in the
4843446Smrj  * handler that they've interrupted. This results in a growing discrepancy
4853446Smrj  * between [0] and [1], which is returned the next time intr_get_time() is
4863446Smrj  * called. Time spent in the higher-pil interrupt will not be returned in
4873446Smrj  * the next intr_get_time() call from the original interrupt, because
4883446Smrj  * the higher-pil interrupt's time is accumulated in intrstat[higherpil][].
489916Sschwartz  */
490916Sschwartz uint64_t
intr_get_time(void)4913446Smrj intr_get_time(void)
492916Sschwartz {
4933446Smrj 	struct cpu *cpu;
4943446Smrj 	struct machcpu *mcpu;
4953446Smrj 	kthread_t *t;
496916Sschwartz 	uint64_t time, delta, ret;
4973446Smrj 	uint_t pil;
498916Sschwartz 
4993446Smrj 	cli();
5003446Smrj 	cpu = CPU;
5013446Smrj 	mcpu = &cpu->cpu_m;
5023446Smrj 	t = cpu->cpu_thread;
5033446Smrj 	pil = t->t_pil;
504916Sschwartz 	ASSERT((cpu->cpu_intr_actv & CPU_INTR_ACTV_HIGH_LEVEL_MASK) == 0);
505916Sschwartz 	ASSERT(t->t_flag & T_INTR_THREAD);
506916Sschwartz 	ASSERT(pil != 0);
507916Sschwartz 	ASSERT(t->t_intr_start != 0);
508916Sschwartz 
509916Sschwartz 	time = tsc_read();
510916Sschwartz 	delta = time - t->t_intr_start;
511916Sschwartz 	t->t_intr_start = time;
512916Sschwartz 
513916Sschwartz 	time = mcpu->intrstat[pil][0] + delta;
514916Sschwartz 	ret = time - mcpu->intrstat[pil][1];
515916Sschwartz 	mcpu->intrstat[pil][0] = time;
516916Sschwartz 	mcpu->intrstat[pil][1] = time;
5171887Sjhaslam 	cpu->cpu_intracct[cpu->cpu_mstate] += delta;
518916Sschwartz 
5193446Smrj 	sti();
520916Sschwartz 	return (ret);
521916Sschwartz }
522916Sschwartz 
5233446Smrj static caddr_t
dosoftint_prolog(struct cpu * cpu,caddr_t stackptr,uint32_t st_pending,uint_t oldpil)5240Sstevel@tonic-gate dosoftint_prolog(
5250Sstevel@tonic-gate 	struct cpu *cpu,
5260Sstevel@tonic-gate 	caddr_t stackptr,
5270Sstevel@tonic-gate 	uint32_t st_pending,
5280Sstevel@tonic-gate 	uint_t oldpil)
5290Sstevel@tonic-gate {
5300Sstevel@tonic-gate 	kthread_t *t, *volatile it;
5310Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
5320Sstevel@tonic-gate 	uint_t pil;
5333446Smrj 	hrtime_t now;
5340Sstevel@tonic-gate 
5350Sstevel@tonic-gate top:
5360Sstevel@tonic-gate 	ASSERT(st_pending == mcpu->mcpu_softinfo.st_pending);
5370Sstevel@tonic-gate 
5380Sstevel@tonic-gate 	pil = bsrw_insn((uint16_t)st_pending);
5390Sstevel@tonic-gate 	if (pil <= oldpil || pil <= cpu->cpu_base_spl)
5400Sstevel@tonic-gate 		return (0);
5410Sstevel@tonic-gate 
5420Sstevel@tonic-gate 	/*
5430Sstevel@tonic-gate 	 * XX64	Sigh.
5440Sstevel@tonic-gate 	 *
5450Sstevel@tonic-gate 	 * This is a transliteration of the i386 assembler code for
5460Sstevel@tonic-gate 	 * soft interrupts.  One question is "why does this need
5470Sstevel@tonic-gate 	 * to be atomic?"  One possible race is -other- processors
5480Sstevel@tonic-gate 	 * posting soft interrupts to us in set_pending() i.e. the
5490Sstevel@tonic-gate 	 * CPU might get preempted just after the address computation,
5500Sstevel@tonic-gate 	 * but just before the atomic transaction, so another CPU would
5510Sstevel@tonic-gate 	 * actually set the original CPU's st_pending bit.  However,
5520Sstevel@tonic-gate 	 * it looks like it would be simpler to disable preemption there.
5530Sstevel@tonic-gate 	 * Are there other races for which preemption control doesn't work?
5540Sstevel@tonic-gate 	 *
5550Sstevel@tonic-gate 	 * The i386 assembler version -also- checks to see if the bit
5560Sstevel@tonic-gate 	 * being cleared was actually set; if it wasn't, it rechecks
5570Sstevel@tonic-gate 	 * for more.  This seems a bit strange, as the only code that
5580Sstevel@tonic-gate 	 * ever clears the bit is -this- code running with interrupts
5590Sstevel@tonic-gate 	 * disabled on -this- CPU.  This code would probably be cheaper:
5600Sstevel@tonic-gate 	 *
5610Sstevel@tonic-gate 	 * atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending,
5620Sstevel@tonic-gate 	 *   ~(1 << pil));
5630Sstevel@tonic-gate 	 *
5640Sstevel@tonic-gate 	 * and t->t_preempt--/++ around set_pending() even cheaper,
5650Sstevel@tonic-gate 	 * but at this point, correctness is critical, so we slavishly
5660Sstevel@tonic-gate 	 * emulate the i386 port.
5670Sstevel@tonic-gate 	 */
5683446Smrj 	if (atomic_btr32((uint32_t *)
5693446Smrj 	    &mcpu->mcpu_softinfo.st_pending, pil) == 0) {
5700Sstevel@tonic-gate 		st_pending = mcpu->mcpu_softinfo.st_pending;
5710Sstevel@tonic-gate 		goto top;
5720Sstevel@tonic-gate 	}
5730Sstevel@tonic-gate 
5740Sstevel@tonic-gate 	mcpu->mcpu_pri = pil;
5750Sstevel@tonic-gate 	(*setspl)(pil);
5760Sstevel@tonic-gate 
5773446Smrj 	now = tsc_read();
5783446Smrj 
5790Sstevel@tonic-gate 	/*
5800Sstevel@tonic-gate 	 * Get set to run interrupt thread.
5810Sstevel@tonic-gate 	 * There should always be an interrupt thread since we
5820Sstevel@tonic-gate 	 * allocate one for each level on the CPU.
5830Sstevel@tonic-gate 	 */
5840Sstevel@tonic-gate 	it = cpu->cpu_intr_thread;
5850Sstevel@tonic-gate 	cpu->cpu_intr_thread = it->t_link;
5860Sstevel@tonic-gate 
587989Sesolom 	/* t_intr_start could be zero due to cpu_intr_swtch_enter. */
588989Sesolom 	t = cpu->cpu_thread;
589989Sesolom 	if ((t->t_flag & T_INTR_THREAD) && t->t_intr_start != 0) {
5903446Smrj 		hrtime_t intrtime = now - t->t_intr_start;
591989Sesolom 		mcpu->intrstat[pil][0] += intrtime;
592989Sesolom 		cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
593989Sesolom 		t->t_intr_start = 0;
594989Sesolom 	}
595989Sesolom 
5960Sstevel@tonic-gate 	/*
5970Sstevel@tonic-gate 	 * Note that the code in kcpc_overflow_intr -relies- on the
5980Sstevel@tonic-gate 	 * ordering of events here - in particular that t->t_lwp of
5990Sstevel@tonic-gate 	 * the interrupt thread is set to the pinned thread *before*
600989Sesolom 	 * curthread is changed.
6010Sstevel@tonic-gate 	 */
6020Sstevel@tonic-gate 	it->t_lwp = t->t_lwp;
6030Sstevel@tonic-gate 	it->t_state = TS_ONPROC;
6040Sstevel@tonic-gate 
6050Sstevel@tonic-gate 	/*
6060Sstevel@tonic-gate 	 * Push interrupted thread onto list from new thread.
6070Sstevel@tonic-gate 	 * Set the new thread as the current one.
6080Sstevel@tonic-gate 	 * Set interrupted thread's T_SP because if it is the idle thread,
6090Sstevel@tonic-gate 	 * resume() may use that stack between threads.
6100Sstevel@tonic-gate 	 */
6110Sstevel@tonic-gate 
6120Sstevel@tonic-gate 	ASSERT(SA((uintptr_t)stackptr) == (uintptr_t)stackptr);
6130Sstevel@tonic-gate 	t->t_sp = (uintptr_t)stackptr;
6140Sstevel@tonic-gate 
6150Sstevel@tonic-gate 	it->t_intr = t;
6160Sstevel@tonic-gate 	cpu->cpu_thread = it;
6170Sstevel@tonic-gate 
6180Sstevel@tonic-gate 	/*
6190Sstevel@tonic-gate 	 * Set bit for this pil in CPU's interrupt active bitmask.
6200Sstevel@tonic-gate 	 */
6210Sstevel@tonic-gate 	ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
6220Sstevel@tonic-gate 	cpu->cpu_intr_actv |= (1 << pil);
6230Sstevel@tonic-gate 
6240Sstevel@tonic-gate 	/*
6250Sstevel@tonic-gate 	 * Initialize thread priority level from intr_pri
6260Sstevel@tonic-gate 	 */
6270Sstevel@tonic-gate 	it->t_pil = (uchar_t)pil;
6280Sstevel@tonic-gate 	it->t_pri = (pri_t)pil + intr_pri;
6293446Smrj 	it->t_intr_start = now;
6300Sstevel@tonic-gate 
6310Sstevel@tonic-gate 	return (it->t_stk);
6320Sstevel@tonic-gate }
6330Sstevel@tonic-gate 
6343446Smrj static void
dosoftint_epilog(struct cpu * cpu,uint_t oldpil)6350Sstevel@tonic-gate dosoftint_epilog(struct cpu *cpu, uint_t oldpil)
6360Sstevel@tonic-gate {
6370Sstevel@tonic-gate 	struct machcpu *mcpu = &cpu->cpu_m;
6380Sstevel@tonic-gate 	kthread_t *t, *it;
6390Sstevel@tonic-gate 	uint_t pil, basespl;
640590Sesolom 	hrtime_t intrtime;
6413446Smrj 	hrtime_t now = tsc_read();
6420Sstevel@tonic-gate 
6430Sstevel@tonic-gate 	it = cpu->cpu_thread;
6440Sstevel@tonic-gate 	pil = it->t_pil;
6450Sstevel@tonic-gate 
6460Sstevel@tonic-gate 	cpu->cpu_stats.sys.intr[pil - 1]++;
6470Sstevel@tonic-gate 
6480Sstevel@tonic-gate 	ASSERT(cpu->cpu_intr_actv & (1 << pil));
6490Sstevel@tonic-gate 	cpu->cpu_intr_actv &= ~(1 << pil);
6503446Smrj 	intrtime = now - it->t_intr_start;
651916Sschwartz 	mcpu->intrstat[pil][0] += intrtime;
652590Sesolom 	cpu->cpu_intracct[cpu->cpu_mstate] += intrtime;
6530Sstevel@tonic-gate 
6540Sstevel@tonic-gate 	/*
6550Sstevel@tonic-gate 	 * If there is still an interrupted thread underneath this one
6560Sstevel@tonic-gate 	 * then the interrupt was never blocked and the return is
6570Sstevel@tonic-gate 	 * fairly simple.  Otherwise it isn't.
6580Sstevel@tonic-gate 	 */
6590Sstevel@tonic-gate 	if ((t = it->t_intr) == NULL) {
6600Sstevel@tonic-gate 		/*
6610Sstevel@tonic-gate 		 * Put thread back on the interrupt thread list.
6620Sstevel@tonic-gate 		 * This was an interrupt thread, so set CPU's base SPL.
6630Sstevel@tonic-gate 		 */
6640Sstevel@tonic-gate 		set_base_spl();
6650Sstevel@tonic-gate 		it->t_state = TS_FREE;
6660Sstevel@tonic-gate 		it->t_link = cpu->cpu_intr_thread;
6670Sstevel@tonic-gate 		cpu->cpu_intr_thread = it;
6680Sstevel@tonic-gate 		(void) splhigh();
6693446Smrj 		sti();
6700Sstevel@tonic-gate 		swtch();
6710Sstevel@tonic-gate 		/*NOTREACHED*/
6723446Smrj 		panic("dosoftint_epilog: swtch returned");
6730Sstevel@tonic-gate 	}
6740Sstevel@tonic-gate 	it->t_link = cpu->cpu_intr_thread;
6750Sstevel@tonic-gate 	cpu->cpu_intr_thread = it;
6760Sstevel@tonic-gate 	it->t_state = TS_FREE;
6770Sstevel@tonic-gate 	cpu->cpu_thread = t;
6780Sstevel@tonic-gate 	if (t->t_flag & T_INTR_THREAD)
6793446Smrj 		t->t_intr_start = now;
6800Sstevel@tonic-gate 	basespl = cpu->cpu_base_spl;
6810Sstevel@tonic-gate 	pil = MAX(oldpil, basespl);
6820Sstevel@tonic-gate 	mcpu->mcpu_pri = pil;
6830Sstevel@tonic-gate 	(*setspl)(pil);
6840Sstevel@tonic-gate }
6850Sstevel@tonic-gate 
6863446Smrj 
6870Sstevel@tonic-gate /*
6880Sstevel@tonic-gate  * Make the interrupted thread 'to' be runnable.
6890Sstevel@tonic-gate  *
6900Sstevel@tonic-gate  * Since t->t_sp has already been saved, t->t_pc is all
6910Sstevel@tonic-gate  * that needs to be set in this function.
6920Sstevel@tonic-gate  *
6930Sstevel@tonic-gate  * Returns the interrupt level of the interrupt thread.
6940Sstevel@tonic-gate  */
6950Sstevel@tonic-gate int
intr_passivate(kthread_t * it,kthread_t * t)6960Sstevel@tonic-gate intr_passivate(
6970Sstevel@tonic-gate 	kthread_t *it,		/* interrupt thread */
6980Sstevel@tonic-gate 	kthread_t *t)		/* interrupted thread */
6990Sstevel@tonic-gate {
7000Sstevel@tonic-gate 	extern void _sys_rtt();
7010Sstevel@tonic-gate 
7020Sstevel@tonic-gate 	ASSERT(it->t_flag & T_INTR_THREAD);
7030Sstevel@tonic-gate 	ASSERT(SA(t->t_sp) == t->t_sp);
7040Sstevel@tonic-gate 
7050Sstevel@tonic-gate 	t->t_pc = (uintptr_t)_sys_rtt;
7060Sstevel@tonic-gate 	return (it->t_pil);
7070Sstevel@tonic-gate }
7080Sstevel@tonic-gate 
7090Sstevel@tonic-gate /*
7100Sstevel@tonic-gate  * Create interrupt kstats for this CPU.
7110Sstevel@tonic-gate  */
7120Sstevel@tonic-gate void
cpu_create_intrstat(cpu_t * cp)7130Sstevel@tonic-gate cpu_create_intrstat(cpu_t *cp)
7140Sstevel@tonic-gate {
7150Sstevel@tonic-gate 	int		i;
7160Sstevel@tonic-gate 	kstat_t		*intr_ksp;
7170Sstevel@tonic-gate 	kstat_named_t	*knp;
7180Sstevel@tonic-gate 	char		name[KSTAT_STRLEN];
7190Sstevel@tonic-gate 	zoneid_t	zoneid;
7200Sstevel@tonic-gate 
7210Sstevel@tonic-gate 	ASSERT(MUTEX_HELD(&cpu_lock));
7220Sstevel@tonic-gate 
7230Sstevel@tonic-gate 	if (pool_pset_enabled())
7240Sstevel@tonic-gate 		zoneid = GLOBAL_ZONEID;
7250Sstevel@tonic-gate 	else
7260Sstevel@tonic-gate 		zoneid = ALL_ZONES;
7270Sstevel@tonic-gate 
7280Sstevel@tonic-gate 	intr_ksp = kstat_create_zone("cpu", cp->cpu_id, "intrstat", "misc",
7290Sstevel@tonic-gate 	    KSTAT_TYPE_NAMED, PIL_MAX * 2, NULL, zoneid);
7300Sstevel@tonic-gate 
7310Sstevel@tonic-gate 	/*
7320Sstevel@tonic-gate 	 * Initialize each PIL's named kstat
7330Sstevel@tonic-gate 	 */
7340Sstevel@tonic-gate 	if (intr_ksp != NULL) {
7350Sstevel@tonic-gate 		intr_ksp->ks_update = cpu_kstat_intrstat_update;
7360Sstevel@tonic-gate 		knp = (kstat_named_t *)intr_ksp->ks_data;
7370Sstevel@tonic-gate 		intr_ksp->ks_private = cp;
7380Sstevel@tonic-gate 		for (i = 0; i < PIL_MAX; i++) {
7390Sstevel@tonic-gate 			(void) snprintf(name, KSTAT_STRLEN, "level-%d-time",
7400Sstevel@tonic-gate 			    i + 1);
7410Sstevel@tonic-gate 			kstat_named_init(&knp[i * 2], name, KSTAT_DATA_UINT64);
7420Sstevel@tonic-gate 			(void) snprintf(name, KSTAT_STRLEN, "level-%d-count",
7430Sstevel@tonic-gate 			    i + 1);
7440Sstevel@tonic-gate 			kstat_named_init(&knp[(i * 2) + 1], name,
7450Sstevel@tonic-gate 			    KSTAT_DATA_UINT64);
7460Sstevel@tonic-gate 		}
7470Sstevel@tonic-gate 		kstat_install(intr_ksp);
7480Sstevel@tonic-gate 	}
7490Sstevel@tonic-gate }
7500Sstevel@tonic-gate 
7510Sstevel@tonic-gate /*
7520Sstevel@tonic-gate  * Delete interrupt kstats for this CPU.
7530Sstevel@tonic-gate  */
7540Sstevel@tonic-gate void
cpu_delete_intrstat(cpu_t * cp)7550Sstevel@tonic-gate cpu_delete_intrstat(cpu_t *cp)
7560Sstevel@tonic-gate {
7570Sstevel@tonic-gate 	kstat_delete_byname_zone("cpu", cp->cpu_id, "intrstat", ALL_ZONES);
7580Sstevel@tonic-gate }
7590Sstevel@tonic-gate 
7600Sstevel@tonic-gate /*
7610Sstevel@tonic-gate  * Convert interrupt statistics from CPU ticks to nanoseconds and
7620Sstevel@tonic-gate  * update kstat.
7630Sstevel@tonic-gate  */
7640Sstevel@tonic-gate int
cpu_kstat_intrstat_update(kstat_t * ksp,int rw)7650Sstevel@tonic-gate cpu_kstat_intrstat_update(kstat_t *ksp, int rw)
7660Sstevel@tonic-gate {
7670Sstevel@tonic-gate 	kstat_named_t	*knp = ksp->ks_data;
7680Sstevel@tonic-gate 	cpu_t		*cpup = (cpu_t *)ksp->ks_private;
7690Sstevel@tonic-gate 	int		i;
7700Sstevel@tonic-gate 	hrtime_t	hrt;
7710Sstevel@tonic-gate 
7720Sstevel@tonic-gate 	if (rw == KSTAT_WRITE)
7730Sstevel@tonic-gate 		return (EACCES);
7740Sstevel@tonic-gate 
7750Sstevel@tonic-gate 	for (i = 0; i < PIL_MAX; i++) {
776916Sschwartz 		hrt = (hrtime_t)cpup->cpu_m.intrstat[i + 1][0];
7775084Sjohnlev 		scalehrtimef(&hrt);
7780Sstevel@tonic-gate 		knp[i * 2].value.ui64 = (uint64_t)hrt;
7790Sstevel@tonic-gate 		knp[(i * 2) + 1].value.ui64 = cpup->cpu_stats.sys.intr[i];
7800Sstevel@tonic-gate 	}
7810Sstevel@tonic-gate 
7820Sstevel@tonic-gate 	return (0);
7830Sstevel@tonic-gate }
7840Sstevel@tonic-gate 
7850Sstevel@tonic-gate /*
7860Sstevel@tonic-gate  * An interrupt thread is ending a time slice, so compute the interval it
7870Sstevel@tonic-gate  * ran for and update the statistic for its PIL.
7880Sstevel@tonic-gate  */
7890Sstevel@tonic-gate void
cpu_intr_swtch_enter(kthread_id_t t)7900Sstevel@tonic-gate cpu_intr_swtch_enter(kthread_id_t t)
7910Sstevel@tonic-gate {
7920Sstevel@tonic-gate 	uint64_t	interval;
7930Sstevel@tonic-gate 	uint64_t	start;
794590Sesolom 	cpu_t		*cpu;
7950Sstevel@tonic-gate 
7960Sstevel@tonic-gate 	ASSERT((t->t_flag & T_INTR_THREAD) != 0);
7970Sstevel@tonic-gate 	ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
7980Sstevel@tonic-gate 
7990Sstevel@tonic-gate 	/*
8000Sstevel@tonic-gate 	 * We could be here with a zero timestamp. This could happen if:
8010Sstevel@tonic-gate 	 * an interrupt thread which no longer has a pinned thread underneath
8020Sstevel@tonic-gate 	 * it (i.e. it blocked at some point in its past) has finished running
8030Sstevel@tonic-gate 	 * its handler. intr_thread() updated the interrupt statistic for its
8040Sstevel@tonic-gate 	 * PIL and zeroed its timestamp. Since there was no pinned thread to
8050Sstevel@tonic-gate 	 * return to, swtch() gets called and we end up here.
806590Sesolom 	 *
807590Sesolom 	 * Note that we use atomic ops below (cas64 and atomic_add_64), which
808590Sesolom 	 * we don't use in the functions above, because we're not called
809590Sesolom 	 * with interrupts blocked, but the epilog/prolog functions are.
8100Sstevel@tonic-gate 	 */
8110Sstevel@tonic-gate 	if (t->t_intr_start) {
8120Sstevel@tonic-gate 		do {
8130Sstevel@tonic-gate 			start = t->t_intr_start;
8140Sstevel@tonic-gate 			interval = tsc_read() - start;
8150Sstevel@tonic-gate 		} while (cas64(&t->t_intr_start, start, 0) != start);
816590Sesolom 		cpu = CPU;
817916Sschwartz 		cpu->cpu_m.intrstat[t->t_pil][0] += interval;
818590Sesolom 
819590Sesolom 		atomic_add_64((uint64_t *)&cpu->cpu_intracct[cpu->cpu_mstate],
820590Sesolom 		    interval);
8210Sstevel@tonic-gate 	} else
8220Sstevel@tonic-gate 		ASSERT(t->t_intr == NULL);
8230Sstevel@tonic-gate }
8240Sstevel@tonic-gate 
8250Sstevel@tonic-gate /*
8260Sstevel@tonic-gate  * An interrupt thread is returning from swtch(). Place a starting timestamp
8270Sstevel@tonic-gate  * in its thread structure.
8280Sstevel@tonic-gate  */
8290Sstevel@tonic-gate void
cpu_intr_swtch_exit(kthread_id_t t)8300Sstevel@tonic-gate cpu_intr_swtch_exit(kthread_id_t t)
8310Sstevel@tonic-gate {
8320Sstevel@tonic-gate 	uint64_t ts;
8330Sstevel@tonic-gate 
8340Sstevel@tonic-gate 	ASSERT((t->t_flag & T_INTR_THREAD) != 0);
8350Sstevel@tonic-gate 	ASSERT(t->t_pil > 0 && t->t_pil <= LOCK_LEVEL);
8360Sstevel@tonic-gate 
8370Sstevel@tonic-gate 	do {
8380Sstevel@tonic-gate 		ts = t->t_intr_start;
8390Sstevel@tonic-gate 	} while (cas64(&t->t_intr_start, ts, tsc_read()) != ts);
8400Sstevel@tonic-gate }
8413446Smrj 
8423446Smrj /*
8433446Smrj  * Dispatch a hilevel interrupt (one above LOCK_LEVEL)
8443446Smrj  */
8453446Smrj /*ARGSUSED*/
8463446Smrj static void
dispatch_hilevel(uint_t vector,uint_t arg2)8473446Smrj dispatch_hilevel(uint_t vector, uint_t arg2)
8483446Smrj {
8493446Smrj 	sti();
8503446Smrj 	av_dispatch_autovect(vector);
8513446Smrj 	cli();
8523446Smrj }
8533446Smrj 
8543446Smrj /*
8553446Smrj  * Dispatch a soft interrupt
8563446Smrj  */
8573446Smrj /*ARGSUSED*/
8583446Smrj static void
dispatch_softint(uint_t oldpil,uint_t arg2)8593446Smrj dispatch_softint(uint_t oldpil, uint_t arg2)
8603446Smrj {
8613446Smrj 	struct cpu *cpu = CPU;
8623446Smrj 
8633446Smrj 	sti();
8643446Smrj 	av_dispatch_softvect((int)cpu->cpu_thread->t_pil);
8653446Smrj 	cli();
8663446Smrj 
8673446Smrj 	/*
8683446Smrj 	 * Must run softint_epilog() on the interrupt thread stack, since
8693446Smrj 	 * there may not be a return from it if the interrupt thread blocked.
8703446Smrj 	 */
8713446Smrj 	dosoftint_epilog(cpu, oldpil);
8723446Smrj }
8733446Smrj 
8743446Smrj /*
8753446Smrj  * Dispatch a normal interrupt
8763446Smrj  */
8773446Smrj static void
dispatch_hardint(uint_t vector,uint_t oldipl)8783446Smrj dispatch_hardint(uint_t vector, uint_t oldipl)
8793446Smrj {
8803446Smrj 	struct cpu *cpu = CPU;
8813446Smrj 
8823446Smrj 	sti();
8833446Smrj 	av_dispatch_autovect(vector);
8843446Smrj 	cli();
8853446Smrj 
8863446Smrj 	/*
8873446Smrj 	 * Must run intr_thread_epilog() on the interrupt thread stack, since
8883446Smrj 	 * there may not be a return from it if the interrupt thread blocked.
8893446Smrj 	 */
8903446Smrj 	intr_thread_epilog(cpu, vector, oldipl);
8913446Smrj }
8923446Smrj 
8933446Smrj /*
8943446Smrj  * Deliver any softints the current interrupt priority allows.
8953446Smrj  * Called with interrupts disabled.
8963446Smrj  */
8973446Smrj void
dosoftint(struct regs * regs)8983446Smrj dosoftint(struct regs *regs)
8993446Smrj {
9003446Smrj 	struct cpu *cpu = CPU;
9013446Smrj 	int oldipl;
9023446Smrj 	caddr_t newsp;
9033446Smrj 
9043446Smrj 	while (cpu->cpu_softinfo.st_pending) {
9053446Smrj 		oldipl = cpu->cpu_pri;
9063446Smrj 		newsp = dosoftint_prolog(cpu, (caddr_t)regs,
9075084Sjohnlev 		    cpu->cpu_softinfo.st_pending, oldipl);
9083446Smrj 		/*
9093446Smrj 		 * If returned stack pointer is NULL, priority is too high
9103446Smrj 		 * to run any of the pending softints now.
9113446Smrj 		 * Break out and they will be run later.
9123446Smrj 		 */
9133446Smrj 		if (newsp == NULL)
9143446Smrj 			break;
9153446Smrj 		switch_sp_and_call(newsp, dispatch_softint, oldipl, 0);
9163446Smrj 	}
9173446Smrj }
9183446Smrj 
9193446Smrj /*
9203446Smrj  * Interrupt service routine, called with interrupts disabled.
9213446Smrj  */
9223446Smrj /*ARGSUSED*/
9233446Smrj void
do_interrupt(struct regs * rp,trap_trace_rec_t * ttp)9243446Smrj do_interrupt(struct regs *rp, trap_trace_rec_t *ttp)
9253446Smrj {
9263446Smrj 	struct cpu *cpu = CPU;
9273446Smrj 	int newipl, oldipl = cpu->cpu_pri;
9283446Smrj 	uint_t vector;
9293446Smrj 	caddr_t newsp;
9303446Smrj 
9313446Smrj #ifdef TRAPTRACE
9323446Smrj 	ttp->ttr_marker = TT_INTERRUPT;
9333446Smrj 	ttp->ttr_ipl = 0xff;
9343446Smrj 	ttp->ttr_pri = oldipl;
9353446Smrj 	ttp->ttr_spl = cpu->cpu_base_spl;
9363446Smrj 	ttp->ttr_vector = 0xff;
9373446Smrj #endif	/* TRAPTRACE */
9383446Smrj 
9399637SRandy.Fishel@Sun.COM 	cpu_idle_exit(CPU_IDLE_CB_FLAG_INTR);
9404191Sjosephb 
94111330SFrank.Vanderlinden@Sun.COM 	++*(uint16_t *)&cpu->cpu_m.mcpu_istamp;
94211330SFrank.Vanderlinden@Sun.COM 
9434191Sjosephb 	/*
9443446Smrj 	 * If it's a softint go do it now.
9453446Smrj 	 */
9463446Smrj 	if (rp->r_trapno == T_SOFTINT) {
9473446Smrj 		dosoftint(rp);
9483446Smrj 		ASSERT(!interrupts_enabled());
9493446Smrj 		return;
9503446Smrj 	}
9513446Smrj 
9523446Smrj 	/*
9533446Smrj 	 * Raise the interrupt priority.
9543446Smrj 	 */
9553446Smrj 	newipl = (*setlvl)(oldipl, (int *)&rp->r_trapno);
9563446Smrj #ifdef TRAPTRACE
9573446Smrj 	ttp->ttr_ipl = newipl;
9583446Smrj #endif	/* TRAPTRACE */
9593446Smrj 
9603446Smrj 	/*
9613446Smrj 	 * Bail if it is a spurious interrupt
9623446Smrj 	 */
9633446Smrj 	if (newipl == -1)
9643446Smrj 		return;
9653446Smrj 	cpu->cpu_pri = newipl;
9663446Smrj 	vector = rp->r_trapno;
9673446Smrj #ifdef TRAPTRACE
9683446Smrj 	ttp->ttr_vector = vector;
9693446Smrj #endif	/* TRAPTRACE */
9703446Smrj 	if (newipl > LOCK_LEVEL) {
9713446Smrj 		/*
9723446Smrj 		 * High priority interrupts run on this cpu's interrupt stack.
9733446Smrj 		 */
9743446Smrj 		if (hilevel_intr_prolog(cpu, newipl, oldipl, rp) == 0) {
9753446Smrj 			newsp = cpu->cpu_intr_stack;
9763446Smrj 			switch_sp_and_call(newsp, dispatch_hilevel, vector, 0);
9773446Smrj 		} else { /* already on the interrupt stack */
9783446Smrj 			dispatch_hilevel(vector, 0);
9793446Smrj 		}
9803446Smrj 		(void) hilevel_intr_epilog(cpu, newipl, oldipl, vector);
9813446Smrj 	} else {
9823446Smrj 		/*
9833446Smrj 		 * Run this interrupt in a separate thread.
9843446Smrj 		 */
9853446Smrj 		newsp = intr_thread_prolog(cpu, (caddr_t)rp, newipl);
9863446Smrj 		switch_sp_and_call(newsp, dispatch_hardint, vector, oldipl);
9873446Smrj 	}
9883446Smrj 
98910175SStuart.Maybee@Sun.COM #if !defined(__xpv)
9903446Smrj 	/*
9913446Smrj 	 * Deliver any pending soft interrupts.
9923446Smrj 	 */
9933446Smrj 	if (cpu->cpu_softinfo.st_pending)
9943446Smrj 		dosoftint(rp);
99510175SStuart.Maybee@Sun.COM #endif	/* !__xpv */
9963446Smrj }
9973446Smrj 
99810175SStuart.Maybee@Sun.COM 
9993446Smrj /*
10003446Smrj  * Common tasks always done by _sys_rtt, called with interrupts disabled.
10013446Smrj  * Returns 1 if returning to userland, 0 if returning to system mode.
10023446Smrj  */
10033446Smrj int
sys_rtt_common(struct regs * rp)10043446Smrj sys_rtt_common(struct regs *rp)
10053446Smrj {
10063446Smrj 	kthread_t *tp;
10073446Smrj 	extern void mutex_exit_critical_start();
10083446Smrj 	extern long mutex_exit_critical_size;
10095834Spt157919 	extern void mutex_owner_running_critical_start();
10105834Spt157919 	extern long mutex_owner_running_critical_size;
10113446Smrj 
10123446Smrj loop:
10133446Smrj 
10143446Smrj 	/*
10153446Smrj 	 * Check if returning to user
10163446Smrj 	 */
10173446Smrj 	tp = CPU->cpu_thread;
10183446Smrj 	if (USERMODE(rp->r_cs)) {
10193446Smrj 		/*
10203446Smrj 		 * Check if AST pending.
10213446Smrj 		 */
10223446Smrj 		if (tp->t_astflag) {
10233446Smrj 			/*
10243446Smrj 			 * Let trap() handle the AST
10253446Smrj 			 */
10263446Smrj 			sti();
10273446Smrj 			rp->r_trapno = T_AST;
10283446Smrj 			trap(rp, (caddr_t)0, CPU->cpu_id);
10293446Smrj 			cli();
10303446Smrj 			goto loop;
10313446Smrj 		}
10323446Smrj 
10333446Smrj #if defined(__amd64)
10343446Smrj 		/*
10353446Smrj 		 * We are done if segment registers do not need updating.
10363446Smrj 		 */
10374503Ssudheer 		if (tp->t_lwp->lwp_pcb.pcb_rupdate == 0)
10383446Smrj 			return (1);
10393446Smrj 
10403446Smrj 		if (update_sregs(rp, tp->t_lwp)) {
10413446Smrj 			/*
10423446Smrj 			 * 1 or more of the selectors is bad.
10433446Smrj 			 * Deliver a SIGSEGV.
10443446Smrj 			 */
10453446Smrj 			proc_t *p = ttoproc(tp);
10463446Smrj 
10473446Smrj 			sti();
10483446Smrj 			mutex_enter(&p->p_lock);
10493446Smrj 			tp->t_lwp->lwp_cursig = SIGSEGV;
10503446Smrj 			mutex_exit(&p->p_lock);
10513446Smrj 			psig();
10523446Smrj 			tp->t_sig_check = 1;
10533446Smrj 			cli();
10543446Smrj 		}
10554503Ssudheer 		tp->t_lwp->lwp_pcb.pcb_rupdate = 0;
10563446Smrj 
10573446Smrj #endif	/* __amd64 */
10583446Smrj 		return (1);
10593446Smrj 	}
10603446Smrj 
10613446Smrj 	/*
10623446Smrj 	 * Here if we are returning to supervisor mode.
10633446Smrj 	 * Check for a kernel preemption request.
10643446Smrj 	 */
10653446Smrj 	if (CPU->cpu_kprunrun && (rp->r_ps & PS_IE)) {
10663446Smrj 
10673446Smrj 		/*
10683446Smrj 		 * Do nothing if already in kpreempt
10693446Smrj 		 */
10703446Smrj 		if (!tp->t_preempt_lk) {
10713446Smrj 			tp->t_preempt_lk = 1;
10723446Smrj 			sti();
10733446Smrj 			kpreempt(1); /* asynchronous kpreempt call */
10743446Smrj 			cli();
10753446Smrj 			tp->t_preempt_lk = 0;
10763446Smrj 		}
10773446Smrj 	}
10783446Smrj 
10793446Smrj 	/*
10803446Smrj 	 * If we interrupted the mutex_exit() critical region we must
10813446Smrj 	 * reset the PC back to the beginning to prevent missed wakeups
10823446Smrj 	 * See the comments in mutex_exit() for details.
10833446Smrj 	 */
10843446Smrj 	if ((uintptr_t)rp->r_pc - (uintptr_t)mutex_exit_critical_start <
10853446Smrj 	    mutex_exit_critical_size) {
10863446Smrj 		rp->r_pc = (greg_t)mutex_exit_critical_start;
10873446Smrj 	}
10885834Spt157919 
10895834Spt157919 	/*
10905834Spt157919 	 * If we interrupted the mutex_owner_running() critical region we
10915834Spt157919 	 * must reset the PC back to the beginning to prevent dereferencing
10925834Spt157919 	 * of a freed thread pointer. See the comments in mutex_owner_running
10935834Spt157919 	 * for details.
10945834Spt157919 	 */
10955834Spt157919 	if ((uintptr_t)rp->r_pc -
10965834Spt157919 	    (uintptr_t)mutex_owner_running_critical_start <
10975834Spt157919 	    mutex_owner_running_critical_size) {
10985834Spt157919 		rp->r_pc = (greg_t)mutex_owner_running_critical_start;
10995834Spt157919 	}
11005834Spt157919 
11013446Smrj 	return (0);
11023446Smrj }
11033446Smrj 
11043446Smrj void
send_dirint(int cpuid,int int_level)11053446Smrj send_dirint(int cpuid, int int_level)
11063446Smrj {
11073446Smrj 	(*send_dirintf)(cpuid, int_level);
11083446Smrj }
11093446Smrj 
111012683SJimmy.Vetayases@oracle.com #define	IS_FAKE_SOFTINT(flag, newpri)		\
111112683SJimmy.Vetayases@oracle.com 	(((flag) & PS_IE) &&				\
111212683SJimmy.Vetayases@oracle.com 	    (((*get_pending_spl)() > (newpri)) ||	\
111312683SJimmy.Vetayases@oracle.com 	    bsrw_insn((uint16_t)cpu->cpu_softinfo.st_pending) > (newpri)))
111412683SJimmy.Vetayases@oracle.com 
11153446Smrj /*
11163446Smrj  * do_splx routine, takes new ipl to set
11173446Smrj  * returns the old ipl.
11183446Smrj  * We are careful not to set priority lower than CPU->cpu_base_pri,
11193446Smrj  * even though it seems we're raising the priority, it could be set
11203446Smrj  * higher at any time by an interrupt routine, so we must block interrupts
11213446Smrj  * and look at CPU->cpu_base_pri
11223446Smrj  */
11233446Smrj int
do_splx(int newpri)11243446Smrj do_splx(int newpri)
11253446Smrj {
11263446Smrj 	ulong_t	flag;
11273446Smrj 	cpu_t	*cpu;
11283446Smrj 	int	curpri, basepri;
11293446Smrj 
11303446Smrj 	flag = intr_clear();
11313446Smrj 	cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
11323446Smrj 	curpri = cpu->cpu_m.mcpu_pri;
11333446Smrj 	basepri = cpu->cpu_base_spl;
11343446Smrj 	if (newpri < basepri)
11353446Smrj 		newpri = basepri;
11363446Smrj 	cpu->cpu_m.mcpu_pri = newpri;
11373446Smrj 	(*setspl)(newpri);
11383446Smrj 	/*
11393446Smrj 	 * If we are going to reenable interrupts see if new priority level
11403446Smrj 	 * allows pending softint delivery.
11413446Smrj 	 */
114212683SJimmy.Vetayases@oracle.com 	if (IS_FAKE_SOFTINT(flag, newpri))
11433446Smrj 		fakesoftint();
11443446Smrj 	ASSERT(!interrupts_enabled());
11453446Smrj 	intr_restore(flag);
11463446Smrj 	return (curpri);
11473446Smrj }
11483446Smrj 
11493446Smrj /*
11503446Smrj  * Common spl raise routine, takes new ipl to set
11513446Smrj  * returns the old ipl, will not lower ipl.
11523446Smrj  */
11533446Smrj int
splr(int newpri)11543446Smrj splr(int newpri)
11553446Smrj {
11563446Smrj 	ulong_t	flag;
11573446Smrj 	cpu_t	*cpu;
11583446Smrj 	int	curpri, basepri;
11593446Smrj 
11603446Smrj 	flag = intr_clear();
11613446Smrj 	cpu = CPU; /* ints are disabled, now safe to cache cpu ptr */
11623446Smrj 	curpri = cpu->cpu_m.mcpu_pri;
11633446Smrj 	/*
11643446Smrj 	 * Only do something if new priority is larger
11653446Smrj 	 */
11663446Smrj 	if (newpri > curpri) {
11673446Smrj 		basepri = cpu->cpu_base_spl;
11683446Smrj 		if (newpri < basepri)
11693446Smrj 			newpri = basepri;
11703446Smrj 		cpu->cpu_m.mcpu_pri = newpri;
11713446Smrj 		(*setspl)(newpri);
11723446Smrj 		/*
11733446Smrj 		 * See if new priority level allows pending softint delivery
11743446Smrj 		 */
117512683SJimmy.Vetayases@oracle.com 		if (IS_FAKE_SOFTINT(flag, newpri))
11763446Smrj 			fakesoftint();
11773446Smrj 	}
11783446Smrj 	intr_restore(flag);
11793446Smrj 	return (curpri);
11803446Smrj }
11813446Smrj 
11823446Smrj int
getpil(void)11833446Smrj getpil(void)
11843446Smrj {
11853446Smrj 	return (CPU->cpu_m.mcpu_pri);
11863446Smrj }
11873446Smrj 
11883446Smrj int
spl_xcall(void)118911389SAlexander.Kolbasov@Sun.COM spl_xcall(void)
119011389SAlexander.Kolbasov@Sun.COM {
119111389SAlexander.Kolbasov@Sun.COM 	return (splr(ipltospl(XCALL_PIL)));
119211389SAlexander.Kolbasov@Sun.COM }
119311389SAlexander.Kolbasov@Sun.COM 
119411389SAlexander.Kolbasov@Sun.COM int
interrupts_enabled(void)11953446Smrj interrupts_enabled(void)
11963446Smrj {
11973446Smrj 	ulong_t	flag;
11983446Smrj 
11993446Smrj 	flag = getflags();
12003446Smrj 	return ((flag & PS_IE) == PS_IE);
12013446Smrj }
12023446Smrj 
12033446Smrj #ifdef DEBUG
12043446Smrj void
assert_ints_enabled(void)12053446Smrj assert_ints_enabled(void)
12063446Smrj {
12073446Smrj 	ASSERT(!interrupts_unleashed || interrupts_enabled());
12083446Smrj }
12093446Smrj #endif	/* DEBUG */
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