xref: /onnv-gate/usr/src/uts/i86pc/io/ppm_plat.c (revision 4667:2cb417b1d90c)
1*4667Smh27603 /*
2*4667Smh27603  * CDDL HEADER START
3*4667Smh27603  *
4*4667Smh27603  * The contents of this file are subject to the terms of the
5*4667Smh27603  * Common Development and Distribution License (the "License").
6*4667Smh27603  * You may not use this file except in compliance with the License.
7*4667Smh27603  *
8*4667Smh27603  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*4667Smh27603  * or http://www.opensolaris.org/os/licensing.
10*4667Smh27603  * See the License for the specific language governing permissions
11*4667Smh27603  * and limitations under the License.
12*4667Smh27603  *
13*4667Smh27603  * When distributing Covered Code, include this CDDL HEADER in each
14*4667Smh27603  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*4667Smh27603  * If applicable, add the following below this CDDL HEADER, with the
16*4667Smh27603  * fields enclosed by brackets "[]" replaced with your own identifying
17*4667Smh27603  * information: Portions Copyright [yyyy] [name of copyright owner]
18*4667Smh27603  *
19*4667Smh27603  * CDDL HEADER END
20*4667Smh27603  */
21*4667Smh27603 /*
22*4667Smh27603  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23*4667Smh27603  * Use is subject to license terms.
24*4667Smh27603  */
25*4667Smh27603 
26*4667Smh27603 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27*4667Smh27603 
28*4667Smh27603 /*
29*4667Smh27603  * Platform Power Management master pseudo driver platform support.
30*4667Smh27603  */
31*4667Smh27603 
32*4667Smh27603 #include <sys/ddi.h>
33*4667Smh27603 #include <sys/sunddi.h>
34*4667Smh27603 #include <sys/ppmvar.h>
35*4667Smh27603 #include <sys/cpupm.h>
36*4667Smh27603 
37*4667Smh27603 static struct ppm_domit *
38*4667Smh27603 ppm_get_domit_by_model(int model)
39*4667Smh27603 {
40*4667Smh27603 	struct ppm_domit *domit_p;
41*4667Smh27603 	for (domit_p = ppm_domit_data; (domit_p->name &&
42*4667Smh27603 	    (domit_p->model != model));	domit_p++)
43*4667Smh27603 		;
44*4667Smh27603 	ASSERT(domit_p);
45*4667Smh27603 	return (domit_p);
46*4667Smh27603 }
47*4667Smh27603 
48*4667Smh27603 void
49*4667Smh27603 ppm_rebuild_cpu_domains(void)
50*4667Smh27603 {
51*4667Smh27603 	char *str = "ppm_rebuild_cpu_domains";
52*4667Smh27603 	cpupm_cpu_dependency_t *dep;
53*4667Smh27603 	cpupm_cpu_dependency_t *dep_next;
54*4667Smh27603 	cpupm_cpu_node_t *cpu_next;
55*4667Smh27603 	struct ppm_domit *domit_p;
56*4667Smh27603 	ppm_domain_t *domp_old;
57*4667Smh27603 	ppm_domain_t *domp;
58*4667Smh27603 	ppm_dev_t *devp;
59*4667Smh27603 	ppm_db_t *dbp;
60*4667Smh27603 
61*4667Smh27603 	/*
62*4667Smh27603 	 * Get the CPU domain data
63*4667Smh27603 	 */
64*4667Smh27603 	domit_p = ppm_get_domit_by_model(PPMD_CPU);
65*4667Smh27603 
66*4667Smh27603 	/*
67*4667Smh27603 	 * Find the CPU domain created from ppm.conf. It's only a
68*4667Smh27603 	 * temporary domain used to make sure that all CPUs are
69*4667Smh27603 	 * claimed. There should only be one such domain defined.
70*4667Smh27603 	 */
71*4667Smh27603 	for (domp = ppm_domain_p; (domp && (domp->model != PPMD_CPU));
72*4667Smh27603 	    domp = domp->next)
73*4667Smh27603 		;
74*4667Smh27603 	if (domp == NULL) {
75*4667Smh27603 		cmn_err(CE_WARN, "%s: ppm.conf does not define a CPU domain!",
76*4667Smh27603 		    str);
77*4667Smh27603 		return;
78*4667Smh27603 	}
79*4667Smh27603 	domp_old = domp;
80*4667Smh27603 	for (domp = domp->next; domp; domp = domp->next) {
81*4667Smh27603 		if (domp->model == PPMD_CPU) {
82*4667Smh27603 			cmn_err(CE_WARN, "%s: Multiple CPU domains defined "
83*4667Smh27603 			    "in ppm.conf!", str);
84*4667Smh27603 			return;
85*4667Smh27603 		}
86*4667Smh27603 	}
87*4667Smh27603 
88*4667Smh27603 	/*
89*4667Smh27603 	 * It is quite possible that the platform does not contain any
90*4667Smh27603 	 * power manageable CPUs. If so, devlist will be NULL.
91*4667Smh27603 	 */
92*4667Smh27603 	if (domp_old->devlist == NULL) {
93*4667Smh27603 		PPMD(D_CPU, ("%s: No CPUs claimed by ppm!\n", str));
94*4667Smh27603 		return;
95*4667Smh27603 	}
96*4667Smh27603 
97*4667Smh27603 	/*
98*4667Smh27603 	 * Get the CPU dependencies as determined by the CPU driver. If
99*4667Smh27603 	 * the CPU driver didn't create a valid set of dependencies, then
100*4667Smh27603 	 * default to all CPUs in one domain.
101*4667Smh27603 	 */
102*4667Smh27603 	dep = cpupm_get_cpu_dependencies();
103*4667Smh27603 	if (dep == NULL) {
104*4667Smh27603 		cmn_err(CE_WARN, "%s: Could not retrieve CPU dependency info!",
105*4667Smh27603 		    str);
106*4667Smh27603 		domp_old->dflags |= PPMD_CPU_READY;
107*4667Smh27603 		return;
108*4667Smh27603 	}
109*4667Smh27603 
110*4667Smh27603 	/*
111*4667Smh27603 	 * Build real CPU domains. OFFLINE the old one as we don't
112*4667Smh27603 	 * want it to be used when we're done.
113*4667Smh27603 	 */
114*4667Smh27603 	mutex_enter(&domp_old->lock);
115*4667Smh27603 	domp_old->dflags |= PPMD_OFFLINE;
116*4667Smh27603 	for (dep_next = dep; dep_next; dep_next = dep_next->cd_next) {
117*4667Smh27603 		domp = kmem_zalloc(sizeof (*domp), KM_SLEEP);
118*4667Smh27603 		domp->name =  kmem_zalloc(MAXNAMELEN, KM_SLEEP);
119*4667Smh27603 		(void) snprintf(domp->name, MAXNAMELEN, "acpi_cpu_domain_%d",
120*4667Smh27603 			dep_next->cd_dependency_id);
121*4667Smh27603 		mutex_init(&domp->lock, NULL, MUTEX_DRIVER, NULL);
122*4667Smh27603 		mutex_enter(&domp->lock);
123*4667Smh27603 		domp->dflags = domit_p->dflags | PPMD_CPU_READY;
124*4667Smh27603 		domp->pwr_cnt = 0;
125*4667Smh27603 		domp->propname = domp_old->propname;
126*4667Smh27603 		domp->model = domit_p->model;
127*4667Smh27603 		domp->status = domit_p->status;
128*4667Smh27603 
129*4667Smh27603 		/*
130*4667Smh27603 		 * Add devices to new domain. As a precaution,
131*4667Smh27603 		 * make sure that the device is currently owned by the
132*4667Smh27603 		 * ppm.conf defined CPU domain. Adding the device to the
133*4667Smh27603 		 * domain will result in the domain's "devlist" and "owned"
134*4667Smh27603 		 * lists being properly formed. It will also update the
135*4667Smh27603 		 * dip pointer to the device structure. We have to manually
136*4667Smh27603 		 * build the "conflist" for the domain. But conveniently, the
137*4667Smh27603 		 * "conflist" data is easily obtainable from the "devlist".
138*4667Smh27603 		 */
139*4667Smh27603 		for (cpu_next = dep_next->cd_cpu; cpu_next;
140*4667Smh27603 		    cpu_next = cpu_next->cn_next) {
141*4667Smh27603 			devp = PPM_GET_PRIVATE(cpu_next->cn_dip);
142*4667Smh27603 			ASSERT(devp && devp->domp == domp_old);
143*4667Smh27603 			devp = ppm_add_dev(cpu_next->cn_dip, domp);
144*4667Smh27603 			dbp = kmem_zalloc(sizeof (struct ppm_db), KM_SLEEP);
145*4667Smh27603 			dbp->name = kmem_zalloc((strlen(devp->path) + 1),
146*4667Smh27603 			    KM_SLEEP);
147*4667Smh27603 			(void) strcpy(dbp->name, devp->path);
148*4667Smh27603 			dbp->next = domp->conflist;
149*4667Smh27603 			domp->conflist = dbp;
150*4667Smh27603 		}
151*4667Smh27603 
152*4667Smh27603 		/*
153*4667Smh27603 		 * Note that we do not bother creating a "dc" list as there
154*4667Smh27603 		 * isn't one for x86 CPU power management. If this changes
155*4667Smh27603 		 * in the future some more work will need to be done to
156*4667Smh27603 		 * support it.
157*4667Smh27603 		 */
158*4667Smh27603 		ASSERT(domp_old->dc == NULL);
159*4667Smh27603 
160*4667Smh27603 		/*
161*4667Smh27603 		 * Add the domain to the live list.
162*4667Smh27603 		 */
163*4667Smh27603 		domp->next = ppm_domain_p;
164*4667Smh27603 		ppm_domain_p = domp;
165*4667Smh27603 
166*4667Smh27603 		mutex_exit(&domp->lock);
167*4667Smh27603 	}
168*4667Smh27603 	mutex_exit(&domp_old->lock);
169*4667Smh27603 	cpupm_free_cpu_dependencies();
170*4667Smh27603 }
171*4667Smh27603 
172*4667Smh27603 /*
173*4667Smh27603  * Used by ppm_redefine_topspeed() to set the highest power level of all CPUs
174*4667Smh27603  * in a domain.
175*4667Smh27603  */
176*4667Smh27603 void
177*4667Smh27603 ppm_set_topspeed(ppm_dev_t *cpup, int speed)
178*4667Smh27603 {
179*4667Smh27603 	for (cpup = cpup->domp->devlist; cpup != NULL; cpup = cpup->next)
180*4667Smh27603 		(*cpupm_set_topspeed)(cpup->dip, speed);
181*4667Smh27603 }
182*4667Smh27603 
183*4667Smh27603 /*
184*4667Smh27603  * Redefine the highest power level for all CPUs in a domain. This
185*4667Smh27603  * functionality is necessary because ACPI uses the _PPC to define
186*4667Smh27603  * a CPU's highest power level *and* allows the _PPC to be redefined
187*4667Smh27603  * dynamically. _PPC changes are communicated through _PPC change
188*4667Smh27603  * notifications caught by the CPU device driver.
189*4667Smh27603  */
190*4667Smh27603 void
191*4667Smh27603 ppm_redefine_topspeed(void *ctx)
192*4667Smh27603 {
193*4667Smh27603 	char *str = "ppm_redefine_topspeed";
194*4667Smh27603 	ppm_dev_t *cpup;
195*4667Smh27603 	ppm_dev_t *ncpup;
196*4667Smh27603 	int topspeed;
197*4667Smh27603 	int newspeed = -1;
198*4667Smh27603 
199*4667Smh27603 	cpup = PPM_GET_PRIVATE((dev_info_t *)ctx);
200*4667Smh27603 
201*4667Smh27603 	if (cpupm_get_topspeed == NULL || cpupm_set_topspeed == NULL) {
202*4667Smh27603 		cmn_err(CE_WARN, "%s: Cannot process request for instance %d "
203*4667Smh27603 		    "since cpupm interfaces are not initialized", str,
204*4667Smh27603 		    ddi_get_instance(cpup->dip));
205*4667Smh27603 		return;
206*4667Smh27603 	}
207*4667Smh27603 
208*4667Smh27603 	if (!(cpup->domp->dflags & PPMD_CPU_READY)) {
209*4667Smh27603 		PPMD(D_CPU, ("%s: instance %d received _PPC change "
210*4667Smh27603 		    "notification before PPMD_CPU_READY", str,
211*4667Smh27603 		    ddi_get_instance(cpup->dip)));
212*4667Smh27603 		return;
213*4667Smh27603 	}
214*4667Smh27603 
215*4667Smh27603 	/*
216*4667Smh27603 	 * Process each CPU in the domain.
217*4667Smh27603 	 */
218*4667Smh27603 	for (ncpup = cpup->domp->devlist; ncpup != NULL; ncpup = ncpup->next) {
219*4667Smh27603 		topspeed = (*cpupm_get_topspeed)(ncpup->dip);
220*4667Smh27603 		if (newspeed == -1 || topspeed < newspeed)
221*4667Smh27603 			newspeed = topspeed;
222*4667Smh27603 	}
223*4667Smh27603 
224*4667Smh27603 	ppm_set_topspeed(cpup, newspeed);
225*4667Smh27603 }
226*4667Smh27603 
227*4667Smh27603 /*
228*4667Smh27603  * Traverses all domains looking for CPU domains and for each CPU domain
229*4667Smh27603  * redefines the topspeed for that domain. The reason that this is necessary
230*4667Smh27603  * is that on x86 platforms ACPI allows the highest power level to be
231*4667Smh27603  * redefined dynamically. Once all CPU devices have been started it we
232*4667Smh27603  * need to go back and reinitialize the topspeeds (just in case it's changed).
233*4667Smh27603  */
234*4667Smh27603 void
235*4667Smh27603 ppm_init_topspeed(void)
236*4667Smh27603 {
237*4667Smh27603 	ppm_domain_t *domp;
238*4667Smh27603 	for (domp = ppm_domain_p; domp;	domp = domp->next) {
239*4667Smh27603 		if (domp->model != PPMD_CPU || !PPM_DOMAIN_UP(domp))
240*4667Smh27603 			continue;
241*4667Smh27603 		if (domp->devlist == NULL)
242*4667Smh27603 			continue;
243*4667Smh27603 		ppm_redefine_topspeed(domp->devlist->dip);
244*4667Smh27603 	}
245*4667Smh27603 }
246*4667Smh27603 
247*4667Smh27603 /*
248*4667Smh27603  * For x86 platforms CPU domains must be built dynamically at bootime.
249*4667Smh27603  * Until the domains have been built, refuse all power transition
250*4667Smh27603  * requests.
251*4667Smh27603  */
252*4667Smh27603 /* ARGSUSED */
253*4667Smh27603 boolean_t
254*4667Smh27603 ppm_manage_early_cpus(dev_info_t *dip, int new, int *result)
255*4667Smh27603 {
256*4667Smh27603 	ppm_dev_t *ppmd = PPM_GET_PRIVATE(dip);
257*4667Smh27603 
258*4667Smh27603 	if (!(ppmd->domp->dflags & PPMD_CPU_READY)) {
259*4667Smh27603 		PPMD(D_CPU, ("ppm_manage_early_cpus: attempt to manage CPU "
260*4667Smh27603 		    "before it was ready dip(0x%p)", (void *)dip));
261*4667Smh27603 		return (B_TRUE);
262*4667Smh27603 	}
263*4667Smh27603 	*result = DDI_FAILURE;
264*4667Smh27603 	return (B_FALSE);
265*4667Smh27603 }
266*4667Smh27603 
267*4667Smh27603 int
268*4667Smh27603 ppm_change_cpu_power(ppm_dev_t *ppmd, int newlevel)
269*4667Smh27603 {
270*4667Smh27603 #ifdef DEBUG
271*4667Smh27603 	char *str = "ppm_change_cpu_power";
272*4667Smh27603 #endif
273*4667Smh27603 	ppm_unit_t *unitp;
274*4667Smh27603 	ppm_domain_t *domp;
275*4667Smh27603 	ppm_dev_t *cpup;
276*4667Smh27603 	dev_info_t *dip;
277*4667Smh27603 	int oldlevel;
278*4667Smh27603 	int ret;
279*4667Smh27603 
280*4667Smh27603 	unitp = ddi_get_soft_state(ppm_statep, ppm_inst);
281*4667Smh27603 	ASSERT(unitp);
282*4667Smh27603 	domp = ppmd->domp;
283*4667Smh27603 	cpup = domp->devlist;
284*4667Smh27603 
285*4667Smh27603 	dip = cpup->dip;
286*4667Smh27603 	ASSERT(dip);
287*4667Smh27603 
288*4667Smh27603 	oldlevel = cpup->level;
289*4667Smh27603 
290*4667Smh27603 	PPMD(D_CPU, ("%s: old %d, new %d\n", str, oldlevel, newlevel))
291*4667Smh27603 
292*4667Smh27603 	if (newlevel == oldlevel)
293*4667Smh27603 		return (DDI_SUCCESS);
294*4667Smh27603 
295*4667Smh27603 	/* bring each cpu to next level */
296*4667Smh27603 	for (; cpup; cpup = cpup->next) {
297*4667Smh27603 		ret = pm_power(cpup->dip, 0, newlevel);
298*4667Smh27603 		PPMD(D_CPU, ("%s: \"%s\", changed to level %d, ret %d\n",
299*4667Smh27603 		    str, cpup->path, newlevel, ret))
300*4667Smh27603 		if (ret == DDI_SUCCESS) {
301*4667Smh27603 			cpup->level = newlevel;
302*4667Smh27603 			cpup->rplvl = PM_LEVEL_UNKNOWN;
303*4667Smh27603 			continue;
304*4667Smh27603 		}
305*4667Smh27603 
306*4667Smh27603 		/*
307*4667Smh27603 		 * If the driver was unable to lower cpu speed,
308*4667Smh27603 		 * the cpu probably got busy. Best to change
309*4667Smh27603 		 * speed back to normal.
310*4667Smh27603 		 */
311*4667Smh27603 		if (newlevel < oldlevel) {
312*4667Smh27603 			oldlevel = pm_get_normal_power(dip, 0);
313*4667Smh27603 			ret = ppm_revert_cpu_power(cpup, oldlevel);
314*4667Smh27603 		}
315*4667Smh27603 		return (ret);
316*4667Smh27603 	}
317*4667Smh27603 
318*4667Smh27603 	return (DDI_SUCCESS);
319*4667Smh27603 }
320