10Sstevel@tonic-gate /* 20Sstevel@tonic-gate * CDDL HEADER START 30Sstevel@tonic-gate * 40Sstevel@tonic-gate * The contents of this file are subject to the terms of the 52434Sanish * Common Development and Distribution License (the "License"). 62434Sanish * You may not use this file except in compliance with the License. 70Sstevel@tonic-gate * 80Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 100Sstevel@tonic-gate * See the License for the specific language governing permissions 110Sstevel@tonic-gate * and limitations under the License. 120Sstevel@tonic-gate * 130Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 140Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 160Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 170Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 180Sstevel@tonic-gate * 190Sstevel@tonic-gate * CDDL HEADER END 200Sstevel@tonic-gate */ 210Sstevel@tonic-gate /* 228772SDan.Mick@Sun.COM * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 230Sstevel@tonic-gate * Use is subject to license terms. 240Sstevel@tonic-gate */ 250Sstevel@tonic-gate 260Sstevel@tonic-gate #include <sys/types.h> 270Sstevel@tonic-gate #include <sys/mkdev.h> 28117Sschwartz #include <sys/stat.h> 290Sstevel@tonic-gate #include <sys/sunddi.h> 300Sstevel@tonic-gate #include <vm/seg_kmem.h> 310Sstevel@tonic-gate #include <sys/machparam.h> 32916Sschwartz #include <sys/sunndi.h> 330Sstevel@tonic-gate #include <sys/ontrap.h> 34916Sschwartz #include <sys/psm.h> 35881Sjohnny #include <sys/pcie.h> 360Sstevel@tonic-gate #include <sys/pci_cfgspace.h> 370Sstevel@tonic-gate #include <sys/pci_tools.h> 381083Sanish #include <io/pci/pci_tools_ext.h> 393446Smrj #include <sys/apic.h> 40916Sschwartz #include <io/pci/pci_var.h> 4110923SEvan.Yan@Sun.COM #include <sys/pci_impl.h> 420Sstevel@tonic-gate #include <sys/promif.h> 431083Sanish #include <sys/x86_archext.h> 442434Sanish #include <sys/cpuvar.h> 45*11245SZhijun.Fu@Sun.COM #include <sys/pci_cfgacc.h> 460Sstevel@tonic-gate 475084Sjohnlev #ifdef __xpv 485084Sjohnlev #include <sys/hypervisor.h> 495084Sjohnlev #endif 505084Sjohnlev 51777Sschwartz #define PCIEX_BDF_OFFSET_DELTA 4 52777Sschwartz #define PCIEX_REG_FUNC_SHIFT (PCI_REG_FUNC_SHIFT + PCIEX_BDF_OFFSET_DELTA) 53777Sschwartz #define PCIEX_REG_DEV_SHIFT (PCI_REG_DEV_SHIFT + PCIEX_BDF_OFFSET_DELTA) 54777Sschwartz #define PCIEX_REG_BUS_SHIFT (PCI_REG_BUS_SHIFT + PCIEX_BDF_OFFSET_DELTA) 55777Sschwartz 560Sstevel@tonic-gate #define SUCCESS 0 570Sstevel@tonic-gate 58*11245SZhijun.Fu@Sun.COM extern uint64_t mcfg_mem_base; 590Sstevel@tonic-gate int pcitool_debug = 0; 600Sstevel@tonic-gate 610Sstevel@tonic-gate /* 620Sstevel@tonic-gate * Offsets of BARS in config space. First entry of 0 means config space. 630Sstevel@tonic-gate * Entries here correlate to pcitool_bars_t enumerated type. 640Sstevel@tonic-gate */ 650Sstevel@tonic-gate static uint8_t pci_bars[] = { 660Sstevel@tonic-gate 0x0, 670Sstevel@tonic-gate PCI_CONF_BASE0, 680Sstevel@tonic-gate PCI_CONF_BASE1, 690Sstevel@tonic-gate PCI_CONF_BASE2, 700Sstevel@tonic-gate PCI_CONF_BASE3, 710Sstevel@tonic-gate PCI_CONF_BASE4, 720Sstevel@tonic-gate PCI_CONF_BASE5, 730Sstevel@tonic-gate PCI_CONF_ROM 740Sstevel@tonic-gate }; 750Sstevel@tonic-gate 76777Sschwartz /* Max offset allowed into config space for a particular device. */ 77777Sschwartz static uint64_t max_cfg_size = PCI_CONF_HDR_SIZE; 78777Sschwartz 790Sstevel@tonic-gate static uint64_t pcitool_swap_endian(uint64_t data, int size); 80*11245SZhijun.Fu@Sun.COM static int pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 81*11245SZhijun.Fu@Sun.COM boolean_t io_access); 82*11245SZhijun.Fu@Sun.COM static int pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag); 83*11245SZhijun.Fu@Sun.COM static int pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, 840Sstevel@tonic-gate boolean_t write_flag); 850Sstevel@tonic-gate static uint64_t pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages); 860Sstevel@tonic-gate static void pcitool_unmap(uint64_t virt_addr, size_t num_pages); 870Sstevel@tonic-gate 884397Sschwartz /* Extern declarations */ 89916Sschwartz extern int (*psm_intr_ops)(dev_info_t *, ddi_intr_handle_impl_t *, 90916Sschwartz psm_intr_op_t, int *); 91916Sschwartz 92117Sschwartz int 93777Sschwartz pcitool_init(dev_info_t *dip, boolean_t is_pciex) 94117Sschwartz { 95117Sschwartz int instance = ddi_get_instance(dip); 96117Sschwartz 97117Sschwartz /* Create pcitool nodes for register access and interrupt routing. */ 98117Sschwartz 99117Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_REG, S_IFCHR, 10010923SEvan.Yan@Sun.COM PCI_MINOR_NUM(instance, PCI_TOOL_REG_MINOR_NUM), 101117Sschwartz DDI_NT_REGACC, 0) != DDI_SUCCESS) { 102117Sschwartz return (DDI_FAILURE); 103117Sschwartz } 104117Sschwartz 105117Sschwartz if (ddi_create_minor_node(dip, PCI_MINOR_INTR, S_IFCHR, 10610923SEvan.Yan@Sun.COM PCI_MINOR_NUM(instance, PCI_TOOL_INTR_MINOR_NUM), 107117Sschwartz DDI_NT_INTRCTL, 0) != DDI_SUCCESS) { 108117Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 109117Sschwartz return (DDI_FAILURE); 110117Sschwartz } 111117Sschwartz 112777Sschwartz if (is_pciex) 113777Sschwartz max_cfg_size = PCIE_CONF_HDR_SIZE; 114777Sschwartz 115117Sschwartz return (DDI_SUCCESS); 116117Sschwartz } 117117Sschwartz 118117Sschwartz void 119117Sschwartz pcitool_uninit(dev_info_t *dip) 120117Sschwartz { 121117Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_INTR); 122117Sschwartz ddi_remove_minor_node(dip, PCI_MINOR_REG); 123117Sschwartz } 124117Sschwartz 125916Sschwartz /*ARGSUSED*/ 126916Sschwartz static int 127916Sschwartz pcitool_set_intr(dev_info_t *dip, void *arg, int mode) 128916Sschwartz { 129916Sschwartz ddi_intr_handle_impl_t info_hdl; 130916Sschwartz pcitool_intr_set_t iset; 131916Sschwartz uint32_t old_cpu; 132916Sschwartz int ret, result; 1334397Sschwartz size_t copyinout_size; 134916Sschwartz int rval = SUCCESS; 135916Sschwartz 1364397Sschwartz /* Version 1 of pcitool_intr_set_t doesn't have flags. */ 1374397Sschwartz copyinout_size = (size_t)&iset.flags - (size_t)&iset; 1384397Sschwartz 1394397Sschwartz if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 140916Sschwartz return (EFAULT); 141916Sschwartz 1424397Sschwartz switch (iset.user_version) { 1434397Sschwartz case PCITOOL_V1: 1444397Sschwartz break; 1454397Sschwartz 1464397Sschwartz case PCITOOL_V2: 1474397Sschwartz copyinout_size = sizeof (pcitool_intr_set_t); 1484397Sschwartz if (ddi_copyin(arg, &iset, copyinout_size, mode) != DDI_SUCCESS) 1494397Sschwartz return (EFAULT); 1504397Sschwartz break; 1514397Sschwartz 1524397Sschwartz default: 1534397Sschwartz iset.status = PCITOOL_OUT_OF_RANGE; 1544397Sschwartz rval = ENOTSUP; 1554397Sschwartz goto done_set_intr; 1564397Sschwartz } 1574397Sschwartz 15810053SEvan.Yan@Sun.COM if (iset.flags & PCITOOL_INTR_FLAG_SET_MSI) { 15910053SEvan.Yan@Sun.COM rval = ENOTSUP; 16010053SEvan.Yan@Sun.COM iset.status = PCITOOL_IO_ERROR; 16110053SEvan.Yan@Sun.COM goto done_set_intr; 16210053SEvan.Yan@Sun.COM } 16310053SEvan.Yan@Sun.COM 164916Sschwartz if (iset.ino > APIC_MAX_VECTOR) { 165916Sschwartz rval = EINVAL; 166916Sschwartz iset.status = PCITOOL_INVALID_INO; 167916Sschwartz goto done_set_intr; 168916Sschwartz } 169916Sschwartz 170916Sschwartz iset.status = PCITOOL_SUCCESS; 171916Sschwartz 172916Sschwartz if ((old_cpu = pci_get_cpu_from_vecirq(iset.ino, IS_VEC)) == -1) { 173916Sschwartz iset.status = PCITOOL_IO_ERROR; 174916Sschwartz rval = EINVAL; 175916Sschwartz goto done_set_intr; 176916Sschwartz } 177916Sschwartz 1784397Sschwartz 179916Sschwartz old_cpu &= ~PSMGI_CPU_USER_BOUND; 180916Sschwartz 181916Sschwartz /* 182916Sschwartz * For this locally-declared and used handle, ih_private will contain a 183916Sschwartz * CPU value, not an ihdl_plat_t as used for global interrupt handling. 184916Sschwartz */ 185916Sschwartz info_hdl.ih_vector = iset.ino; 186916Sschwartz info_hdl.ih_private = (void *)(uintptr_t)iset.cpu_id; 18710053SEvan.Yan@Sun.COM info_hdl.ih_flags = PSMGI_INTRBY_VEC; 1884397Sschwartz if (pcitool_debug) 1894397Sschwartz prom_printf("user version:%d, flags:0x%x\n", 1904397Sschwartz iset.user_version, iset.flags); 191916Sschwartz 1924397Sschwartz result = ENOTSUP; 1934397Sschwartz if ((iset.user_version >= PCITOOL_V2) && 19410053SEvan.Yan@Sun.COM (iset.flags & PCITOOL_INTR_FLAG_SET_GROUP)) { 1954397Sschwartz ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_GRP_SET_CPU, 1964397Sschwartz &result); 1974397Sschwartz } else { 1984397Sschwartz ret = (*psm_intr_ops)(NULL, &info_hdl, PSM_INTR_OP_SET_CPU, 1994397Sschwartz &result); 2004397Sschwartz } 2014397Sschwartz 202916Sschwartz if (ret != PSM_SUCCESS) { 203916Sschwartz switch (result) { 204916Sschwartz case EIO: /* Error making the change */ 205916Sschwartz rval = EIO; 206916Sschwartz iset.status = PCITOOL_IO_ERROR; 207916Sschwartz break; 208916Sschwartz case ENXIO: /* Couldn't convert vector to irq */ 209916Sschwartz rval = EINVAL; 210916Sschwartz iset.status = PCITOOL_INVALID_INO; 211916Sschwartz break; 212916Sschwartz case EINVAL: /* CPU out of range */ 213916Sschwartz rval = EINVAL; 214916Sschwartz iset.status = PCITOOL_INVALID_CPUID; 215916Sschwartz break; 2164397Sschwartz case ENOTSUP: /* Requested PSM intr ops missing */ 2174397Sschwartz rval = ENOTSUP; 2184397Sschwartz iset.status = PCITOOL_IO_ERROR; 2194397Sschwartz break; 220916Sschwartz } 221916Sschwartz } 222916Sschwartz 223916Sschwartz /* Return original CPU. */ 224916Sschwartz iset.cpu_id = old_cpu; 225916Sschwartz 226916Sschwartz done_set_intr: 2274397Sschwartz iset.drvr_version = PCITOOL_VERSION; 2284397Sschwartz if (ddi_copyout(&iset, arg, copyinout_size, mode) != DDI_SUCCESS) 229916Sschwartz rval = EFAULT; 230916Sschwartz return (rval); 231916Sschwartz } 232916Sschwartz 233916Sschwartz 234916Sschwartz /* It is assumed that dip != NULL */ 235916Sschwartz static void 236916Sschwartz pcitool_get_intr_dev_info(dev_info_t *dip, pcitool_intr_dev_t *devs) 237916Sschwartz { 238916Sschwartz (void) strncpy(devs->driver_name, 2399537SErwin.Tsaur@Sun.COM ddi_driver_name(dip), MAXMODCONFNAME-2); 2409537SErwin.Tsaur@Sun.COM devs->driver_name[MAXMODCONFNAME-1] = '\0'; 241916Sschwartz (void) ddi_pathname(dip, devs->path); 242916Sschwartz devs->dev_inst = ddi_get_instance(dip); 243916Sschwartz } 244916Sschwartz 245916Sschwartz static int 246916Sschwartz pcitool_get_intr(dev_info_t *dip, void *arg, int mode) 247916Sschwartz { 248916Sschwartz /* Array part isn't used here, but oh well... */ 249916Sschwartz pcitool_intr_get_t partial_iget; 250916Sschwartz pcitool_intr_get_t *iget = &partial_iget; 251916Sschwartz size_t iget_kmem_alloc_size = 0; 252916Sschwartz uint8_t num_devs_ret; 253916Sschwartz int copyout_rval; 254916Sschwartz int rval = SUCCESS; 255916Sschwartz int circ; 256916Sschwartz int i; 257916Sschwartz 258916Sschwartz ddi_intr_handle_impl_t info_hdl; 259916Sschwartz apic_get_intr_t intr_info; 260916Sschwartz 261916Sschwartz /* Read in just the header part, no array section. */ 262916Sschwartz if (ddi_copyin(arg, &partial_iget, PCITOOL_IGET_SIZE(0), mode) != 263916Sschwartz DDI_SUCCESS) 264916Sschwartz return (EFAULT); 265916Sschwartz 26610053SEvan.Yan@Sun.COM if (partial_iget.flags & PCITOOL_INTR_FLAG_GET_MSI) { 26710053SEvan.Yan@Sun.COM partial_iget.status = PCITOOL_IO_ERROR; 26810053SEvan.Yan@Sun.COM partial_iget.num_devs_ret = 0; 26910053SEvan.Yan@Sun.COM rval = ENOTSUP; 27010053SEvan.Yan@Sun.COM goto done_get_intr; 27110053SEvan.Yan@Sun.COM } 27210053SEvan.Yan@Sun.COM 273916Sschwartz /* Validate argument. */ 274916Sschwartz if (partial_iget.ino > APIC_MAX_VECTOR) { 275916Sschwartz partial_iget.status = PCITOOL_INVALID_INO; 276916Sschwartz partial_iget.num_devs_ret = 0; 277916Sschwartz rval = EINVAL; 278916Sschwartz goto done_get_intr; 279916Sschwartz } 280916Sschwartz 281916Sschwartz num_devs_ret = partial_iget.num_devs_ret; 282916Sschwartz intr_info.avgi_dip_list = NULL; 283916Sschwartz intr_info.avgi_req_flags = 284916Sschwartz PSMGI_REQ_CPUID | PSMGI_REQ_NUM_DEVS | PSMGI_INTRBY_VEC; 285916Sschwartz /* 286916Sschwartz * For this locally-declared and used handle, ih_private will contain a 287916Sschwartz * pointer to apic_get_intr_t, not an ihdl_plat_t as used for 288916Sschwartz * global interrupt handling. 289916Sschwartz */ 290916Sschwartz info_hdl.ih_private = &intr_info; 291916Sschwartz info_hdl.ih_vector = partial_iget.ino; 292916Sschwartz 293916Sschwartz /* Caller wants device information returned. */ 294916Sschwartz if (num_devs_ret > 0) { 295916Sschwartz 296916Sschwartz intr_info.avgi_req_flags |= PSMGI_REQ_GET_DEVS; 297916Sschwartz 298916Sschwartz /* 299916Sschwartz * Allocate room. 300916Sschwartz * If num_devs_ret == 0 iget remains pointing to partial_iget. 301916Sschwartz */ 302916Sschwartz iget_kmem_alloc_size = PCITOOL_IGET_SIZE(num_devs_ret); 303916Sschwartz iget = kmem_alloc(iget_kmem_alloc_size, KM_SLEEP); 304916Sschwartz 305916Sschwartz /* Read in whole structure to verify there's room. */ 306916Sschwartz if (ddi_copyin(arg, iget, iget_kmem_alloc_size, mode) != 307916Sschwartz SUCCESS) { 308916Sschwartz 309916Sschwartz /* Be consistent and just return EFAULT here. */ 310916Sschwartz kmem_free(iget, iget_kmem_alloc_size); 311916Sschwartz 312916Sschwartz return (EFAULT); 313916Sschwartz } 314916Sschwartz } 315916Sschwartz 316916Sschwartz bzero(iget, PCITOOL_IGET_SIZE(num_devs_ret)); 317916Sschwartz iget->ino = info_hdl.ih_vector; 318916Sschwartz 319916Sschwartz /* 320916Sschwartz * Lock device tree branch from the pci root nexus on down if info will 321916Sschwartz * be extracted from dips returned from the tree. 322916Sschwartz */ 323916Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 324916Sschwartz ndi_devi_enter(dip, &circ); 325916Sschwartz } 326916Sschwartz 327916Sschwartz /* Call psm_intr_ops(PSM_INTR_OP_GET_INTR) to get information. */ 328916Sschwartz if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 329916Sschwartz PSM_INTR_OP_GET_INTR, NULL)) != PSM_SUCCESS) { 330916Sschwartz iget->status = PCITOOL_IO_ERROR; 331916Sschwartz iget->num_devs_ret = 0; 332916Sschwartz rval = EINVAL; 333916Sschwartz goto done_get_intr; 334916Sschwartz } 335916Sschwartz 336916Sschwartz /* 337916Sschwartz * Fill in the pcitool_intr_get_t to be returned, 338916Sschwartz * with the CPU, num_devs_ret and num_devs. 339916Sschwartz */ 340916Sschwartz iget->cpu_id = intr_info.avgi_cpu_id & ~PSMGI_CPU_USER_BOUND; 341916Sschwartz 342916Sschwartz /* Number of devices returned by apic. */ 343916Sschwartz iget->num_devs = intr_info.avgi_num_devs; 344916Sschwartz 345916Sschwartz /* Device info was returned. */ 346916Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 347916Sschwartz 348916Sschwartz /* 349916Sschwartz * num devs returned is num devs ret by apic, 350916Sschwartz * space permitting. 351916Sschwartz */ 352916Sschwartz iget->num_devs_ret = min(num_devs_ret, intr_info.avgi_num_devs); 353916Sschwartz 354916Sschwartz /* 355916Sschwartz * Loop thru list of dips and extract driver, name and instance. 356916Sschwartz * Fill in the pcitool_intr_dev_t's with this info. 357916Sschwartz */ 358916Sschwartz for (i = 0; i < iget->num_devs_ret; i++) 359916Sschwartz pcitool_get_intr_dev_info(intr_info.avgi_dip_list[i], 360916Sschwartz &iget->dev[i]); 361916Sschwartz 362916Sschwartz /* Free kmem_alloc'ed memory of the apic_get_intr_t */ 363916Sschwartz kmem_free(intr_info.avgi_dip_list, 364916Sschwartz intr_info.avgi_num_devs * sizeof (dev_info_t *)); 365916Sschwartz } 366916Sschwartz 367916Sschwartz done_get_intr: 368916Sschwartz 369916Sschwartz if (intr_info.avgi_req_flags & PSMGI_REQ_GET_DEVS) { 370916Sschwartz ndi_devi_exit(dip, circ); 371916Sschwartz } 372916Sschwartz 3734397Sschwartz iget->drvr_version = PCITOOL_VERSION; 374916Sschwartz copyout_rval = ddi_copyout(iget, arg, 375916Sschwartz PCITOOL_IGET_SIZE(num_devs_ret), mode); 376916Sschwartz 377916Sschwartz if (iget_kmem_alloc_size > 0) 378916Sschwartz kmem_free(iget, iget_kmem_alloc_size); 379916Sschwartz 380916Sschwartz if (copyout_rval != DDI_SUCCESS) 381916Sschwartz rval = EFAULT; 382916Sschwartz 383916Sschwartz return (rval); 384916Sschwartz } 385916Sschwartz 3864397Sschwartz /*ARGSUSED*/ 3874397Sschwartz static int 3884397Sschwartz pcitool_intr_info(dev_info_t *dip, void *arg, int mode) 3894397Sschwartz { 3904397Sschwartz pcitool_intr_info_t intr_info; 3914397Sschwartz ddi_intr_handle_impl_t info_hdl; 3924397Sschwartz int rval = SUCCESS; 3934397Sschwartz 3944397Sschwartz /* If we need user_version, and to ret same user version as passed in */ 3954397Sschwartz if (ddi_copyin(arg, &intr_info, sizeof (pcitool_intr_info_t), mode) != 3964397Sschwartz DDI_SUCCESS) { 3974397Sschwartz if (pcitool_debug) 3984397Sschwartz prom_printf("Error reading arguments\n"); 3994397Sschwartz return (EFAULT); 4004397Sschwartz } 4014397Sschwartz 40210053SEvan.Yan@Sun.COM if (intr_info.flags & PCITOOL_INTR_FLAG_GET_MSI) 40310053SEvan.Yan@Sun.COM return (ENOTSUP); 40410053SEvan.Yan@Sun.COM 4054397Sschwartz /* For UPPC systems, psm_intr_ops has no entry for APIC_TYPE. */ 4064397Sschwartz if ((rval = (*psm_intr_ops)(NULL, &info_hdl, 4074397Sschwartz PSM_INTR_OP_APIC_TYPE, NULL)) != PSM_SUCCESS) { 4084397Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UPPC; 4094397Sschwartz intr_info.ctlr_version = 0; 4104397Sschwartz 4114397Sschwartz } else { 4124397Sschwartz intr_info.ctlr_version = (uint32_t)info_hdl.ih_ver; 4134397Sschwartz if (strcmp((char *)info_hdl.ih_private, 4144397Sschwartz APIC_PCPLUSMP_NAME) == 0) 4154397Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_PCPLUSMP; 4164397Sschwartz else 4174397Sschwartz intr_info.ctlr_type = PCITOOL_CTLR_TYPE_UNKNOWN; 4184397Sschwartz } 4194397Sschwartz 4204397Sschwartz intr_info.num_intr = APIC_MAX_VECTOR; 4214397Sschwartz intr_info.drvr_version = PCITOOL_VERSION; 4224397Sschwartz if (ddi_copyout(&intr_info, arg, sizeof (pcitool_intr_info_t), mode) != 4234397Sschwartz DDI_SUCCESS) { 4244397Sschwartz if (pcitool_debug) 4254397Sschwartz prom_printf("Error returning arguments.\n"); 4264397Sschwartz rval = EFAULT; 4274397Sschwartz } 4284397Sschwartz 4294397Sschwartz return (rval); 4304397Sschwartz } 4314397Sschwartz 4324397Sschwartz 433916Sschwartz 434916Sschwartz /* 435916Sschwartz * Main function for handling interrupt CPU binding requests and queries. 436916Sschwartz * Need to implement later 437916Sschwartz */ 438916Sschwartz int 439916Sschwartz pcitool_intr_admn(dev_info_t *dip, void *arg, int cmd, int mode) 440916Sschwartz { 441916Sschwartz int rval; 442916Sschwartz 443916Sschwartz switch (cmd) { 444916Sschwartz 445916Sschwartz /* Associate a new CPU with a given vector */ 446916Sschwartz case PCITOOL_DEVICE_SET_INTR: 447916Sschwartz rval = pcitool_set_intr(dip, arg, mode); 448916Sschwartz break; 449916Sschwartz 450916Sschwartz case PCITOOL_DEVICE_GET_INTR: 451916Sschwartz rval = pcitool_get_intr(dip, arg, mode); 452916Sschwartz break; 453916Sschwartz 4544397Sschwartz case PCITOOL_SYSTEM_INTR_INFO: 4554397Sschwartz rval = pcitool_intr_info(dip, arg, mode); 456916Sschwartz break; 457916Sschwartz 458916Sschwartz default: 459916Sschwartz rval = ENOTSUP; 460916Sschwartz } 461916Sschwartz 462916Sschwartz return (rval); 463916Sschwartz } 464916Sschwartz 4650Sstevel@tonic-gate /* 4660Sstevel@tonic-gate * Perform register accesses on the nexus device itself. 4670Sstevel@tonic-gate * No explicit PCI nexus device for X86, so not applicable. 4680Sstevel@tonic-gate */ 469916Sschwartz 4700Sstevel@tonic-gate /*ARGSUSED*/ 4710Sstevel@tonic-gate int 472777Sschwartz pcitool_bus_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 4730Sstevel@tonic-gate { 4740Sstevel@tonic-gate return (ENOTSUP); 4750Sstevel@tonic-gate } 4760Sstevel@tonic-gate 4770Sstevel@tonic-gate /* Swap endianness. */ 4780Sstevel@tonic-gate static uint64_t 4790Sstevel@tonic-gate pcitool_swap_endian(uint64_t data, int size) 4800Sstevel@tonic-gate { 4810Sstevel@tonic-gate typedef union { 4820Sstevel@tonic-gate uint64_t data64; 4830Sstevel@tonic-gate uint8_t data8[8]; 4840Sstevel@tonic-gate } data_split_t; 4850Sstevel@tonic-gate 4860Sstevel@tonic-gate data_split_t orig_data; 4870Sstevel@tonic-gate data_split_t returned_data; 4880Sstevel@tonic-gate int i; 4890Sstevel@tonic-gate 4900Sstevel@tonic-gate orig_data.data64 = data; 4910Sstevel@tonic-gate returned_data.data64 = 0; 4920Sstevel@tonic-gate 4930Sstevel@tonic-gate for (i = 0; i < size; i++) { 4940Sstevel@tonic-gate returned_data.data8[i] = orig_data.data8[size - 1 - i]; 4950Sstevel@tonic-gate } 4960Sstevel@tonic-gate 4970Sstevel@tonic-gate return (returned_data.data64); 4980Sstevel@tonic-gate } 4990Sstevel@tonic-gate 500777Sschwartz /* 501*11245SZhijun.Fu@Sun.COM * A note about ontrap handling: 502777Sschwartz * 503*11245SZhijun.Fu@Sun.COM * X86 systems on which this module was tested return FFs instead of bus errors 504*11245SZhijun.Fu@Sun.COM * when accessing devices with invalid addresses. Ontrap handling, which 505*11245SZhijun.Fu@Sun.COM * gracefully handles kernel bus errors, is installed anyway for I/O and mem 506*11245SZhijun.Fu@Sun.COM * space accessing (not for pci config space), in case future X86 platforms 507*11245SZhijun.Fu@Sun.COM * require it. 508777Sschwartz */ 509777Sschwartz 5100Sstevel@tonic-gate /* Access device. prg is modified. */ 5110Sstevel@tonic-gate static int 512*11245SZhijun.Fu@Sun.COM pcitool_cfg_access(pcitool_reg_t *prg, boolean_t write_flag, 513*11245SZhijun.Fu@Sun.COM boolean_t io_access) 5140Sstevel@tonic-gate { 5150Sstevel@tonic-gate int size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 5160Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 5170Sstevel@tonic-gate int rval = SUCCESS; 5180Sstevel@tonic-gate uint64_t local_data; 519*11245SZhijun.Fu@Sun.COM pci_cfgacc_req_t req; 520*11245SZhijun.Fu@Sun.COM uint32_t max_offset; 521*11245SZhijun.Fu@Sun.COM 522*11245SZhijun.Fu@Sun.COM if ((size <= 0) || (size > 8) || ((size & (size - 1)) != 0)) { 523*11245SZhijun.Fu@Sun.COM prg->status = PCITOOL_INVALID_SIZE; 524*11245SZhijun.Fu@Sun.COM return (ENOTSUP); 525*11245SZhijun.Fu@Sun.COM } 5260Sstevel@tonic-gate 5270Sstevel@tonic-gate /* 5288772SDan.Mick@Sun.COM * NOTE: there is no way to verify whether or not the address is 5298772SDan.Mick@Sun.COM * valid other than that it is within the maximum offset. The 530*11245SZhijun.Fu@Sun.COM * put functions return void and the get functions return -1 on error. 5310Sstevel@tonic-gate */ 5328772SDan.Mick@Sun.COM 533*11245SZhijun.Fu@Sun.COM if (io_access) 534*11245SZhijun.Fu@Sun.COM max_offset = 0xFF; 535*11245SZhijun.Fu@Sun.COM else 536*11245SZhijun.Fu@Sun.COM max_offset = 0xFFF; 537*11245SZhijun.Fu@Sun.COM if (prg->offset + size - 1 > max_offset) { 5388772SDan.Mick@Sun.COM prg->status = PCITOOL_INVALID_ADDRESS; 5398772SDan.Mick@Sun.COM return (ENOTSUP); 5408772SDan.Mick@Sun.COM } 5418772SDan.Mick@Sun.COM 5420Sstevel@tonic-gate prg->status = PCITOOL_SUCCESS; 5430Sstevel@tonic-gate 544*11245SZhijun.Fu@Sun.COM req.rcdip = NULL; 545*11245SZhijun.Fu@Sun.COM req.bdf = PCI_GETBDF(prg->bus_no, prg->dev_no, prg->func_no); 546*11245SZhijun.Fu@Sun.COM req.offset = prg->offset; 547*11245SZhijun.Fu@Sun.COM req.size = size; 548*11245SZhijun.Fu@Sun.COM req.write = write_flag; 549*11245SZhijun.Fu@Sun.COM req.ioacc = io_access; 5500Sstevel@tonic-gate if (write_flag) { 5510Sstevel@tonic-gate if (big_endian) { 5520Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 5530Sstevel@tonic-gate } else { 5540Sstevel@tonic-gate local_data = prg->data; 5550Sstevel@tonic-gate } 556*11245SZhijun.Fu@Sun.COM VAL64(&req) = local_data; 557*11245SZhijun.Fu@Sun.COM pci_cfgacc_acc(&req); 5580Sstevel@tonic-gate } else { 559*11245SZhijun.Fu@Sun.COM pci_cfgacc_acc(&req); 560*11245SZhijun.Fu@Sun.COM local_data = VAL64(&req); 561*11245SZhijun.Fu@Sun.COM if (big_endian) { 562*11245SZhijun.Fu@Sun.COM prg->data = 563*11245SZhijun.Fu@Sun.COM pcitool_swap_endian(local_data, size); 564*11245SZhijun.Fu@Sun.COM } else { 565*11245SZhijun.Fu@Sun.COM prg->data = local_data; 5660Sstevel@tonic-gate } 5670Sstevel@tonic-gate } 568*11245SZhijun.Fu@Sun.COM /* 569*11245SZhijun.Fu@Sun.COM * Check if legacy IO config access is used, in which case 570*11245SZhijun.Fu@Sun.COM * only first 256 bytes are valid. 571*11245SZhijun.Fu@Sun.COM */ 572*11245SZhijun.Fu@Sun.COM if (req.ioacc && (prg->offset + size - 1 > 0xFF)) { 573*11245SZhijun.Fu@Sun.COM prg->status = PCITOOL_INVALID_ADDRESS; 574*11245SZhijun.Fu@Sun.COM return (ENOTSUP); 575*11245SZhijun.Fu@Sun.COM } 576*11245SZhijun.Fu@Sun.COM 577*11245SZhijun.Fu@Sun.COM /* Set phys_addr only if MMIO is used */ 578*11245SZhijun.Fu@Sun.COM prg->phys_addr = 0; 579*11245SZhijun.Fu@Sun.COM if (!req.ioacc && mcfg_mem_base != 0) { 580*11245SZhijun.Fu@Sun.COM prg->phys_addr = mcfg_mem_base + prg->offset + 581*11245SZhijun.Fu@Sun.COM ((prg->bus_no << PCIEX_REG_BUS_SHIFT) | 582*11245SZhijun.Fu@Sun.COM (prg->dev_no << PCIEX_REG_DEV_SHIFT) | 583*11245SZhijun.Fu@Sun.COM (prg->func_no << PCIEX_REG_FUNC_SHIFT)); 584*11245SZhijun.Fu@Sun.COM } 585*11245SZhijun.Fu@Sun.COM 5860Sstevel@tonic-gate return (rval); 5870Sstevel@tonic-gate } 5880Sstevel@tonic-gate 5890Sstevel@tonic-gate static int 590*11245SZhijun.Fu@Sun.COM pcitool_io_access(pcitool_reg_t *prg, boolean_t write_flag) 5910Sstevel@tonic-gate { 5920Sstevel@tonic-gate int port = (int)prg->phys_addr; 5930Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 5940Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 5950Sstevel@tonic-gate int rval = SUCCESS; 5960Sstevel@tonic-gate on_trap_data_t otd; 5970Sstevel@tonic-gate uint64_t local_data; 5980Sstevel@tonic-gate 5990Sstevel@tonic-gate 6000Sstevel@tonic-gate /* 6010Sstevel@tonic-gate * on_trap works like setjmp. 6020Sstevel@tonic-gate * 6030Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 6040Sstevel@tonic-gate * 6050Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 6060Sstevel@tonic-gate */ 6070Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 6080Sstevel@tonic-gate no_trap(); 6090Sstevel@tonic-gate if (pcitool_debug) 6100Sstevel@tonic-gate prom_printf( 6114397Sschwartz "pcitool_io_access: on_trap caught an error...\n"); 6120Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 6130Sstevel@tonic-gate return (EFAULT); 6140Sstevel@tonic-gate } 6150Sstevel@tonic-gate 6160Sstevel@tonic-gate if (write_flag) { 6170Sstevel@tonic-gate 6180Sstevel@tonic-gate if (big_endian) { 6190Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 6200Sstevel@tonic-gate } else { 6210Sstevel@tonic-gate local_data = prg->data; 6220Sstevel@tonic-gate } 6230Sstevel@tonic-gate 6240Sstevel@tonic-gate if (pcitool_debug) 6250Sstevel@tonic-gate prom_printf("Writing %ld byte(s) to port 0x%x\n", 6260Sstevel@tonic-gate size, port); 6270Sstevel@tonic-gate 6280Sstevel@tonic-gate switch (size) { 6290Sstevel@tonic-gate case 1: 6300Sstevel@tonic-gate outb(port, (uint8_t)local_data); 6310Sstevel@tonic-gate break; 6320Sstevel@tonic-gate case 2: 6330Sstevel@tonic-gate outw(port, (uint16_t)local_data); 6340Sstevel@tonic-gate break; 6350Sstevel@tonic-gate case 4: 6360Sstevel@tonic-gate outl(port, (uint32_t)local_data); 6370Sstevel@tonic-gate break; 6380Sstevel@tonic-gate default: 6390Sstevel@tonic-gate rval = ENOTSUP; 6400Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 6410Sstevel@tonic-gate break; 6420Sstevel@tonic-gate } 6430Sstevel@tonic-gate } else { 6440Sstevel@tonic-gate if (pcitool_debug) 6450Sstevel@tonic-gate prom_printf("Reading %ld byte(s) from port 0x%x\n", 6460Sstevel@tonic-gate size, port); 6470Sstevel@tonic-gate 6480Sstevel@tonic-gate switch (size) { 6490Sstevel@tonic-gate case 1: 6500Sstevel@tonic-gate local_data = inb(port); 6510Sstevel@tonic-gate break; 6520Sstevel@tonic-gate case 2: 6530Sstevel@tonic-gate local_data = inw(port); 6540Sstevel@tonic-gate break; 6550Sstevel@tonic-gate case 4: 6560Sstevel@tonic-gate local_data = inl(port); 6570Sstevel@tonic-gate break; 6580Sstevel@tonic-gate default: 6590Sstevel@tonic-gate rval = ENOTSUP; 6600Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 6610Sstevel@tonic-gate break; 6620Sstevel@tonic-gate } 6630Sstevel@tonic-gate 6640Sstevel@tonic-gate if (rval == SUCCESS) { 6650Sstevel@tonic-gate if (big_endian) { 6660Sstevel@tonic-gate prg->data = 6670Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 6680Sstevel@tonic-gate } else { 6690Sstevel@tonic-gate prg->data = local_data; 6700Sstevel@tonic-gate } 6710Sstevel@tonic-gate } 6720Sstevel@tonic-gate } 6730Sstevel@tonic-gate 6740Sstevel@tonic-gate no_trap(); 6750Sstevel@tonic-gate return (rval); 6760Sstevel@tonic-gate } 6770Sstevel@tonic-gate 6780Sstevel@tonic-gate static int 679*11245SZhijun.Fu@Sun.COM pcitool_mem_access(pcitool_reg_t *prg, uint64_t virt_addr, boolean_t write_flag) 6800Sstevel@tonic-gate { 6810Sstevel@tonic-gate size_t size = PCITOOL_ACC_ATTR_SIZE(prg->acc_attr); 6820Sstevel@tonic-gate boolean_t big_endian = PCITOOL_ACC_IS_BIG_ENDIAN(prg->acc_attr); 6830Sstevel@tonic-gate int rval = DDI_SUCCESS; 6840Sstevel@tonic-gate on_trap_data_t otd; 6850Sstevel@tonic-gate uint64_t local_data; 6860Sstevel@tonic-gate 6870Sstevel@tonic-gate /* 6880Sstevel@tonic-gate * on_trap works like setjmp. 6890Sstevel@tonic-gate * 6900Sstevel@tonic-gate * A non-zero return here means on_trap has returned from an error. 6910Sstevel@tonic-gate * 6920Sstevel@tonic-gate * A zero return here means that on_trap has just returned from setup. 6930Sstevel@tonic-gate */ 6940Sstevel@tonic-gate if (on_trap(&otd, OT_DATA_ACCESS)) { 6950Sstevel@tonic-gate no_trap(); 6960Sstevel@tonic-gate if (pcitool_debug) 6970Sstevel@tonic-gate prom_printf( 6980Sstevel@tonic-gate "pcitool_mem_access: on_trap caught an error...\n"); 6990Sstevel@tonic-gate prg->status = PCITOOL_INVALID_ADDRESS; 7000Sstevel@tonic-gate return (EFAULT); 7010Sstevel@tonic-gate } 7020Sstevel@tonic-gate 7030Sstevel@tonic-gate if (write_flag) { 7040Sstevel@tonic-gate 7050Sstevel@tonic-gate if (big_endian) { 7060Sstevel@tonic-gate local_data = pcitool_swap_endian(prg->data, size); 7070Sstevel@tonic-gate } else { 7080Sstevel@tonic-gate local_data = prg->data; 7090Sstevel@tonic-gate } 7100Sstevel@tonic-gate 7110Sstevel@tonic-gate switch (size) { 7120Sstevel@tonic-gate case 1: 7130Sstevel@tonic-gate *((uint8_t *)(uintptr_t)virt_addr) = local_data; 7140Sstevel@tonic-gate break; 7150Sstevel@tonic-gate case 2: 7160Sstevel@tonic-gate *((uint16_t *)(uintptr_t)virt_addr) = local_data; 7170Sstevel@tonic-gate break; 7180Sstevel@tonic-gate case 4: 7190Sstevel@tonic-gate *((uint32_t *)(uintptr_t)virt_addr) = local_data; 7200Sstevel@tonic-gate break; 7210Sstevel@tonic-gate case 8: 7220Sstevel@tonic-gate *((uint64_t *)(uintptr_t)virt_addr) = local_data; 7230Sstevel@tonic-gate break; 7240Sstevel@tonic-gate default: 7250Sstevel@tonic-gate rval = ENOTSUP; 7260Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 7270Sstevel@tonic-gate break; 7280Sstevel@tonic-gate } 7290Sstevel@tonic-gate } else { 7300Sstevel@tonic-gate switch (size) { 7310Sstevel@tonic-gate case 1: 7320Sstevel@tonic-gate local_data = *((uint8_t *)(uintptr_t)virt_addr); 7330Sstevel@tonic-gate break; 7340Sstevel@tonic-gate case 2: 7350Sstevel@tonic-gate local_data = *((uint16_t *)(uintptr_t)virt_addr); 7360Sstevel@tonic-gate break; 7370Sstevel@tonic-gate case 4: 7380Sstevel@tonic-gate local_data = *((uint32_t *)(uintptr_t)virt_addr); 7390Sstevel@tonic-gate break; 7400Sstevel@tonic-gate case 8: 7410Sstevel@tonic-gate local_data = *((uint64_t *)(uintptr_t)virt_addr); 7420Sstevel@tonic-gate break; 7430Sstevel@tonic-gate default: 7440Sstevel@tonic-gate rval = ENOTSUP; 7450Sstevel@tonic-gate prg->status = PCITOOL_INVALID_SIZE; 7460Sstevel@tonic-gate break; 7470Sstevel@tonic-gate } 7480Sstevel@tonic-gate 7490Sstevel@tonic-gate if (rval == SUCCESS) { 7500Sstevel@tonic-gate if (big_endian) { 7510Sstevel@tonic-gate prg->data = 7520Sstevel@tonic-gate pcitool_swap_endian(local_data, size); 7530Sstevel@tonic-gate } else { 7540Sstevel@tonic-gate prg->data = local_data; 7550Sstevel@tonic-gate } 7560Sstevel@tonic-gate } 7570Sstevel@tonic-gate } 7580Sstevel@tonic-gate 7590Sstevel@tonic-gate no_trap(); 7600Sstevel@tonic-gate return (rval); 7610Sstevel@tonic-gate } 7620Sstevel@tonic-gate 7630Sstevel@tonic-gate /* 7640Sstevel@tonic-gate * Map up to 2 pages which contain the address we want to access. 7650Sstevel@tonic-gate * 7660Sstevel@tonic-gate * Mapping should span no more than 8 bytes. With X86 it is possible for an 7670Sstevel@tonic-gate * 8 byte value to start on a 4 byte boundary, so it can cross a page boundary. 7680Sstevel@tonic-gate * We'll never have to map more than two pages. 7690Sstevel@tonic-gate */ 7700Sstevel@tonic-gate 7710Sstevel@tonic-gate static uint64_t 7720Sstevel@tonic-gate pcitool_map(uint64_t phys_addr, size_t size, size_t *num_pages) 7730Sstevel@tonic-gate { 7740Sstevel@tonic-gate 7750Sstevel@tonic-gate uint64_t page_base = phys_addr & ~MMU_PAGEOFFSET; 7760Sstevel@tonic-gate uint64_t offset = phys_addr & MMU_PAGEOFFSET; 7770Sstevel@tonic-gate void *virt_base; 7780Sstevel@tonic-gate uint64_t returned_addr; 7793446Smrj pfn_t pfn; 7800Sstevel@tonic-gate 7810Sstevel@tonic-gate if (pcitool_debug) 7820Sstevel@tonic-gate prom_printf("pcitool_map: Called with PA:0x%p\n", 7837632SNick.Todd@Sun.COM (void *)(uintptr_t)phys_addr); 7840Sstevel@tonic-gate 7850Sstevel@tonic-gate *num_pages = 1; 7860Sstevel@tonic-gate 7870Sstevel@tonic-gate /* Desired mapping would span more than two pages. */ 7880Sstevel@tonic-gate if ((offset + size) > (MMU_PAGESIZE * 2)) { 7890Sstevel@tonic-gate if (pcitool_debug) 7900Sstevel@tonic-gate prom_printf("boundary violation: " 791777Sschwartz "offset:0x%" PRIx64 ", size:%ld, pagesize:0x%lx\n", 792777Sschwartz offset, (uintptr_t)size, (uintptr_t)MMU_PAGESIZE); 7930Sstevel@tonic-gate return (NULL); 7940Sstevel@tonic-gate 7950Sstevel@tonic-gate } else if ((offset + size) > MMU_PAGESIZE) { 7960Sstevel@tonic-gate (*num_pages)++; 7970Sstevel@tonic-gate } 7980Sstevel@tonic-gate 7990Sstevel@tonic-gate /* Get page(s) of virtual space. */ 8000Sstevel@tonic-gate virt_base = vmem_alloc(heap_arena, ptob(*num_pages), VM_NOSLEEP); 8010Sstevel@tonic-gate if (virt_base == NULL) { 8020Sstevel@tonic-gate if (pcitool_debug) 8030Sstevel@tonic-gate prom_printf("Couldn't get virtual base address.\n"); 8040Sstevel@tonic-gate return (NULL); 8050Sstevel@tonic-gate } 8060Sstevel@tonic-gate 8070Sstevel@tonic-gate if (pcitool_debug) 8080Sstevel@tonic-gate prom_printf("Got base virtual address:0x%p\n", virt_base); 8090Sstevel@tonic-gate 8105084Sjohnlev #ifdef __xpv 8115084Sjohnlev /* 8125084Sjohnlev * We should only get here if we are dom0. 8135084Sjohnlev * We're using a real device so we need to translate the MA to a PFN. 8145084Sjohnlev */ 8155084Sjohnlev ASSERT(DOMAIN_IS_INITDOMAIN(xen_info)); 8165084Sjohnlev pfn = xen_assign_pfn(mmu_btop(page_base)); 8175084Sjohnlev #else 8183446Smrj pfn = btop(page_base); 8195084Sjohnlev #endif 8203446Smrj 8210Sstevel@tonic-gate /* Now map the allocated virtual space to the physical address. */ 8223446Smrj hat_devload(kas.a_hat, virt_base, mmu_ptob(*num_pages), pfn, 8233446Smrj PROT_READ | PROT_WRITE | HAT_STRICTORDER, 8240Sstevel@tonic-gate HAT_LOAD_LOCK); 8250Sstevel@tonic-gate 8260Sstevel@tonic-gate returned_addr = ((uintptr_t)(virt_base)) + offset; 8270Sstevel@tonic-gate 8280Sstevel@tonic-gate if (pcitool_debug) 8290Sstevel@tonic-gate prom_printf("pcitool_map: returning VA:0x%p\n", 8300Sstevel@tonic-gate (void *)(uintptr_t)returned_addr); 8310Sstevel@tonic-gate 8320Sstevel@tonic-gate return (returned_addr); 8330Sstevel@tonic-gate } 8340Sstevel@tonic-gate 8350Sstevel@tonic-gate /* Unmap the mapped page(s). */ 8360Sstevel@tonic-gate static void 8370Sstevel@tonic-gate pcitool_unmap(uint64_t virt_addr, size_t num_pages) 8380Sstevel@tonic-gate { 8390Sstevel@tonic-gate void *base_virt_addr = (void *)(uintptr_t)(virt_addr & ~MMU_PAGEOFFSET); 8400Sstevel@tonic-gate 8410Sstevel@tonic-gate hat_unload(kas.a_hat, base_virt_addr, ptob(num_pages), 8420Sstevel@tonic-gate HAT_UNLOAD_UNLOCK); 8430Sstevel@tonic-gate vmem_free(heap_arena, base_virt_addr, ptob(num_pages)); 8440Sstevel@tonic-gate } 8450Sstevel@tonic-gate 8460Sstevel@tonic-gate 8470Sstevel@tonic-gate /* Perform register accesses on PCI leaf devices. */ 848*11245SZhijun.Fu@Sun.COM /*ARGSUSED*/ 8490Sstevel@tonic-gate int 850777Sschwartz pcitool_dev_reg_ops(dev_info_t *dip, void *arg, int cmd, int mode) 8510Sstevel@tonic-gate { 8520Sstevel@tonic-gate boolean_t write_flag = B_FALSE; 853*11245SZhijun.Fu@Sun.COM boolean_t io_access = B_TRUE; 8540Sstevel@tonic-gate int rval = 0; 8550Sstevel@tonic-gate pcitool_reg_t prg; 8560Sstevel@tonic-gate uint8_t size; 8570Sstevel@tonic-gate 8580Sstevel@tonic-gate uint64_t base_addr; 8590Sstevel@tonic-gate uint64_t virt_addr; 8600Sstevel@tonic-gate size_t num_virt_pages; 8610Sstevel@tonic-gate 8620Sstevel@tonic-gate switch (cmd) { 8630Sstevel@tonic-gate case (PCITOOL_DEVICE_SET_REG): 8640Sstevel@tonic-gate write_flag = B_TRUE; 8650Sstevel@tonic-gate 8660Sstevel@tonic-gate /*FALLTHRU*/ 8670Sstevel@tonic-gate case (PCITOOL_DEVICE_GET_REG): 8680Sstevel@tonic-gate if (pcitool_debug) 8690Sstevel@tonic-gate prom_printf("pci_dev_reg_ops set/get reg\n"); 8700Sstevel@tonic-gate if (ddi_copyin(arg, &prg, sizeof (pcitool_reg_t), mode) != 8710Sstevel@tonic-gate DDI_SUCCESS) { 8720Sstevel@tonic-gate if (pcitool_debug) 8730Sstevel@tonic-gate prom_printf("Error reading arguments\n"); 8740Sstevel@tonic-gate return (EFAULT); 8750Sstevel@tonic-gate } 8760Sstevel@tonic-gate 8770Sstevel@tonic-gate if (prg.barnum >= (sizeof (pci_bars) / sizeof (pci_bars[0]))) { 8780Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 8790Sstevel@tonic-gate rval = EINVAL; 8800Sstevel@tonic-gate goto done_reg; 8810Sstevel@tonic-gate } 8820Sstevel@tonic-gate 8830Sstevel@tonic-gate if (pcitool_debug) 8840Sstevel@tonic-gate prom_printf("raw bus:0x%x, dev:0x%x, func:0x%x\n", 8850Sstevel@tonic-gate prg.bus_no, prg.dev_no, prg.func_no); 8860Sstevel@tonic-gate /* Validate address arguments of bus / dev / func */ 8870Sstevel@tonic-gate if (((prg.bus_no & 8880Sstevel@tonic-gate (PCI_REG_BUS_M >> PCI_REG_BUS_SHIFT)) != 8890Sstevel@tonic-gate prg.bus_no) || 8900Sstevel@tonic-gate ((prg.dev_no & 8910Sstevel@tonic-gate (PCI_REG_DEV_M >> PCI_REG_DEV_SHIFT)) != 8920Sstevel@tonic-gate prg.dev_no) || 8930Sstevel@tonic-gate ((prg.func_no & 8940Sstevel@tonic-gate (PCI_REG_FUNC_M >> PCI_REG_FUNC_SHIFT)) != 8950Sstevel@tonic-gate prg.func_no)) { 8960Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 8970Sstevel@tonic-gate rval = EINVAL; 8980Sstevel@tonic-gate goto done_reg; 8990Sstevel@tonic-gate } 9000Sstevel@tonic-gate 9010Sstevel@tonic-gate size = PCITOOL_ACC_ATTR_SIZE(prg.acc_attr); 9020Sstevel@tonic-gate 9030Sstevel@tonic-gate /* Proper config space desired. */ 9040Sstevel@tonic-gate if (prg.barnum == 0) { 9050Sstevel@tonic-gate 906777Sschwartz if (pcitool_debug) 907777Sschwartz prom_printf( 908777Sschwartz "config access: offset:0x%" PRIx64 ", " 909777Sschwartz "phys_addr:0x%" PRIx64 "\n", 910777Sschwartz prg.offset, prg.phys_addr); 911777Sschwartz 912777Sschwartz if (prg.offset >= max_cfg_size) { 9130Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 9140Sstevel@tonic-gate rval = EINVAL; 9150Sstevel@tonic-gate goto done_reg; 9160Sstevel@tonic-gate } 917*11245SZhijun.Fu@Sun.COM if (max_cfg_size == PCIE_CONF_HDR_SIZE) 918*11245SZhijun.Fu@Sun.COM io_access = B_FALSE; 9190Sstevel@tonic-gate 920*11245SZhijun.Fu@Sun.COM rval = pcitool_cfg_access(&prg, write_flag, io_access); 9210Sstevel@tonic-gate if (pcitool_debug) 9220Sstevel@tonic-gate prom_printf( 9230Sstevel@tonic-gate "config access: data:0x%" PRIx64 "\n", 9240Sstevel@tonic-gate prg.data); 9250Sstevel@tonic-gate 9260Sstevel@tonic-gate /* IO/ MEM/ MEM64 space. */ 9270Sstevel@tonic-gate } else { 9280Sstevel@tonic-gate 9290Sstevel@tonic-gate pcitool_reg_t prg2; 9300Sstevel@tonic-gate bcopy(&prg, &prg2, sizeof (pcitool_reg_t)); 9310Sstevel@tonic-gate 9320Sstevel@tonic-gate /* 9330Sstevel@tonic-gate * Translate BAR number into offset of the BAR in 9340Sstevel@tonic-gate * the device's config space. 9350Sstevel@tonic-gate */ 9360Sstevel@tonic-gate prg2.offset = pci_bars[prg2.barnum]; 9370Sstevel@tonic-gate prg2.acc_attr = 9380Sstevel@tonic-gate PCITOOL_ACC_ATTR_SIZE_4 | PCITOOL_ACC_ATTR_ENDN_LTL; 9390Sstevel@tonic-gate 9400Sstevel@tonic-gate if (pcitool_debug) 9410Sstevel@tonic-gate prom_printf( 9420Sstevel@tonic-gate "barnum:%d, bar_offset:0x%" PRIx64 "\n", 9430Sstevel@tonic-gate prg2.barnum, prg2.offset); 9440Sstevel@tonic-gate /* 9450Sstevel@tonic-gate * Get Bus Address Register (BAR) from config space. 9460Sstevel@tonic-gate * prg2.offset is the offset into config space of the 9470Sstevel@tonic-gate * BAR desired. prg.status is modified on error. 9480Sstevel@tonic-gate */ 949*11245SZhijun.Fu@Sun.COM rval = pcitool_cfg_access(&prg2, B_FALSE, B_TRUE); 9500Sstevel@tonic-gate if (rval != SUCCESS) { 9510Sstevel@tonic-gate if (pcitool_debug) 9520Sstevel@tonic-gate prom_printf("BAR access failed\n"); 9530Sstevel@tonic-gate prg.status = prg2.status; 9540Sstevel@tonic-gate goto done_reg; 9550Sstevel@tonic-gate } 9560Sstevel@tonic-gate /* 9570Sstevel@tonic-gate * Reference proper PCI space based on the BAR. 9580Sstevel@tonic-gate * If 64 bit MEM space, need to load other half of the 9590Sstevel@tonic-gate * BAR first. 9600Sstevel@tonic-gate */ 9610Sstevel@tonic-gate 9620Sstevel@tonic-gate if (pcitool_debug) 9630Sstevel@tonic-gate prom_printf("bar returned is 0x%" PRIx64 "\n", 9640Sstevel@tonic-gate prg2.data); 9650Sstevel@tonic-gate if (!prg2.data) { 9660Sstevel@tonic-gate if (pcitool_debug) 9670Sstevel@tonic-gate prom_printf("BAR data == 0\n"); 9680Sstevel@tonic-gate rval = EINVAL; 9690Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 9700Sstevel@tonic-gate goto done_reg; 9710Sstevel@tonic-gate } 9720Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 9730Sstevel@tonic-gate if (pcitool_debug) 9740Sstevel@tonic-gate prom_printf("BAR data == -1\n"); 9750Sstevel@tonic-gate rval = EINVAL; 9760Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 9770Sstevel@tonic-gate goto done_reg; 9780Sstevel@tonic-gate } 9790Sstevel@tonic-gate 9800Sstevel@tonic-gate /* 9810Sstevel@tonic-gate * BAR has bits saying this space is IO space, unless 9820Sstevel@tonic-gate * this is the ROM address register. 9830Sstevel@tonic-gate */ 9840Sstevel@tonic-gate if (((PCI_BASE_SPACE_M & prg2.data) == 9850Sstevel@tonic-gate PCI_BASE_SPACE_IO) && 9860Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 9870Sstevel@tonic-gate if (pcitool_debug) 9880Sstevel@tonic-gate prom_printf("IO space\n"); 9890Sstevel@tonic-gate 9900Sstevel@tonic-gate prg2.data &= PCI_BASE_IO_ADDR_M; 9910Sstevel@tonic-gate prg.phys_addr = prg2.data + prg.offset; 9920Sstevel@tonic-gate 993*11245SZhijun.Fu@Sun.COM rval = pcitool_io_access(&prg, write_flag); 9940Sstevel@tonic-gate if ((rval != SUCCESS) && (pcitool_debug)) 9950Sstevel@tonic-gate prom_printf("IO access failed\n"); 9960Sstevel@tonic-gate 9970Sstevel@tonic-gate goto done_reg; 9980Sstevel@tonic-gate 9990Sstevel@tonic-gate 10000Sstevel@tonic-gate /* 10010Sstevel@tonic-gate * BAR has bits saying this space is 64 bit memory 10020Sstevel@tonic-gate * space, unless this is the ROM address register. 10030Sstevel@tonic-gate * 10040Sstevel@tonic-gate * The 64 bit address stored in two BAR cells is not 10050Sstevel@tonic-gate * necessarily aligned on an 8-byte boundary. 10060Sstevel@tonic-gate * Need to keep the first 4 bytes read, 10070Sstevel@tonic-gate * and do a separate read of the high 4 bytes. 10080Sstevel@tonic-gate */ 10090Sstevel@tonic-gate 10100Sstevel@tonic-gate } else if ((PCI_BASE_TYPE_ALL & prg2.data) && 10110Sstevel@tonic-gate (prg2.offset != PCI_CONF_ROM)) { 10120Sstevel@tonic-gate 10130Sstevel@tonic-gate uint32_t low_bytes = 10140Sstevel@tonic-gate (uint32_t)(prg2.data & ~PCI_BASE_TYPE_ALL); 10150Sstevel@tonic-gate 10160Sstevel@tonic-gate /* 10170Sstevel@tonic-gate * Don't try to read the next 4 bytes 10180Sstevel@tonic-gate * past the end of BARs. 10190Sstevel@tonic-gate */ 10200Sstevel@tonic-gate if (prg2.offset >= PCI_CONF_BASE5) { 10210Sstevel@tonic-gate prg.status = PCITOOL_OUT_OF_RANGE; 10220Sstevel@tonic-gate rval = EIO; 10230Sstevel@tonic-gate goto done_reg; 10240Sstevel@tonic-gate } 10250Sstevel@tonic-gate 10260Sstevel@tonic-gate /* 10270Sstevel@tonic-gate * Access device. 10280Sstevel@tonic-gate * prg2.status is modified on error. 10290Sstevel@tonic-gate */ 10300Sstevel@tonic-gate prg2.offset += 4; 1031*11245SZhijun.Fu@Sun.COM rval = pcitool_cfg_access(&prg2, 1032*11245SZhijun.Fu@Sun.COM B_FALSE, B_TRUE); 10330Sstevel@tonic-gate if (rval != SUCCESS) { 10340Sstevel@tonic-gate prg.status = prg2.status; 10350Sstevel@tonic-gate goto done_reg; 10360Sstevel@tonic-gate } 10370Sstevel@tonic-gate 10380Sstevel@tonic-gate if (prg2.data == 0xffffffff) { 10390Sstevel@tonic-gate prg.status = PCITOOL_INVALID_ADDRESS; 10400Sstevel@tonic-gate prg.status = EFAULT; 10410Sstevel@tonic-gate goto done_reg; 10420Sstevel@tonic-gate } 10430Sstevel@tonic-gate 10440Sstevel@tonic-gate prg2.data = (prg2.data << 32) + low_bytes; 10450Sstevel@tonic-gate if (pcitool_debug) 10460Sstevel@tonic-gate prom_printf( 10470Sstevel@tonic-gate "64 bit mem space. " 10480Sstevel@tonic-gate "64-bit bar is 0x%" PRIx64 "\n", 10490Sstevel@tonic-gate prg2.data); 10500Sstevel@tonic-gate 10510Sstevel@tonic-gate /* Mem32 space, including ROM */ 10520Sstevel@tonic-gate } else { 10530Sstevel@tonic-gate 10540Sstevel@tonic-gate if (prg2.offset == PCI_CONF_ROM) { 10550Sstevel@tonic-gate if (pcitool_debug) 10560Sstevel@tonic-gate prom_printf( 10570Sstevel@tonic-gate "Additional ROM " 10580Sstevel@tonic-gate "checking\n"); 10590Sstevel@tonic-gate /* Can't write to ROM */ 10600Sstevel@tonic-gate if (write_flag) { 10610Sstevel@tonic-gate prg.status = PCITOOL_ROM_WRITE; 10620Sstevel@tonic-gate rval = EIO; 10630Sstevel@tonic-gate goto done_reg; 10640Sstevel@tonic-gate 10650Sstevel@tonic-gate /* ROM disabled for reading */ 10660Sstevel@tonic-gate } else if (!(prg2.data & 0x00000001)) { 10670Sstevel@tonic-gate prg.status = 10680Sstevel@tonic-gate PCITOOL_ROM_DISABLED; 10690Sstevel@tonic-gate rval = EIO; 10700Sstevel@tonic-gate goto done_reg; 10710Sstevel@tonic-gate } 10720Sstevel@tonic-gate } 10730Sstevel@tonic-gate 10740Sstevel@tonic-gate if (pcitool_debug) 10750Sstevel@tonic-gate prom_printf("32 bit mem space\n"); 10760Sstevel@tonic-gate } 10770Sstevel@tonic-gate 10780Sstevel@tonic-gate /* Common code for all IO/MEM range spaces. */ 10790Sstevel@tonic-gate 10800Sstevel@tonic-gate base_addr = prg2.data; 10810Sstevel@tonic-gate if (pcitool_debug) 10820Sstevel@tonic-gate prom_printf( 10830Sstevel@tonic-gate "addr portion of bar is 0x%" PRIx64 ", " 10840Sstevel@tonic-gate "base=0x%" PRIx64 ", " 10850Sstevel@tonic-gate "offset:0x%" PRIx64 "\n", 10860Sstevel@tonic-gate prg2.data, base_addr, prg.offset); 10870Sstevel@tonic-gate /* 10880Sstevel@tonic-gate * Use offset provided by caller to index into 10890Sstevel@tonic-gate * desired space, then access. 10900Sstevel@tonic-gate * Note that prg.status is modified on error. 10910Sstevel@tonic-gate */ 10920Sstevel@tonic-gate prg.phys_addr = base_addr + prg.offset; 10930Sstevel@tonic-gate 10940Sstevel@tonic-gate virt_addr = pcitool_map(prg.phys_addr, size, 10950Sstevel@tonic-gate &num_virt_pages); 10960Sstevel@tonic-gate if (virt_addr == NULL) { 10970Sstevel@tonic-gate prg.status = PCITOOL_IO_ERROR; 10980Sstevel@tonic-gate rval = EIO; 10990Sstevel@tonic-gate goto done_reg; 11000Sstevel@tonic-gate } 11010Sstevel@tonic-gate 1102*11245SZhijun.Fu@Sun.COM rval = pcitool_mem_access(&prg, virt_addr, write_flag); 11030Sstevel@tonic-gate pcitool_unmap(virt_addr, num_virt_pages); 11040Sstevel@tonic-gate } 11050Sstevel@tonic-gate done_reg: 11064397Sschwartz prg.drvr_version = PCITOOL_VERSION; 11070Sstevel@tonic-gate if (ddi_copyout(&prg, arg, sizeof (pcitool_reg_t), mode) != 11080Sstevel@tonic-gate DDI_SUCCESS) { 11090Sstevel@tonic-gate if (pcitool_debug) 11100Sstevel@tonic-gate prom_printf("Error returning arguments.\n"); 11110Sstevel@tonic-gate rval = EFAULT; 11120Sstevel@tonic-gate } 11130Sstevel@tonic-gate break; 11140Sstevel@tonic-gate default: 11150Sstevel@tonic-gate rval = ENOTTY; 11160Sstevel@tonic-gate break; 11170Sstevel@tonic-gate } 11180Sstevel@tonic-gate return (rval); 11190Sstevel@tonic-gate } 1120