14667Smh27603 /* 24667Smh27603 * CDDL HEADER START 34667Smh27603 * 44667Smh27603 * The contents of this file are subject to the terms of the 54667Smh27603 * Common Development and Distribution License (the "License"). 64667Smh27603 * You may not use this file except in compliance with the License. 74667Smh27603 * 84667Smh27603 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 94667Smh27603 * or http://www.opensolaris.org/os/licensing. 104667Smh27603 * See the License for the specific language governing permissions 114667Smh27603 * and limitations under the License. 124667Smh27603 * 134667Smh27603 * When distributing Covered Code, include this CDDL HEADER in each 144667Smh27603 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 154667Smh27603 * If applicable, add the following below this CDDL HEADER, with the 164667Smh27603 * fields enclosed by brackets "[]" replaced with your own identifying 174667Smh27603 * information: Portions Copyright [yyyy] [name of copyright owner] 184667Smh27603 * 194667Smh27603 * CDDL HEADER END 204667Smh27603 */ 214667Smh27603 /* 22*10488SMark.Haywood@Sun.COM * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 234667Smh27603 * Use is subject to license terms. 244667Smh27603 */ 25*10488SMark.Haywood@Sun.COM /* 26*10488SMark.Haywood@Sun.COM * Copyright (c) 2009, Intel Corporation. 27*10488SMark.Haywood@Sun.COM * All Rights Reserved. 28*10488SMark.Haywood@Sun.COM */ 294667Smh27603 304667Smh27603 #ifndef _SYS_PPMVAR_H 314667Smh27603 #define _SYS_PPMVAR_H 324667Smh27603 334667Smh27603 #include <sys/epm.h> 344667Smh27603 #include <sys/sunldi.h> 354667Smh27603 364667Smh27603 #ifdef __cplusplus 374667Smh27603 extern "C" { 384667Smh27603 #endif 394667Smh27603 404667Smh27603 414667Smh27603 typedef struct ppm_unit { 424667Smh27603 dev_info_t *dip; /* node dev info */ 434667Smh27603 kmutex_t lock; /* global driver lock */ 444667Smh27603 uint_t states; /* driver states */ 454667Smh27603 timeout_id_t led_tid; /* timeout id for LED */ 464667Smh27603 } ppm_unit_t; 474667Smh27603 484667Smh27603 /* 494667Smh27603 * driver states 504667Smh27603 */ 514667Smh27603 #define PPM_STATE_SUSPENDED 0x1 /* driver is suspended */ 524667Smh27603 534667Smh27603 /* 544667Smh27603 * Check for domain operational 554667Smh27603 */ 564667Smh27603 #define PPM_DOMAIN_UP(domp) (!(domp->dflags & PPMD_OFFLINE)) 574667Smh27603 584667Smh27603 /* 594667Smh27603 * LED constants 604667Smh27603 */ 614667Smh27603 #define PPM_LED_PULSE (drv_usectohz(250000)) /* 0.25 seconds */ 624667Smh27603 #define PPM_LEDON_INTERVAL (1 * PPM_LED_PULSE) 634667Smh27603 #define PPM_LEDOFF_INTERVAL (8 * PPM_LED_PULSE) 644667Smh27603 #define PPM_LEDON 1 /* (s10) */ 654667Smh27603 #define PPM_LEDOFF 0 /* (s10) */ 664667Smh27603 674667Smh27603 /* 684667Smh27603 * internal form of "ppm.conf" data 694667Smh27603 */ 704667Smh27603 struct ppm_db { 714667Smh27603 struct ppm_db *next; 724667Smh27603 char *name; /* device name */ 734667Smh27603 int plen; /* strlen before wildcard(s10) */ 744667Smh27603 int wccnt; /* upto 2 '*' allowed */ 754667Smh27603 int wcpos[2]; /* '*' location in pathname */ 764667Smh27603 }; 774667Smh27603 typedef struct ppm_db ppm_db_t; 784667Smh27603 794667Smh27603 struct ppm_cdata { 804667Smh27603 char *name; /* property name */ 814667Smh27603 char **strings; /* string array */ 824667Smh27603 uint_t cnt; /* property count */ 834667Smh27603 }; 844667Smh27603 854667Smh27603 /* 864667Smh27603 * ppm device info 874667Smh27603 */ 884667Smh27603 struct ppm_dev { 894667Smh27603 struct ppm_dev *next; 904667Smh27603 struct ppm_domain *domp; 914667Smh27603 dev_info_t *dip; 924667Smh27603 char *path; /* OBP device pathname */ 934667Smh27603 int cmpt; /* component number */ 944667Smh27603 int rplvl; /* last requested power level */ 954667Smh27603 int level; /* actual current power level */ 964667Smh27603 int lowest; /* lowest power level for device */ 974667Smh27603 int highest; /* highest power level for device */ 984667Smh27603 uint_t flags; 994667Smh27603 }; 1004667Smh27603 typedef struct ppm_dev ppm_dev_t; 1014667Smh27603 1024667Smh27603 /* 1034667Smh27603 * ppm_dev.flags field 1044667Smh27603 */ 1054667Smh27603 #define PPMDEV_PCI66_D2 0x1 /* device support D2 at pci 66mhz */ 1064667Smh27603 #define PPMDEV_PCI_PROP_CLKPM 0x2 /* clock can be power managed */ 1074667Smh27603 #define PPM_PM_POWEROP 0x10 /* power level change, initiated */ 1084667Smh27603 /* from PM is in progress. */ 1094667Smh27603 #define PPM_PHC_WHILE_SET_POWER 0x20 /* power level of a device is */ 1104667Smh27603 /* changed through */ 1114667Smh27603 /* pm_power_has_changed path */ 1124667Smh27603 /* while power level change, */ 1134667Smh27603 /* initiated from PM is in */ 1144667Smh27603 /* progress. */ 1154667Smh27603 1164667Smh27603 1174667Smh27603 /* 1184667Smh27603 * per domain record of device _ever_ managed by ppm 1194667Smh27603 */ 1204667Smh27603 struct ppm_owned { 1214667Smh27603 struct ppm_owned *next; 1224667Smh27603 char *path; /* device pathname */ 1234667Smh27603 int initializing; /* initializing flag */ 1244667Smh27603 }; 1254667Smh27603 typedef struct ppm_owned ppm_owned_t; 1264667Smh27603 1274667Smh27603 1284667Smh27603 /* 1294667Smh27603 * domain control data structure - 1304667Smh27603 * when you need to do an op for a domain, look up the op in the 1314667Smh27603 * cmd member of the struct, and then perform the method on the 1324667Smh27603 * path using iowr cmd with the args specified in val or val and 1334667Smh27603 * mask or the speed index. 1344667Smh27603 */ 1354667Smh27603 struct ppm_dc { 1364667Smh27603 struct ppm_dc *next; 1374667Smh27603 ldi_handle_t lh; /* layered (ldi) handle */ 1384667Smh27603 char *path; /* control device prom pathname */ 1394667Smh27603 uint_t cmd; /* search key: op to be performed */ 1405295Srandyf /* one of: PPMDC_CPU_NEXT */ 1415295Srandyf /* PPMDC_CPU_GO, PPMDC_FET_ON, */ 1425295Srandyf /* PPMDC_FET_OFF, PPMDC_LED_ON, */ 1435295Srandyf /* PPMDC_LED_OFF, PPMDC_PCI_ON, */ 1445295Srandyf /* PPMDC_ENTER_S3, PPMDC_PCI_OFF */ 1455295Srandyf /* PPMDC_EXIT_S3 commands */ 1464667Smh27603 uint_t method; /* control method / union selector */ 1474667Smh27603 /* one of PPMDC_KIO, PPMDC_I2CKIO, */ 1484667Smh27603 /* PPMDC_CPUSPEEDKIO */ 1494667Smh27603 1504667Smh27603 union { 1514667Smh27603 /* In each sub struct in union, the first three fields */ 1524667Smh27603 /* must be .iord, .iowr and .val and in such order. */ 1534667Smh27603 /* The .method field above selects a union sub struct */ 1544667Smh27603 /* for a particular .cmd operation. */ 1554667Smh27603 /* The association between .method and .cmd is platform */ 1564667Smh27603 /* specific, therefore described in ppm.conf file. */ 1574667Smh27603 1584667Smh27603 /* PPMDC_KIO: simple KIO */ 1594667Smh27603 struct m_kio { 1604667Smh27603 uint_t iord; /* IOCTL read cmd */ 1614667Smh27603 uint_t iowr; /* IOCTL write cmd */ 1624667Smh27603 uint_t val; /* ioctl arg */ 1634667Smh27603 uint_t delay; /* total delay before this */ 1644667Smh27603 /* operation can be carried out */ 1654667Smh27603 uint_t post_delay; /* post delay, if any */ 1664667Smh27603 } kio; 1674667Smh27603 1685295Srandyf #ifdef sun4u 1694667Smh27603 /* PPMDC_I2CKIO: KIO requires 'arg' as struct i2c_gpio */ 1704667Smh27603 /* (defined in i2c_client.h) */ 1714667Smh27603 struct m_i2ckio { 1724667Smh27603 uint_t iord; /* IOCTL read cmd */ 1734667Smh27603 uint_t iowr; /* IOCTL write cmd */ 1744667Smh27603 uint_t val; /* register content */ 1754667Smh27603 uint_t mask; /* mask to select relevant bits */ 1764667Smh27603 /* of register content */ 1774667Smh27603 uint_t delay; /* total delay before this */ 1784667Smh27603 /* operation can be carried out */ 1794667Smh27603 uint_t post_delay; /* post delay, if any */ 1804667Smh27603 } i2c; 1815295Srandyf #endif 1824667Smh27603 1834667Smh27603 /* PPMDC_CPUSPEEDKIO, PPMDC_VCORE: cpu estar related */ 1844667Smh27603 /* simple KIO */ 1854667Smh27603 struct m_cpu { 1864667Smh27603 uint_t iord; /* IOCTL read cmd */ 1874667Smh27603 uint_t iowr; /* IOCTL write cmd */ 1884667Smh27603 int val; /* new register value */ 1894667Smh27603 uint_t speeds; /* number of speeds cpu supports */ 1904667Smh27603 uint_t delay; /* microseconds post op delay */ 1914667Smh27603 } cpu; 1924667Smh27603 } m_un; 1934667Smh27603 }; 1944667Smh27603 typedef struct ppm_dc ppm_dc_t; 1954667Smh27603 1964667Smh27603 /* 1974667Smh27603 * ppm_dc.cmd field - 1984667Smh27603 */ 1994667Smh27603 #define PPMDC_CPU_NEXT 2 2004667Smh27603 #define PPMDC_PRE_CHNG 3 2014667Smh27603 #define PPMDC_CPU_GO 4 2024667Smh27603 #define PPMDC_POST_CHNG 5 2034667Smh27603 #define PPMDC_FET_ON 6 2044667Smh27603 #define PPMDC_FET_OFF 7 2054667Smh27603 #define PPMDC_LED_ON 8 2064667Smh27603 #define PPMDC_LED_OFF 9 2074667Smh27603 #define PPMDC_CLK_ON 10 2084667Smh27603 #define PPMDC_CLK_OFF 11 2094667Smh27603 #define PPMDC_PRE_PWR_OFF 12 2104667Smh27603 #define PPMDC_PRE_PWR_ON 13 2114667Smh27603 #define PPMDC_POST_PWR_ON 14 2124667Smh27603 #define PPMDC_PWR_OFF 15 2134667Smh27603 #define PPMDC_PWR_ON 16 2144667Smh27603 #define PPMDC_RESET_OFF 17 2154667Smh27603 #define PPMDC_RESET_ON 18 2165295Srandyf #define PPMDC_ENTER_S3 19 2175295Srandyf #define PPMDC_EXIT_S3 20 2184667Smh27603 2194667Smh27603 /* 2204667Smh27603 * ppm_dc.method field - select union element 2214667Smh27603 */ 2224667Smh27603 #define PPMDC_KIO 1 /* simple ioctl with val as arg */ 2234667Smh27603 #define PPMDC_CPUSPEEDKIO 2 /* ioctl with speed index arg */ 2244667Smh27603 #define PPMDC_VCORE 3 /* CPU Vcore change operation */ 2255295Srandyf #ifdef sun4u 2264667Smh27603 #define PPMDC_I2CKIO 4 /* ioctl with i2c_gpio_t as arg */ 2275295Srandyf #endif 2284667Smh27603 2294667Smh27603 /* 2304667Smh27603 * devices that are powered by the same source 2314667Smh27603 * are grouped by this struct as a "power domain" 2324667Smh27603 */ 2334667Smh27603 struct ppm_domain { 2344667Smh27603 char *name; /* domain name */ 2354667Smh27603 int dflags; /* domain flags */ 2364667Smh27603 int pwr_cnt; /* number of powered up devices */ 2374667Smh27603 ppm_db_t *conflist; /* all devices from ppm.conf file */ 2384667Smh27603 ppm_dev_t *devlist; /* current attached devices */ 2394667Smh27603 char *propname; /* domain property name */ 2404667Smh27603 kmutex_t lock; /* domain lock */ 2414667Smh27603 int refcnt; /* domain lock ref count */ 2424667Smh27603 int model; /* pm model, CPU, FET or LED */ 2434667Smh27603 int status; /* domain specific status */ 244*10488SMark.Haywood@Sun.COM int sub_domain; /* sub-domain */ 2454667Smh27603 ppm_dc_t *dc; /* domain control method */ 2464667Smh27603 ppm_owned_t *owned; /* list of ever owned devices */ 2474667Smh27603 struct ppm_domain *next; /* a linked list */ 2484667Smh27603 clock_t last_off_time; /* last time domain was off */ 2494667Smh27603 2504667Smh27603 }; 2514667Smh27603 typedef struct ppm_domain ppm_domain_t; 2524667Smh27603 2534667Smh27603 2544667Smh27603 /* 2554667Smh27603 * ppm_domain.model field - 2564667Smh27603 */ 2574667Smh27603 #define PPMD_CPU 1 /* cpu PM model */ 2584667Smh27603 #define PPMD_FET 2 /* power FET pm model */ 2594667Smh27603 #define PPMD_LED 3 /* LED pm model */ 2604667Smh27603 #define PPMD_PCI 4 /* PCI pm model */ 2614667Smh27603 #define PPMD_PCI_PROP 5 /* PCI_PROP pm model */ 2624667Smh27603 #define PPMD_PCIE 6 /* PCI Express pm model */ 2635295Srandyf #define PPMD_SX 7 /* ACPI Sx pm model */ 2644667Smh27603 2654667Smh27603 #define PPMD_IS_PCI(model) \ 2664667Smh27603 ((model) == PPMD_PCI || (model) == PPMD_PCI_PROP) 2674667Smh27603 2684667Smh27603 /* 2694667Smh27603 * ppm_domain.status field - 2704667Smh27603 */ 2714667Smh27603 #define PPMD_OFF 0x0 /* FET/LED/PCI clock: off */ 2724667Smh27603 #define PPMD_ON 0x1 /* FET/LED/PCI clock: on */ 2734667Smh27603 2744667Smh27603 /* 2754667Smh27603 * ppm_domain.dflags field - 2764667Smh27603 */ 2774667Smh27603 #define PPMD_LOCK_ONE 0x1 2784667Smh27603 #define PPMD_LOCK_ALL 0x4 2794667Smh27603 #define PPMD_PCI33MHZ 0x1000 /* 33mhz PCI slot */ 2804667Smh27603 #define PPMD_PCI66MHZ 0x2000 /* 66mhz PCI slot */ 2814667Smh27603 #define PPMD_INITCHILD_CLKON 0x4000 /* clk turned on in init_child */ 2824667Smh27603 #define PPMD_OFFLINE 0x10000 /* domain is not functional */ 2834667Smh27603 #define PPMD_CPU_READY 0x20000 /* CPU domain can process power call */ 2844667Smh27603 2854667Smh27603 struct ppm_domit { 2864667Smh27603 char *name; 2874667Smh27603 int model; 2884667Smh27603 int dflags; 2894667Smh27603 int status; 2904667Smh27603 }; 2914667Smh27603 extern struct ppm_domit ppm_domit_data[]; 2924667Smh27603 2934667Smh27603 /* 2944667Smh27603 * XXppm driver-specific routines called from common code (s10) 2954667Smh27603 */ 2964667Smh27603 struct ppm_funcs { 2974667Smh27603 void (*dev_init)(ppm_dev_t *); 2984667Smh27603 void (*dev_fini)(ppm_dev_t *); 2994667Smh27603 void (*iocset)(uint8_t); 3004667Smh27603 uint8_t (*iocget)(void); 3014667Smh27603 }; 3024667Smh27603 3034667Smh27603 extern ppm_domain_t *ppm_domain_p; 3044667Smh27603 extern void *ppm_statep; 3054667Smh27603 extern int ppm_inst; 3064667Smh27603 extern ppm_domain_t *ppm_domains[]; /* (s10) */ 3074667Smh27603 extern struct ppm_funcs ppmf; /* (s10) */ 3084667Smh27603 3094667Smh27603 extern void ppm_dev_init(ppm_dev_t *); 3104667Smh27603 extern void ppm_dev_fini(ppm_dev_t *); 3114667Smh27603 extern int ppm_create_db(dev_info_t *); 3124667Smh27603 extern int ppm_claim_dev(dev_info_t *); 3134667Smh27603 extern void ppm_rem_dev(dev_info_t *); 3144667Smh27603 extern ppm_dev_t *ppm_get_dev(dev_info_t *, ppm_domain_t *); 3154667Smh27603 extern void ppm_init_cb(dev_info_t *); 3164667Smh27603 extern int ppm_init_lyr(ppm_dc_t *, dev_info_t *); 3174667Smh27603 extern ppm_domain_t *ppm_lookup_dev(dev_info_t *); 3184667Smh27603 extern ppm_domain_t *ppm_lookup_domain(char *); 3194667Smh27603 extern ppm_dc_t *ppm_lookup_dc(ppm_domain_t *, int); 3204667Smh27603 extern ppm_dc_t *ppm_lookup_hndl(int, ppm_dc_t *); 3214667Smh27603 extern ppm_domain_t *ppm_get_domain_by_dev(const char *); 3224667Smh27603 extern boolean_t ppm_none_else_holds_power(ppm_domain_t *); 3234667Smh27603 extern ppm_owned_t *ppm_add_owned(dev_info_t *, ppm_domain_t *); 3244667Smh27603 extern void ppm_lock_one(ppm_dev_t *, power_req_t *, int *); 3254667Smh27603 extern void ppm_lock_all(ppm_domain_t *, power_req_t *, int *); 3264667Smh27603 extern boolean_t ppm_manage_early_cpus(dev_info_t *, int, int *); 3274667Smh27603 extern int ppm_change_cpu_power(ppm_dev_t *, int); 3284667Smh27603 extern int ppm_revert_cpu_power(ppm_dev_t *, int); 3294667Smh27603 extern ppm_dev_t *ppm_add_dev(dev_info_t *, ppm_domain_t *); 3304667Smh27603 3314667Smh27603 #define PPM_GET_PRIVATE(dip) \ 3324667Smh27603 DEVI(dip)->devi_pm_ppm_private 3334667Smh27603 #define PPM_SET_PRIVATE(dip, datap) \ 3344667Smh27603 DEVI(dip)->devi_pm_ppm_private = datap 3354667Smh27603 3364667Smh27603 #define PPM_LOCK_DOMAIN(domp) { \ 3374667Smh27603 if (!MUTEX_HELD(&(domp)->lock)) \ 3384667Smh27603 mutex_enter(&(domp)->lock); \ 3394667Smh27603 (domp)->refcnt++; \ 3404667Smh27603 } 3414667Smh27603 3424667Smh27603 #define PPM_UNLOCK_DOMAIN(domp) { \ 3434667Smh27603 ASSERT(MUTEX_HELD(&(domp)->lock) && \ 3444667Smh27603 (domp)->refcnt > 0); \ 3454667Smh27603 if (--(domp)->refcnt == 0) \ 3464667Smh27603 mutex_exit(&(domp)->lock); \ 3474667Smh27603 } 3484667Smh27603 3494667Smh27603 /* 3504667Smh27603 * debug support 3514667Smh27603 */ 3524667Smh27603 #ifdef DEBUG 3534667Smh27603 #include <sys/promif.h> 3544667Smh27603 3554667Smh27603 extern char *ppm_get_ctlstr(int, uint_t); 3564667Smh27603 extern void ppm_print_dc(struct ppm_dc *); 3574667Smh27603 3584667Smh27603 extern uint_t ppm_debug; 3594667Smh27603 3604667Smh27603 #define D_CREATEDB 0x00000001 3614667Smh27603 #define D_CLAIMDEV 0x00000002 3624667Smh27603 #define D_ADDDEV 0x00000004 3634667Smh27603 #define D_REMDEV 0x00000008 3644667Smh27603 #define D_LOWEST 0x00000010 3654667Smh27603 #define D_SETLVL 0x00000020 3664667Smh27603 #define D_GPIO 0x00000040 3674667Smh27603 #define D_CPU 0x00000080 3684667Smh27603 #define D_FET 0x00000100 3694667Smh27603 #define D_PCIUPA 0x00000200 3704667Smh27603 #define D_1394 0x00000400 3714667Smh27603 #define D_CTLOPS1 0x00000800 3724667Smh27603 #define D_CTLOPS2 0x00001000 3734667Smh27603 #define D_SOME 0x00002000 3744667Smh27603 #define D_LOCKS 0x00004000 3754667Smh27603 #define D_IOCTL 0x00008000 3764667Smh27603 #define D_ATTACH 0x00010000 3774667Smh27603 #define D_DETACH 0x00020000 3784667Smh27603 #define D_OPEN 0x00040000 3794667Smh27603 #define D_CLOSE 0x00080000 3804667Smh27603 #define D_INIT 0x00100000 3814667Smh27603 #define D_FINI 0x00200000 3824667Smh27603 #define D_ERROR 0x00400000 3834667Smh27603 #define D_SETPWR 0x00800000 3844667Smh27603 #define D_LED 0x01000000 3854667Smh27603 #define D_PCI 0x02000000 3864667Smh27603 #define D_PPMDC 0x04000000 3874667Smh27603 #define D_CPR 0x08000000 3884667Smh27603 3894667Smh27603 #define PPMD(level, arglist) { \ 3904667Smh27603 if (ppm_debug & (level)) { \ 3914667Smh27603 pm_log arglist; \ 3924667Smh27603 } \ 3934667Smh27603 } 3944667Smh27603 /* (s10) */ 3954667Smh27603 #define DPRINTF PPMD 3964667Smh27603 3974667Smh27603 #else /* DEBUG */ 3984667Smh27603 #define PPMD(level, arglist) 3994667Smh27603 #define DPRINTF(flag, args) /* (s10) */ 4004667Smh27603 #endif /* DEBUG */ 4014667Smh27603 4024667Smh27603 #ifdef __cplusplus 4034667Smh27603 } 4044667Smh27603 #endif 4054667Smh27603 4064667Smh27603 #endif /* _SYS_PPMVAR_H */ 407