1*0Sstevel@tonic-gate /* 2*0Sstevel@tonic-gate * CDDL HEADER START 3*0Sstevel@tonic-gate * 4*0Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*0Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*0Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*0Sstevel@tonic-gate * with the License. 8*0Sstevel@tonic-gate * 9*0Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*0Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*0Sstevel@tonic-gate * See the License for the specific language governing permissions 12*0Sstevel@tonic-gate * and limitations under the License. 13*0Sstevel@tonic-gate * 14*0Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*0Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*0Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*0Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*0Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*0Sstevel@tonic-gate * 20*0Sstevel@tonic-gate * CDDL HEADER END 21*0Sstevel@tonic-gate */ 22*0Sstevel@tonic-gate /* 23*0Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*0Sstevel@tonic-gate * Use is subject to license terms. 25*0Sstevel@tonic-gate */ 26*0Sstevel@tonic-gate 27*0Sstevel@tonic-gate #ifndef _SYS_PCI_H 28*0Sstevel@tonic-gate #define _SYS_PCI_H 29*0Sstevel@tonic-gate 30*0Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 31*0Sstevel@tonic-gate 32*0Sstevel@tonic-gate #ifdef __cplusplus 33*0Sstevel@tonic-gate extern "C" { 34*0Sstevel@tonic-gate #endif 35*0Sstevel@tonic-gate 36*0Sstevel@tonic-gate /* 37*0Sstevel@tonic-gate * PCI Configuration Header offsets 38*0Sstevel@tonic-gate */ 39*0Sstevel@tonic-gate #define PCI_CONF_VENID 0x0 /* vendor id, 2 bytes */ 40*0Sstevel@tonic-gate #define PCI_CONF_DEVID 0x2 /* device id, 2 bytes */ 41*0Sstevel@tonic-gate #define PCI_CONF_COMM 0x4 /* command register, 2 bytes */ 42*0Sstevel@tonic-gate #define PCI_CONF_STAT 0x6 /* status register, 2 bytes */ 43*0Sstevel@tonic-gate #define PCI_CONF_REVID 0x8 /* revision id, 1 byte */ 44*0Sstevel@tonic-gate #define PCI_CONF_PROGCLASS 0x9 /* programming class code, 1 byte */ 45*0Sstevel@tonic-gate #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */ 46*0Sstevel@tonic-gate #define PCI_CONF_BASCLASS 0xB /* basic class code, 1 byte */ 47*0Sstevel@tonic-gate #define PCI_CONF_CACHE_LINESZ 0xC /* cache line size, 1 byte */ 48*0Sstevel@tonic-gate #define PCI_CONF_LATENCY_TIMER 0xD /* latency timer, 1 byte */ 49*0Sstevel@tonic-gate #define PCI_CONF_HEADER 0xE /* header type, 1 byte */ 50*0Sstevel@tonic-gate #define PCI_CONF_BIST 0xF /* builtin self test, 1 byte */ 51*0Sstevel@tonic-gate 52*0Sstevel@tonic-gate /* 53*0Sstevel@tonic-gate * Header type 0 offsets 54*0Sstevel@tonic-gate */ 55*0Sstevel@tonic-gate #define PCI_CONF_BASE0 0x10 /* base register 0, 4 bytes */ 56*0Sstevel@tonic-gate #define PCI_CONF_BASE1 0x14 /* base register 1, 4 bytes */ 57*0Sstevel@tonic-gate #define PCI_CONF_BASE2 0x18 /* base register 2, 4 bytes */ 58*0Sstevel@tonic-gate #define PCI_CONF_BASE3 0x1c /* base register 3, 4 bytes */ 59*0Sstevel@tonic-gate #define PCI_CONF_BASE4 0x20 /* base register 4, 4 bytes */ 60*0Sstevel@tonic-gate #define PCI_CONF_BASE5 0x24 /* base register 5, 4 bytes */ 61*0Sstevel@tonic-gate #define PCI_CONF_CIS 0x28 /* Cardbus CIS Pointer */ 62*0Sstevel@tonic-gate #define PCI_CONF_SUBVENID 0x2c /* Subsystem Vendor ID */ 63*0Sstevel@tonic-gate #define PCI_CONF_SUBSYSID 0x2e /* Subsystem ID */ 64*0Sstevel@tonic-gate #define PCI_CONF_ROM 0x30 /* ROM base register, 4 bytes */ 65*0Sstevel@tonic-gate #define PCI_CONF_CAP_PTR 0x34 /* capabilities pointer, 1 byte */ 66*0Sstevel@tonic-gate #define PCI_CONF_ILINE 0x3c /* interrupt line, 1 byte */ 67*0Sstevel@tonic-gate #define PCI_CONF_IPIN 0x3d /* interrupt pin, 1 byte */ 68*0Sstevel@tonic-gate #define PCI_CONF_MIN_G 0x3e /* minimum grant, 1 byte */ 69*0Sstevel@tonic-gate #define PCI_CONF_MAX_L 0x3f /* maximum grant, 1 byte */ 70*0Sstevel@tonic-gate 71*0Sstevel@tonic-gate /* 72*0Sstevel@tonic-gate * PCI to PCI bridge configuration space header format 73*0Sstevel@tonic-gate */ 74*0Sstevel@tonic-gate #define PCI_BCNF_PRIBUS 0x18 /* primary bus number */ 75*0Sstevel@tonic-gate #define PCI_BCNF_SECBUS 0x19 /* secondary bus number */ 76*0Sstevel@tonic-gate #define PCI_BCNF_SUBBUS 0x1a /* subordinate bus number */ 77*0Sstevel@tonic-gate #define PCI_BCNF_LATENCY_TIMER 0x1b 78*0Sstevel@tonic-gate #define PCI_BCNF_IO_BASE_LOW 0x1c 79*0Sstevel@tonic-gate #define PCI_BCNF_IO_LIMIT_LOW 0x1d 80*0Sstevel@tonic-gate #define PCI_BCNF_SEC_STATUS 0x1e 81*0Sstevel@tonic-gate #define PCI_BCNF_MEM_BASE 0x20 82*0Sstevel@tonic-gate #define PCI_BCNF_MEM_LIMIT 0x22 83*0Sstevel@tonic-gate #define PCI_BCNF_PF_BASE_LOW 0x24 84*0Sstevel@tonic-gate #define PCI_BCNF_PF_LIMIT_LOW 0x26 85*0Sstevel@tonic-gate #define PCI_BCNF_PF_BASE_HIGH 0x28 86*0Sstevel@tonic-gate #define PCI_BCNF_PF_LIMIT_HIGH 0x2c 87*0Sstevel@tonic-gate #define PCI_BCNF_IO_BASE_HI 0x30 88*0Sstevel@tonic-gate #define PCI_BCNF_IO_LIMIT_HI 0x32 89*0Sstevel@tonic-gate #define PCI_BCNF_CAP_PTR 0x34 90*0Sstevel@tonic-gate #define PCI_BCNF_ROM 0x38 91*0Sstevel@tonic-gate #define PCI_BCNF_ILINE 0x3c 92*0Sstevel@tonic-gate #define PCI_BCNF_IPIN 0x3d 93*0Sstevel@tonic-gate #define PCI_BCNF_BCNTRL 0x3e 94*0Sstevel@tonic-gate 95*0Sstevel@tonic-gate #define PCI_BCNF_BASE_NUM 0x2 96*0Sstevel@tonic-gate 97*0Sstevel@tonic-gate /* 98*0Sstevel@tonic-gate * PCI to PCI bridge control register (0x3e) format 99*0Sstevel@tonic-gate */ 100*0Sstevel@tonic-gate #define PCI_BCNF_BCNTRL_PARITY_ENABLE 0x1 101*0Sstevel@tonic-gate #define PCI_BCNF_BCNTRL_SERR_ENABLE 0x2 102*0Sstevel@tonic-gate #define PCI_BCNF_BCNTRL_MAST_AB_MODE 0x20 103*0Sstevel@tonic-gate #define PCI_BCNF_BCNTRL_DTO_STAT 0x400 104*0Sstevel@tonic-gate 105*0Sstevel@tonic-gate #define PCI_BCNF_IO_MASK 0xf0 106*0Sstevel@tonic-gate #define PCI_BCNF_MEM_MASK 0xfff0 107*0Sstevel@tonic-gate 108*0Sstevel@tonic-gate /* 109*0Sstevel@tonic-gate * Header type 2 (Cardbus) offsets 110*0Sstevel@tonic-gate */ 111*0Sstevel@tonic-gate #define PCI_CBUS_SOCK_REG 0x10 /* Cardbus socket regs, 4 bytes */ 112*0Sstevel@tonic-gate #define PCI_CBUS_RESERVED1 0x14 /* Reserved, 2 bytes */ 113*0Sstevel@tonic-gate #define PCI_CBUS_SEC_STATUS 0x16 /* Secondary status, 2 bytes */ 114*0Sstevel@tonic-gate #define PCI_CBUS_PCI_BUS_NO 0x18 /* PCI bus number, 1 byte */ 115*0Sstevel@tonic-gate #define PCI_CBUS_CBUS_NO 0x19 /* Cardbus bus number, 1 byte */ 116*0Sstevel@tonic-gate #define PCI_CBUS_SUB_BUS_NO 0x1a /* Subordinate bus number, 1 byte */ 117*0Sstevel@tonic-gate #define PCI_CBUS_LATENCY_TIMER 0x1b /* Cardbus latency timer, 1 byte */ 118*0Sstevel@tonic-gate #define PCI_CBUS_MEM_BASE0 0x1c /* Memory base reg 0, 4 bytes */ 119*0Sstevel@tonic-gate #define PCI_CBUS_MEM_LIMIT0 0x20 /* Memory limit reg 0, 4 bytes */ 120*0Sstevel@tonic-gate #define PCI_CBUS_MEM_BASE1 0x24 /* Memory base reg 1, 4 bytes */ 121*0Sstevel@tonic-gate #define PCI_CBUS_MEM_LIMIT1 0x28 /* Memory limit reg 1, 4 bytes */ 122*0Sstevel@tonic-gate #define PCI_CBUS_IO_BASE0 0x2c /* IO base reg 0, 4 bytes */ 123*0Sstevel@tonic-gate #define PCI_CBUS_IO_LIMIT0 0x30 /* IO limit reg 0, 4 bytes */ 124*0Sstevel@tonic-gate #define PCI_CBUS_IO_BASE1 0x34 /* IO base reg 1, 4 bytes */ 125*0Sstevel@tonic-gate #define PCI_CBUS_IO_LIMIT1 0x38 /* IO limit reg 1, 4 bytes */ 126*0Sstevel@tonic-gate #define PCI_CBUS_ILINE 0x3c /* interrupt line, 1 byte */ 127*0Sstevel@tonic-gate #define PCI_CBUS_IPIN 0x3d /* interrupt pin, 1 byte */ 128*0Sstevel@tonic-gate #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 129*0Sstevel@tonic-gate #define PCI_CBUS_BRIDGE_CTRL 0x3e /* Bridge control, 2 bytes */ 130*0Sstevel@tonic-gate #define PCI_CBUS_SUBVENID 0x40 /* Subsystem Vendor ID, 2 bytes */ 131*0Sstevel@tonic-gate #define PCI_CBUS_SUBSYSID 0x42 /* Subsystem ID, 2 bytes */ 132*0Sstevel@tonic-gate #define PCI_CBUS_LEG_MODE_ADDR 0x44 /* PCCard 16bit IF legacy mode addr */ 133*0Sstevel@tonic-gate 134*0Sstevel@tonic-gate #define PCI_CBUS_BASE_NUM 0x1 /* number of base registers */ 135*0Sstevel@tonic-gate 136*0Sstevel@tonic-gate /* 137*0Sstevel@tonic-gate * PCI command register bits 138*0Sstevel@tonic-gate */ 139*0Sstevel@tonic-gate #define PCI_COMM_IO 0x1 /* I/O access enable */ 140*0Sstevel@tonic-gate #define PCI_COMM_MAE 0x2 /* memory access enable */ 141*0Sstevel@tonic-gate #define PCI_COMM_ME 0x4 /* master enable */ 142*0Sstevel@tonic-gate #define PCI_COMM_SPEC_CYC 0x8 143*0Sstevel@tonic-gate #define PCI_COMM_MEMWR_INVAL 0x10 144*0Sstevel@tonic-gate #define PCI_COMM_PALETTE_SNOOP 0x20 145*0Sstevel@tonic-gate #define PCI_COMM_PARITY_DETECT 0x40 146*0Sstevel@tonic-gate #define PCI_COMM_WAIT_CYC_ENAB 0x80 147*0Sstevel@tonic-gate #define PCI_COMM_SERR_ENABLE 0x100 148*0Sstevel@tonic-gate #define PCI_COMM_BACK2BACK_ENAB 0x200 149*0Sstevel@tonic-gate #define PCI_COMM_INTX_DISABLE 0x400 /* INTx emulation disable */ 150*0Sstevel@tonic-gate 151*0Sstevel@tonic-gate /* 152*0Sstevel@tonic-gate * PCI Interrupt pin value 153*0Sstevel@tonic-gate */ 154*0Sstevel@tonic-gate #define PCI_INTA 1 155*0Sstevel@tonic-gate #define PCI_INTB 2 156*0Sstevel@tonic-gate #define PCI_INTC 3 157*0Sstevel@tonic-gate #define PCI_INTD 4 158*0Sstevel@tonic-gate 159*0Sstevel@tonic-gate /* 160*0Sstevel@tonic-gate * PCI status register bits 161*0Sstevel@tonic-gate */ 162*0Sstevel@tonic-gate #define PCI_STAT_INTR 0x8 /* Interrupt state */ 163*0Sstevel@tonic-gate #define PCI_STAT_CAP 0x10 /* Implements Capabilities */ 164*0Sstevel@tonic-gate #define PCI_STAT_66MHZ 0x20 /* 66 MHz capable */ 165*0Sstevel@tonic-gate #define PCI_STAT_UDF 0x40 /* UDF supported */ 166*0Sstevel@tonic-gate #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */ 167*0Sstevel@tonic-gate #define PCI_STAT_S_PERROR 0x100 /* Data Parity Reported */ 168*0Sstevel@tonic-gate #define PCI_STAT_DEVSELT 0x600 /* Device select timing */ 169*0Sstevel@tonic-gate #define PCI_STAT_S_TARG_AB 0x800 /* Signaled Target Abort */ 170*0Sstevel@tonic-gate #define PCI_STAT_R_TARG_AB 0x1000 /* Received Target Abort */ 171*0Sstevel@tonic-gate #define PCI_STAT_R_MAST_AB 0x2000 /* Received Master Abort */ 172*0Sstevel@tonic-gate #define PCI_STAT_S_SYSERR 0x4000 /* Signaled System Error */ 173*0Sstevel@tonic-gate #define PCI_STAT_PERROR 0x8000 /* Detected Parity Error */ 174*0Sstevel@tonic-gate 175*0Sstevel@tonic-gate /* 176*0Sstevel@tonic-gate * DEVSEL timing values 177*0Sstevel@tonic-gate */ 178*0Sstevel@tonic-gate #define PCI_STAT_DEVSELT_FAST 0x0000 179*0Sstevel@tonic-gate #define PCI_STAT_DEVSELT_MEDIUM 0x0200 180*0Sstevel@tonic-gate #define PCI_STAT_DEVSELT_SLOW 0x0400 181*0Sstevel@tonic-gate 182*0Sstevel@tonic-gate /* 183*0Sstevel@tonic-gate * BIST values 184*0Sstevel@tonic-gate */ 185*0Sstevel@tonic-gate #define PCI_BIST_SUPPORTED 0x80 186*0Sstevel@tonic-gate #define PCI_BIST_GO 0x40 187*0Sstevel@tonic-gate #define PCI_BIST_RESULT_M 0x0f 188*0Sstevel@tonic-gate #define PCI_BIST_RESULT_OK 0x00 189*0Sstevel@tonic-gate 190*0Sstevel@tonic-gate /* 191*0Sstevel@tonic-gate * PCI class codes 192*0Sstevel@tonic-gate */ 193*0Sstevel@tonic-gate #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */ 194*0Sstevel@tonic-gate #define PCI_CLASS_MASS 0x1 /* Mass storage Controller class */ 195*0Sstevel@tonic-gate #define PCI_CLASS_NET 0x2 /* Network Controller class */ 196*0Sstevel@tonic-gate #define PCI_CLASS_DISPLAY 0x3 /* Display Controller class */ 197*0Sstevel@tonic-gate #define PCI_CLASS_MM 0x4 /* Multimedia Controller class */ 198*0Sstevel@tonic-gate #define PCI_CLASS_MEM 0x5 /* Memory Controller class */ 199*0Sstevel@tonic-gate #define PCI_CLASS_BRIDGE 0x6 /* Bridge Controller class */ 200*0Sstevel@tonic-gate #define PCI_CLASS_COMM 0x7 /* Communications Controller class */ 201*0Sstevel@tonic-gate #define PCI_CLASS_PERIPH 0x8 /* Peripheral Controller class */ 202*0Sstevel@tonic-gate #define PCI_CLASS_INPUT 0x9 /* Input Device class */ 203*0Sstevel@tonic-gate #define PCI_CLASS_DOCK 0xa /* Docking Station class */ 204*0Sstevel@tonic-gate #define PCI_CLASS_PROCESSOR 0xb /* Processor class */ 205*0Sstevel@tonic-gate #define PCI_CLASS_SERIALBUS 0xc /* Serial Bus class */ 206*0Sstevel@tonic-gate #define PCI_CLASS_WIRELESS 0xd /* Wireless Controller class */ 207*0Sstevel@tonic-gate #define PCI_CLASS_INTIO 0xe /* Intelligent IO Controller class */ 208*0Sstevel@tonic-gate #define PCI_CLASS_SATELLITE 0xf /* Satellite Communication class */ 209*0Sstevel@tonic-gate #define PCI_CLASS_CRYPT 0x10 /* Encrytion/Decryption class */ 210*0Sstevel@tonic-gate #define PCI_CLASS_SIGNAL 0x11 /* Signal Processing class */ 211*0Sstevel@tonic-gate 212*0Sstevel@tonic-gate /* 213*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x0 (no new devices should use this code). 214*0Sstevel@tonic-gate */ 215*0Sstevel@tonic-gate #define PCI_NONE_NOTVGA 0x0 /* All devices except VGA compatible */ 216*0Sstevel@tonic-gate #define PCI_NONE_VGA 0x1 /* VGA compatible */ 217*0Sstevel@tonic-gate 218*0Sstevel@tonic-gate /* 219*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x1 (mass storage controllers) 220*0Sstevel@tonic-gate */ 221*0Sstevel@tonic-gate #define PCI_MASS_SCSI 0x0 /* SCSI bus Controller */ 222*0Sstevel@tonic-gate #define PCI_MASS_IDE 0x1 /* IDE Controller */ 223*0Sstevel@tonic-gate #define PCI_MASS_FD 0x2 /* floppy disk Controller */ 224*0Sstevel@tonic-gate #define PCI_MASS_IPI 0x3 /* IPI bus Controller */ 225*0Sstevel@tonic-gate #define PCI_MASS_RAID 0x4 /* RAID Controller */ 226*0Sstevel@tonic-gate #define PCI_MASS_ATA 0x5 /* ATA Controller */ 227*0Sstevel@tonic-gate #define PCI_MASS_SATA 0x6 /* Serial ATA */ 228*0Sstevel@tonic-gate #define PCI_MASS_OTHER 0x80 /* Other Mass Storage Controller */ 229*0Sstevel@tonic-gate 230*0Sstevel@tonic-gate /* 231*0Sstevel@tonic-gate * programming interface for IDE (subclass 1) 232*0Sstevel@tonic-gate */ 233*0Sstevel@tonic-gate #define PCI_IDE_IF_NATIVE_PRI 0x1 /* primary channel is native */ 234*0Sstevel@tonic-gate #define PCI_IDE_IF_PROG_PRI 0x2 /* primary can operate in either mode */ 235*0Sstevel@tonic-gate #define PCI_IDE_IF_NATIVE_SEC 0x4 /* secondary channel is native */ 236*0Sstevel@tonic-gate #define PCI_IDE_IF_PROG_SEC 0x8 /* sec. can operate in either mode */ 237*0Sstevel@tonic-gate #define PCI_IDE_IF_MASK 0xf /* programming interface mask */ 238*0Sstevel@tonic-gate 239*0Sstevel@tonic-gate 240*0Sstevel@tonic-gate /* 241*0Sstevel@tonic-gate * programming interface for ATA (subclass 5) 242*0Sstevel@tonic-gate */ 243*0Sstevel@tonic-gate #define PCI_ATA_IF_SINGLE_DMA 0x20 /* ATA controller with single DMA */ 244*0Sstevel@tonic-gate #define PCI_ATA_IF_CHAINED_DMA 0x30 /* ATA controller with chained DMA */ 245*0Sstevel@tonic-gate 246*0Sstevel@tonic-gate /* 247*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x2 (Network controllers) 248*0Sstevel@tonic-gate */ 249*0Sstevel@tonic-gate #define PCI_NET_ENET 0x0 /* Ethernet Controller */ 250*0Sstevel@tonic-gate #define PCI_NET_TOKEN 0x1 /* Token Ring Controller */ 251*0Sstevel@tonic-gate #define PCI_NET_FDDI 0x2 /* FDDI Controller */ 252*0Sstevel@tonic-gate #define PCI_NET_ATM 0x3 /* ATM Controller */ 253*0Sstevel@tonic-gate #define PCI_NET_ISDN 0x4 /* ISDN Controller */ 254*0Sstevel@tonic-gate #define PCI_NET_WFIP 0x5 /* WorldFip Controller */ 255*0Sstevel@tonic-gate #define PCI_NET_PICMG 0x6 /* PICMG 2.14 Multi Computing */ 256*0Sstevel@tonic-gate #define PCI_NET_OTHER 0x80 /* Other Network Controller */ 257*0Sstevel@tonic-gate 258*0Sstevel@tonic-gate /* 259*0Sstevel@tonic-gate * PCI Sub-class codes - base class 03 (display controllers) 260*0Sstevel@tonic-gate */ 261*0Sstevel@tonic-gate #define PCI_DISPLAY_VGA 0x0 /* VGA device */ 262*0Sstevel@tonic-gate #define PCI_DISPLAY_XGA 0x1 /* XGA device */ 263*0Sstevel@tonic-gate #define PCI_DISPLAY_3D 0x2 /* 3D controller */ 264*0Sstevel@tonic-gate #define PCI_DISPLAY_OTHER 0x80 /* Other Display Device */ 265*0Sstevel@tonic-gate 266*0Sstevel@tonic-gate /* 267*0Sstevel@tonic-gate * programming interface for display for display class (subclass 0) VGA ctrlrs 268*0Sstevel@tonic-gate */ 269*0Sstevel@tonic-gate #define PCI_DISPLAY_IF_VGA 0x0 /* VGA compatible */ 270*0Sstevel@tonic-gate #define PCI_DISPLAY_IF_8514 0x1 /* 8514 compatible */ 271*0Sstevel@tonic-gate 272*0Sstevel@tonic-gate /* 273*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x4 (multi-media devices) 274*0Sstevel@tonic-gate */ 275*0Sstevel@tonic-gate #define PCI_MM_VIDEO 0x0 /* Video device */ 276*0Sstevel@tonic-gate #define PCI_MM_AUDIO 0x1 /* Audio device */ 277*0Sstevel@tonic-gate #define PCI_MM_TELEPHONY 0x2 /* Computer Telephony device */ 278*0Sstevel@tonic-gate #define PCI_MM_OTHER 0x80 /* Other Multimedia Device */ 279*0Sstevel@tonic-gate 280*0Sstevel@tonic-gate /* 281*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x5 (memory controllers) 282*0Sstevel@tonic-gate */ 283*0Sstevel@tonic-gate #define PCI_MEM_RAM 0x0 /* RAM device */ 284*0Sstevel@tonic-gate #define PCI_MEM_FLASH 0x1 /* FLASH device */ 285*0Sstevel@tonic-gate #define PCI_MEM_OTHER 0x80 /* Other Memory Controller */ 286*0Sstevel@tonic-gate 287*0Sstevel@tonic-gate /* 288*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x6 (Bridge devices) 289*0Sstevel@tonic-gate */ 290*0Sstevel@tonic-gate #define PCI_BRIDGE_HOST 0x0 /* Host/PCI Bridge */ 291*0Sstevel@tonic-gate #define PCI_BRIDGE_ISA 0x1 /* PCI/ISA Bridge */ 292*0Sstevel@tonic-gate #define PCI_BRIDGE_EISA 0x2 /* PCI/EISA Bridge */ 293*0Sstevel@tonic-gate #define PCI_BRIDGE_MC 0x3 /* PCI/MC Bridge */ 294*0Sstevel@tonic-gate #define PCI_BRIDGE_PCI 0x4 /* PCI/PCI Bridge */ 295*0Sstevel@tonic-gate #define PCI_BRIDGE_PCMCIA 0x5 /* PCI/PCMCIA Bridge */ 296*0Sstevel@tonic-gate #define PCI_BRIDGE_NUBUS 0x6 /* PCI/NUBUS Bridge */ 297*0Sstevel@tonic-gate #define PCI_BRIDGE_CARDBUS 0x7 /* PCI/CARDBUS Bridge */ 298*0Sstevel@tonic-gate #define PCI_BRIDGE_RACE 0x8 /* RACE-way Bridge */ 299*0Sstevel@tonic-gate #define PCI_BRIDGE_STPCI 0x9 /* Semi-transparent PCI/PCI Bridge */ 300*0Sstevel@tonic-gate #define PCI_BRIDGE_IB 0xA /* InfiniBand/PCI host Bridge */ 301*0Sstevel@tonic-gate #define PCI_BRIDGE_OTHER 0x80 /* PCI/Other Bridge Device */ 302*0Sstevel@tonic-gate 303*0Sstevel@tonic-gate /* 304*0Sstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 4) PCI-PCI bridge 305*0Sstevel@tonic-gate */ 306*0Sstevel@tonic-gate #define PCI_BRIDGE_PCI_IF_PCI2PCI 0x0 /* PCI-PCI bridge */ 307*0Sstevel@tonic-gate #define PCI_BRIDGE_PCI_IF_SUBDECODE 0x1 /* Subtractive Decode */ 308*0Sstevel@tonic-gate /* PCI/PCI bridge */ 309*0Sstevel@tonic-gate 310*0Sstevel@tonic-gate /* 311*0Sstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 08) RACEway bridge 312*0Sstevel@tonic-gate */ 313*0Sstevel@tonic-gate #define PCI_BRIDGE_RACE_IF_TRANSPARENT 0x0 /* Transport mode */ 314*0Sstevel@tonic-gate #define PCI_BRIDGE_RACE_IF_ENDPOINT 0x1 /* Endpoint mode */ 315*0Sstevel@tonic-gate 316*0Sstevel@tonic-gate /* 317*0Sstevel@tonic-gate * programming interface for Bridges class 0x6 (subclass 09) 318*0Sstevel@tonic-gate * Semi-transparent PCI-to-PCI bridge 319*0Sstevel@tonic-gate */ 320*0Sstevel@tonic-gate #define PCI_BRIDGE_STPCI_IF_PRIMARY 0x40 /* primary PCI side bus */ 321*0Sstevel@tonic-gate /* facing system processor */ 322*0Sstevel@tonic-gate #define PCI_BRIDGE_STPCI_IF_SECONDARY 0x80 /* secondary PCI side bus */ 323*0Sstevel@tonic-gate /* facing system processor */ 324*0Sstevel@tonic-gate 325*0Sstevel@tonic-gate /* 326*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x7 (communication devices) 327*0Sstevel@tonic-gate */ 328*0Sstevel@tonic-gate #define PCI_COMM_GENERIC_XT 0x0 /* XT Compatible Serial Controller */ 329*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL 0x1 /* Parallel Port Controller */ 330*0Sstevel@tonic-gate #define PCI_COMM_MSC 0x2 /* Multiport Serial Controller */ 331*0Sstevel@tonic-gate #define PCI_COMM_MODEM 0x3 /* Modem Controller */ 332*0Sstevel@tonic-gate #define PCI_COMM_GPIB 0x4 /* GPIB Controller */ 333*0Sstevel@tonic-gate #define PCI_COMM_SMARTCARD 0x5 /* Smart Card Controller */ 334*0Sstevel@tonic-gate #define PCI_COMM_OTHER 0x80 /* Other Communications Controller */ 335*0Sstevel@tonic-gate 336*0Sstevel@tonic-gate /* 337*0Sstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x0 (Serial) 338*0Sstevel@tonic-gate */ 339*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_GENERIC 0x0 /* Generic XT-compat serial */ 340*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16450 0x1 /* 16450-compat serial ctrlr */ 341*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16550 0x2 /* 16550-compat serial ctrlr */ 342*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16650 0x3 /* 16650-compat serial ctrlr */ 343*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16750 0x4 /* 16750-compat serial ctrlr */ 344*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16850 0x5 /* 16850-compat serial ctrlr */ 345*0Sstevel@tonic-gate #define PCI_COMM_SERIAL_IF_16950 0x6 /* 16950-compat serial ctrlr */ 346*0Sstevel@tonic-gate 347*0Sstevel@tonic-gate /* 348*0Sstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x1 (Parallel) 349*0Sstevel@tonic-gate */ 350*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL_IF_GENERIC 0x0 /* Generic Parallel port */ 351*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL_IF_BIDIRECT 0x1 /* Bi-directional Parallel */ 352*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL_IF_ECP 0x2 /* ECP 1.X Parallel port */ 353*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL_IF_1284 0x3 /* IEEE 1284 Parallel port */ 354*0Sstevel@tonic-gate #define PCI_COMM_PARALLEL_IF_1284_TARG 0xFE /* IEEE 1284 target device */ 355*0Sstevel@tonic-gate 356*0Sstevel@tonic-gate /* 357*0Sstevel@tonic-gate * Programming interfaces for class 0x7 / subclass 0x3 (Modem) 358*0Sstevel@tonic-gate */ 359*0Sstevel@tonic-gate #define PCI_COMM_MODEM_IF_GENERIC 0x0 /* Generic Modem */ 360*0Sstevel@tonic-gate #define PCI_COMM_MODEM_IF_HAYES_16450 0x1 /* Hayes 16450-compat Modem */ 361*0Sstevel@tonic-gate #define PCI_COMM_MODEM_IF_HAYES_16550 0x2 /* Hayes 16550-compat Modem */ 362*0Sstevel@tonic-gate #define PCI_COMM_MODEM_IF_HAYES_16650 0x3 /* Hayes 16650-compat Modem */ 363*0Sstevel@tonic-gate #define PCI_COMM_MODEM_IF_HAYES_16750 0x4 /* Hayes 16750-compat Modem */ 364*0Sstevel@tonic-gate 365*0Sstevel@tonic-gate /* 366*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x8 367*0Sstevel@tonic-gate */ 368*0Sstevel@tonic-gate #define PCI_PERIPH_PIC 0x0 /* Generic PIC */ 369*0Sstevel@tonic-gate #define PCI_PERIPH_DMA 0x1 /* Generic DMA Controller */ 370*0Sstevel@tonic-gate #define PCI_PERIPH_TIMER 0x2 /* Generic System Timer Controller */ 371*0Sstevel@tonic-gate #define PCI_PERIPH_RTC 0x3 /* Generic RTC Controller */ 372*0Sstevel@tonic-gate #define PCI_PERIPH_HPC 0x3 /* Generic PCI Hot-Plug Controller */ 373*0Sstevel@tonic-gate #define PCI_PERIPH_OTHER 0x80 /* Other System Peripheral */ 374*0Sstevel@tonic-gate 375*0Sstevel@tonic-gate /* 376*0Sstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x0 (interrupt controller) 377*0Sstevel@tonic-gate */ 378*0Sstevel@tonic-gate #define PCI_PERIPH_PIC_IF_GENERIC 0x0 /* Generic 8259 APIC */ 379*0Sstevel@tonic-gate #define PCI_PERIPH_PIC_IF_ISA 0x1 /* ISA PIC */ 380*0Sstevel@tonic-gate #define PCI_PERIPH_PIC_IF_EISA 0x2 /* EISA PIC */ 381*0Sstevel@tonic-gate #define PCI_PERIPH_PIC_IF_IO_APIC 0x10 /* I/O APIC interrupt ctrlr */ 382*0Sstevel@tonic-gate #define PCI_PERIPH_PIC_IF_IOX_APIC 0x20 /* I/O(x) APIC intr ctrlr */ 383*0Sstevel@tonic-gate 384*0Sstevel@tonic-gate /* 385*0Sstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x1 (DMA controller) 386*0Sstevel@tonic-gate */ 387*0Sstevel@tonic-gate #define PCI_PERIPH_DMA_IF_GENERIC 0x0 /* Generic 8237 DMA ctrlr */ 388*0Sstevel@tonic-gate #define PCI_PERIPH_DMA_IF_ISA 0x1 /* ISA DMA ctrlr */ 389*0Sstevel@tonic-gate #define PCI_PERIPH_DMA_IF_EISA 0x2 /* EISA DMA ctrlr */ 390*0Sstevel@tonic-gate 391*0Sstevel@tonic-gate /* 392*0Sstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x2 (timer) 393*0Sstevel@tonic-gate */ 394*0Sstevel@tonic-gate #define PCI_PERIPH_TIMER_IF_GENERIC 0x0 /* Generic 8254 system timer */ 395*0Sstevel@tonic-gate #define PCI_PERIPH_TIMER_IF_ISA 0x1 /* ISA system timers */ 396*0Sstevel@tonic-gate #define PCI_PERIPH_TIMER_IF_EISA 0x2 /* EISA system timers (two) */ 397*0Sstevel@tonic-gate 398*0Sstevel@tonic-gate /* 399*0Sstevel@tonic-gate * Programming interfaces for class 0x8 / subclass 0x3 (realtime clock) 400*0Sstevel@tonic-gate */ 401*0Sstevel@tonic-gate #define PCI_PERIPH_RTC_IF_GENERIC 0x0 /* Generic RTC controller */ 402*0Sstevel@tonic-gate #define PCI_PERIPH_RTC_IF_ISA 0x1 /* ISA RTC controller */ 403*0Sstevel@tonic-gate 404*0Sstevel@tonic-gate /* 405*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x9 406*0Sstevel@tonic-gate */ 407*0Sstevel@tonic-gate #define PCI_INPUT_KEYBOARD 0x0 /* Keyboard Controller */ 408*0Sstevel@tonic-gate #define PCI_INPUT_DIGITIZ 0x1 /* Digitizer (Pen) */ 409*0Sstevel@tonic-gate #define PCI_INPUT_MOUSE 0x2 /* Mouse Controller */ 410*0Sstevel@tonic-gate #define PCI_INPUT_SCANNER 0x3 /* Scanner Controller */ 411*0Sstevel@tonic-gate #define PCI_INPUT_GAMEPORT 0x4 /* Gameport Controller */ 412*0Sstevel@tonic-gate #define PCI_INPUT_OTHER 0x80 /* Other Input Controller */ 413*0Sstevel@tonic-gate 414*0Sstevel@tonic-gate /* 415*0Sstevel@tonic-gate * Programming interfaces for class 0x9 / subclass 0x4 (Gameport controller) 416*0Sstevel@tonic-gate */ 417*0Sstevel@tonic-gate #define PCI_INPUT_GAMEPORT_IF_GENERIC 0x00 /* Generic controller */ 418*0Sstevel@tonic-gate #define PCI_INPUT_GAMEPORT_IF_LEGACY 0x10 /* Legacy controller */ 419*0Sstevel@tonic-gate 420*0Sstevel@tonic-gate /* 421*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xa 422*0Sstevel@tonic-gate */ 423*0Sstevel@tonic-gate #define PCI_DOCK_GENERIC 0x00 /* Generic Docking Station */ 424*0Sstevel@tonic-gate #define PCI_DOCK_OTHER 0x80 /* Other Type of Docking Station */ 425*0Sstevel@tonic-gate 426*0Sstevel@tonic-gate /* 427*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xb 428*0Sstevel@tonic-gate */ 429*0Sstevel@tonic-gate #define PCI_PROCESSOR_386 0x0 /* 386 */ 430*0Sstevel@tonic-gate #define PCI_PROCESSOR_486 0x1 /* 486 */ 431*0Sstevel@tonic-gate #define PCI_PROCESSOR_PENT 0x2 /* Pentium */ 432*0Sstevel@tonic-gate #define PCI_PROCESSOR_ALPHA 0x10 /* Alpha */ 433*0Sstevel@tonic-gate #define PCI_PROCESSOR_POWERPC 0x20 /* PowerPC */ 434*0Sstevel@tonic-gate #define PCI_PROCESSOR_MIPS 0x30 /* MIPS */ 435*0Sstevel@tonic-gate #define PCI_PROCESSOR_COPROC 0x40 /* Co-processor */ 436*0Sstevel@tonic-gate 437*0Sstevel@tonic-gate /* 438*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xc (Serial Controllers) 439*0Sstevel@tonic-gate */ 440*0Sstevel@tonic-gate #define PCI_SERIAL_FIRE 0x0 /* FireWire (IEEE 1394) */ 441*0Sstevel@tonic-gate #define PCI_SERIAL_ACCESS 0x1 /* ACCESS.bus */ 442*0Sstevel@tonic-gate #define PCI_SERIAL_SSA 0x2 /* SSA */ 443*0Sstevel@tonic-gate #define PCI_SERIAL_USB 0x3 /* Universal Serial Bus */ 444*0Sstevel@tonic-gate #define PCI_SERIAL_FIBRE 0x4 /* Fibre Channel */ 445*0Sstevel@tonic-gate #define PCI_SERIAL_SMBUS 0x5 /* System Management Bus */ 446*0Sstevel@tonic-gate #define PCI_SERIAL_IB 0x6 /* InfiniBand */ 447*0Sstevel@tonic-gate #define PCI_SERIAL_IPMI 0x7 /* IPMI */ 448*0Sstevel@tonic-gate #define PCI_SERIAL_SERCOS 0x8 /* SERCOS Interface Std (IEC 61491) */ 449*0Sstevel@tonic-gate #define PCI_SERIAL_CANBUS 0x9 /* CANbus */ 450*0Sstevel@tonic-gate 451*0Sstevel@tonic-gate /* 452*0Sstevel@tonic-gate * Programming interfaces for class 0xC / subclass 0x3 (USB controller) 453*0Sstevel@tonic-gate */ 454*0Sstevel@tonic-gate #define PCI_SERIAL_USB_IF_UHCI 0x00 /* UHCI Compliant */ 455*0Sstevel@tonic-gate #define PCI_SERIAL_USB_IF_OHCI 0x10 /* OHCI Compliant */ 456*0Sstevel@tonic-gate #define PCI_SERIAL_USB_IF_EHCI 0x20 /* EHCI Compliant */ 457*0Sstevel@tonic-gate #define PCI_SERIAL_USB_IF_GENERIC 0x80 /* no specific HCD */ 458*0Sstevel@tonic-gate #define PCI_SERIAL_USB_IF_DEVICE 0xFE /* not a HCD */ 459*0Sstevel@tonic-gate 460*0Sstevel@tonic-gate /* 461*0Sstevel@tonic-gate * Programming interfaces for class 0xC / subclass 0x7 (IPMI controller) 462*0Sstevel@tonic-gate */ 463*0Sstevel@tonic-gate #define PCI_SERIAL_IPMI_IF_SMIC 0x0 /* SMIC Interface */ 464*0Sstevel@tonic-gate #define PCI_SERIAL_IPMI_IF_KBD 0x1 /* Keyboard Ctrl Style Intfc */ 465*0Sstevel@tonic-gate #define PCI_SERIAL_IPMI_IF_BTI 0x2 /* Block Transfer Interface */ 466*0Sstevel@tonic-gate 467*0Sstevel@tonic-gate /* 468*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xd (Wireless controllers) 469*0Sstevel@tonic-gate */ 470*0Sstevel@tonic-gate #define PCI_WIRELESS_IRDA 0x0 /* iRDA Compatible Controller */ 471*0Sstevel@tonic-gate #define PCI_WIRELESS_IR 0x1 /* Consumer IR Controller */ 472*0Sstevel@tonic-gate #define PCI_WIRELESS_RF 0x10 /* RF Controller */ 473*0Sstevel@tonic-gate #define PCI_WIRELESS_BLUETOOTH 0x11 /* Bluetooth Controller */ 474*0Sstevel@tonic-gate #define PCI_WIRELESS_BROADBAND 0x12 /* Broadband Controller */ 475*0Sstevel@tonic-gate #define PCI_WIRELESS_80211A 0x20 /* Ethernet 802.11a 5 GHz */ 476*0Sstevel@tonic-gate #define PCI_WIRELESS_80211B 0x21 /* Ethernet 802.11b 2.4 GHz */ 477*0Sstevel@tonic-gate #define PCI_WIRELESS_OTHER 0x80 /* Other Wireless Controllers */ 478*0Sstevel@tonic-gate 479*0Sstevel@tonic-gate /* 480*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xe (Intelligent I/O controllers) 481*0Sstevel@tonic-gate */ 482*0Sstevel@tonic-gate #define PCI_INTIO_I20 0x1 /* I20 Arch Spec 1.0 */ 483*0Sstevel@tonic-gate 484*0Sstevel@tonic-gate /* 485*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0xf (Satellite Communication controllers) 486*0Sstevel@tonic-gate */ 487*0Sstevel@tonic-gate #define PCI_SATELLITE_COMM_TV 0x01 /* TV */ 488*0Sstevel@tonic-gate #define PCI_SATELLITE_COMM_AUDIO 0x02 /* Audio */ 489*0Sstevel@tonic-gate #define PCI_SATELLITE_COMM_VOICE 0x03 /* Voice */ 490*0Sstevel@tonic-gate #define PCI_SATELLITE_COMM_DATA 0x04 /* DATA */ 491*0Sstevel@tonic-gate 492*0Sstevel@tonic-gate /* 493*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x10 (Encryption/Decryption controllers) 494*0Sstevel@tonic-gate */ 495*0Sstevel@tonic-gate #define PCI_CRYPT_NETWORK 0x00 /* Network and Computing */ 496*0Sstevel@tonic-gate #define PCI_CRYPT_ENTERTAINMENT 0x10 /* Entertainment en/decrypt */ 497*0Sstevel@tonic-gate #define PCI_CRYPT_OTHER 0x80 /* Other en/decryption ctrlrs */ 498*0Sstevel@tonic-gate 499*0Sstevel@tonic-gate /* 500*0Sstevel@tonic-gate * PCI Sub-class codes - base class 0x11 (Signal Processing controllers) 501*0Sstevel@tonic-gate */ 502*0Sstevel@tonic-gate #define PCI_SIGNAL_DPIO 0x00 /* DPIO modules */ 503*0Sstevel@tonic-gate #define PCI_SIGNAL_PERF_COUNTERS 0x01 /* Performance counters */ 504*0Sstevel@tonic-gate #define PCI_SIGNAL_COMM_SYNC 0x10 /* Comm. synchronization plus */ 505*0Sstevel@tonic-gate /* time and freq test ctrlr */ 506*0Sstevel@tonic-gate #define PCI_SIGNAL_MANAGEMENT 0x20 /* Management card */ 507*0Sstevel@tonic-gate #define PCI_SIGNAL_OTHER 0x80 /* DSP/DAP controller */ 508*0Sstevel@tonic-gate 509*0Sstevel@tonic-gate /* PCI header decode */ 510*0Sstevel@tonic-gate #define PCI_HEADER_MULTI 0x80 /* multi-function device */ 511*0Sstevel@tonic-gate #define PCI_HEADER_ZERO 0x00 /* type zero PCI header */ 512*0Sstevel@tonic-gate #define PCI_HEADER_ONE 0x01 /* type one PCI header */ 513*0Sstevel@tonic-gate #define PCI_HEADER_TWO 0x02 /* type two PCI header */ 514*0Sstevel@tonic-gate #define PCI_HEADER_PPB PCI_HEADER_ONE /* type one PCI to PCI Bridge */ 515*0Sstevel@tonic-gate #define PCI_HEADER_CARDBUS PCI_HEADER_TWO /* type one PCI header */ 516*0Sstevel@tonic-gate 517*0Sstevel@tonic-gate #define PCI_HEADER_TYPE_M 0x7f /* type mask for header */ 518*0Sstevel@tonic-gate 519*0Sstevel@tonic-gate /* 520*0Sstevel@tonic-gate * Base register bit definitions. 521*0Sstevel@tonic-gate */ 522*0Sstevel@tonic-gate #define PCI_BASE_SPACE_M 0x1 /* memory space indicator */ 523*0Sstevel@tonic-gate #define PCI_BASE_SPACE_IO 0x1 /* IO space */ 524*0Sstevel@tonic-gate #define PCI_BASE_SPACE_MEM 0x0 /* memory space */ 525*0Sstevel@tonic-gate 526*0Sstevel@tonic-gate #define PCI_BASE_TYPE_MEM 0x0 /* 32-bit memory address */ 527*0Sstevel@tonic-gate #define PCI_BASE_TYPE_LOW 0x2 /* less than 1Mb address */ 528*0Sstevel@tonic-gate #define PCI_BASE_TYPE_ALL 0x4 /* 64-bit memory address */ 529*0Sstevel@tonic-gate #define PCI_BASE_TYPE_RES 0x6 /* reserved */ 530*0Sstevel@tonic-gate 531*0Sstevel@tonic-gate #define PCI_BASE_TYPE_M 0x00000006 /* type indicator mask */ 532*0Sstevel@tonic-gate #define PCI_BASE_PREF_M 0x00000008 /* prefetch mask */ 533*0Sstevel@tonic-gate #define PCI_BASE_M_ADDR_M 0xfffffff0 /* memory address mask */ 534*0Sstevel@tonic-gate #define PCI_BASE_IO_ADDR_M 0xfffffffe /* I/O address mask */ 535*0Sstevel@tonic-gate 536*0Sstevel@tonic-gate #define PCI_BASE_ROM_ADDR_M 0xfffff800 /* ROM address mask */ 537*0Sstevel@tonic-gate #define PCI_BASE_ROM_ENABLE 0x00000001 /* ROM decoder enable */ 538*0Sstevel@tonic-gate 539*0Sstevel@tonic-gate /* 540*0Sstevel@tonic-gate * Capabilities linked list entry offsets 541*0Sstevel@tonic-gate */ 542*0Sstevel@tonic-gate #define PCI_CAP_ID 0x0 /* capability identifier, 1 byte */ 543*0Sstevel@tonic-gate #define PCI_CAP_NEXT_PTR 0x1 /* next entry pointer, 1 byte */ 544*0Sstevel@tonic-gate #define PCI_CAP_MAX_PTR 0x30 /* maximum number of cap pointers */ 545*0Sstevel@tonic-gate #define PCI_CAP_PTR_OFF 0x40 /* minimum cap pointer offset */ 546*0Sstevel@tonic-gate #define PCI_CAP_PTR_MASK 0xFC /* mask for capability pointer */ 547*0Sstevel@tonic-gate 548*0Sstevel@tonic-gate /* 549*0Sstevel@tonic-gate * Capability identifier values 550*0Sstevel@tonic-gate */ 551*0Sstevel@tonic-gate #define PCI_CAP_ID_PM 0x1 /* power management entry */ 552*0Sstevel@tonic-gate #define PCI_CAP_ID_AGP 0x2 /* AGP supported */ 553*0Sstevel@tonic-gate #define PCI_CAP_ID_VPD 0x3 /* VPD supported */ 554*0Sstevel@tonic-gate #define PCI_CAP_ID_SLOT_ID 0x4 /* Slot Identification supported */ 555*0Sstevel@tonic-gate #define PCI_CAP_ID_MSI 0x5 /* MSI supported */ 556*0Sstevel@tonic-gate #define PCI_CAP_ID_cPCI_HS 0x6 /* CompactPCI Host Swap supported */ 557*0Sstevel@tonic-gate #define PCI_CAP_ID_PCIX 0x7 /* PCI-X supported */ 558*0Sstevel@tonic-gate #define PCI_CAP_ID_HT 0x8 /* HyperTransport supported */ 559*0Sstevel@tonic-gate #define PCI_CAP_ID_VS 0x9 /* Vendor Specific */ 560*0Sstevel@tonic-gate #define PCI_CAP_ID_DEBUG_PORT 0xA /* Debug Port supported */ 561*0Sstevel@tonic-gate #define PCI_CAP_ID_cPCI_CRC 0xB /* CompactPCI central resource ctrl */ 562*0Sstevel@tonic-gate #define PCI_CAP_ID_PCI_HOTPLUG 0xC /* PCI Hot Plug supported */ 563*0Sstevel@tonic-gate #define PCI_CAP_ID_AGP_8X 0xE /* AGP 8X supported */ 564*0Sstevel@tonic-gate #define PCI_CAP_ID_SECURE_DEV 0xF /* Secure Device supported */ 565*0Sstevel@tonic-gate #define PCI_CAP_ID_PCI_E 0x10 /* PCI Express supported */ 566*0Sstevel@tonic-gate #define PCI_CAP_ID_MSI_X 0x11 /* MSI-X supported */ 567*0Sstevel@tonic-gate 568*0Sstevel@tonic-gate /* 569*0Sstevel@tonic-gate * Capability next entry pointer values 570*0Sstevel@tonic-gate */ 571*0Sstevel@tonic-gate #define PCI_CAP_NEXT_PTR_NULL 0x0 /* no more entries in the list */ 572*0Sstevel@tonic-gate 573*0Sstevel@tonic-gate /* 574*0Sstevel@tonic-gate * PCI power management (PM) capability entry offsets 575*0Sstevel@tonic-gate */ 576*0Sstevel@tonic-gate #define PCI_PMCAP 0x2 /* PM capabilities, 2 bytes */ 577*0Sstevel@tonic-gate #define PCI_PMCSR 0x4 /* PM control/status reg, 2 bytes */ 578*0Sstevel@tonic-gate #define PCI_PMCSR_BSE 0x6 /* PCI-PCI bridge extensions, 1 byte */ 579*0Sstevel@tonic-gate #define PCI_PMDATA 0x7 /* PM data, 1 byte */ 580*0Sstevel@tonic-gate 581*0Sstevel@tonic-gate /* 582*0Sstevel@tonic-gate * PM capabilities values - 2 bytes 583*0Sstevel@tonic-gate */ 584*0Sstevel@tonic-gate #define PCI_PMCAP_VER_1_0 0x1 /* PCI PM spec 1.0 */ 585*0Sstevel@tonic-gate #define PCI_PMCAP_VER_1_1 0x2 /* PCI PM spec 1.1 */ 586*0Sstevel@tonic-gate #define PCI_PMCAP_VER_MASK 0x7 /* version mask */ 587*0Sstevel@tonic-gate #define PCI_PMCAP_PME_CLOCK 0x8 /* needs PCI clock for PME */ 588*0Sstevel@tonic-gate #define PCI_PMCAP_DSI 0x20 /* needs device specific init */ 589*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_SELF 0x0 /* 0 aux current - self powered */ 590*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_55mA 0x40 /* 55 mA aux current */ 591*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_100mA 0x80 /* 100 mA aux current */ 592*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_160mA 0xc0 /* 160 mA aux current */ 593*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_220mA 0x100 /* 220 mA aux current */ 594*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_270mA 0x140 /* 270 mA aux current */ 595*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_320mA 0x180 /* 320 mA aux current */ 596*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_375mA 0x1c0 /* 375 mA aux current */ 597*0Sstevel@tonic-gate #define PCI_PMCAP_AUX_CUR_MASK 0x1c0 /* 3.3Vaux aux current needs */ 598*0Sstevel@tonic-gate #define PCI_PMCAP_D1 0x200 /* D1 state supported */ 599*0Sstevel@tonic-gate #define PCI_PMCAP_D2 0x400 /* D2 state supported */ 600*0Sstevel@tonic-gate #define PCI_PMCAP_D0_PME 0x800 /* PME from D0 */ 601*0Sstevel@tonic-gate #define PCI_PMCAP_D1_PME 0x1000 /* PME from D1 */ 602*0Sstevel@tonic-gate #define PCI_PMCAP_D2_PME 0x2000 /* PME from D2 */ 603*0Sstevel@tonic-gate #define PCI_PMCAP_D3HOT_PME 0x4000 /* PME from D3hot */ 604*0Sstevel@tonic-gate #define PCI_PMCAP_D3COLD_PME 0x8000 /* PME from D3cold */ 605*0Sstevel@tonic-gate #define PCI_PMCAP_PME_MASK 0xf800 /* PME support mask */ 606*0Sstevel@tonic-gate 607*0Sstevel@tonic-gate /* 608*0Sstevel@tonic-gate * PM control/status values - 2 bytes 609*0Sstevel@tonic-gate */ 610*0Sstevel@tonic-gate #define PCI_PMCSR_D0 0x0 /* power state D0 */ 611*0Sstevel@tonic-gate #define PCI_PMCSR_D1 0x1 /* power state D1 */ 612*0Sstevel@tonic-gate #define PCI_PMCSR_D2 0x2 /* power state D2 */ 613*0Sstevel@tonic-gate #define PCI_PMCSR_D3HOT 0x3 /* power state D3hot */ 614*0Sstevel@tonic-gate #define PCI_PMCSR_STATE_MASK 0x3 /* power state mask */ 615*0Sstevel@tonic-gate #define PCI_PMCSR_PME_EN 0x100 /* enable PME assertion */ 616*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D0_PWR_C 0x0 /* D0 power consumed */ 617*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D1_PWR_C 0x200 /* D1 power consumed */ 618*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D2_PWR_C 0x400 /* D2 power consumed */ 619*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D3_PWR_C 0x600 /* D3 power consumed */ 620*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D0_PWR_D 0x800 /* D0 power dissipated */ 621*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D1_PWR_D 0xa00 /* D1 power dissipated */ 622*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D2_PWR_D 0xc00 /* D2 power dissipated */ 623*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_D3_PWR_D 0xe00 /* D3 power dissipated */ 624*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_COM_C 0x1000 /* common power consumption */ 625*0Sstevel@tonic-gate #define PCI_PMCSR_DSEL_MASK 0x1e00 /* data select mask */ 626*0Sstevel@tonic-gate #define PCI_PMCSR_DSCL_UNKNOWN 0x0 /* data scale unknown */ 627*0Sstevel@tonic-gate #define PCI_PMCSR_DSCL_1_BY_10 0x2000 /* data scale 0.1x */ 628*0Sstevel@tonic-gate #define PCI_PMCSR_DSCL_1_BY_100 0x4000 /* data scale 0.01x */ 629*0Sstevel@tonic-gate #define PCI_PMCSR_DSCL_1_BY_1000 0x6000 /* data scale 0.001x */ 630*0Sstevel@tonic-gate #define PCI_PMCSR_DSCL_MASK 0x6000 /* data scale mask */ 631*0Sstevel@tonic-gate #define PCI_PMCSR_PME_STAT 0x8000 /* PME status */ 632*0Sstevel@tonic-gate 633*0Sstevel@tonic-gate /* 634*0Sstevel@tonic-gate * PM PMCSR PCI to PCI bridge support extension values - 1 byte 635*0Sstevel@tonic-gate */ 636*0Sstevel@tonic-gate #define PCI_PMCSR_BSE_B2_B3 0x40 /* bridge D3hot -> secondary B2 */ 637*0Sstevel@tonic-gate #define PCI_PMCSR_BSE_BPCC_EN 0x80 /* bus power/clock control enabled */ 638*0Sstevel@tonic-gate 639*0Sstevel@tonic-gate /* 640*0Sstevel@tonic-gate * PCI-X capability related definitions 641*0Sstevel@tonic-gate */ 642*0Sstevel@tonic-gate #define PCI_PCIX_COMMAND 0x2 /* Command register offset */ 643*0Sstevel@tonic-gate 644*0Sstevel@tonic-gate #define PCI_PCIX_VER_MASK 0x3000 /* Bits 12 and 13 */ 645*0Sstevel@tonic-gate #define PCI_PCIX_VER_0 0x0000 /* PCIX cap list item version 0 */ 646*0Sstevel@tonic-gate #define PCI_PCIX_VER_1 0x1000 /* PCIX cap list item version 1 */ 647*0Sstevel@tonic-gate #define PCI_PCIX_VER_2 0x2000 /* PCIX cap list item version 2 */ 648*0Sstevel@tonic-gate 649*0Sstevel@tonic-gate /* 650*0Sstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability entry offsets for 32-bit 651*0Sstevel@tonic-gate */ 652*0Sstevel@tonic-gate #define PCI_MSI_CTRL 0x02 /* MSI control register, 2 bytes */ 653*0Sstevel@tonic-gate #define PCI_MSI_ADDR_OFFSET 0x04 /* MSI 32-bit msg address, 4 bytes */ 654*0Sstevel@tonic-gate #define PCI_MSI_32BIT_DATA 0x08 /* MSI 32-bit msg data, 2 bytes */ 655*0Sstevel@tonic-gate #define PCI_MSI_32BIT_MASK 0x0C /* MSI 32-bit mask bits, 4 bytes */ 656*0Sstevel@tonic-gate #define PCI_MSI_32BIT_PENDING 0x10 /* MSI 32-bit pending bits, 4 bytes */ 657*0Sstevel@tonic-gate 658*0Sstevel@tonic-gate /* 659*0Sstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability entry offsets for 64-bit 660*0Sstevel@tonic-gate */ 661*0Sstevel@tonic-gate #define PCI_MSI_64BIT_DATA 0x0C /* MSI 64-bit msg data, 2 bytes */ 662*0Sstevel@tonic-gate #define PCI_MSI_64BIT_MASKBITS 0x10 /* MSI 64-bit mask bits, 4 bytes */ 663*0Sstevel@tonic-gate #define PCI_MSI_64BIT_PENDING 0x14 /* MSI 64-bit pending bits, 4 bytes */ 664*0Sstevel@tonic-gate 665*0Sstevel@tonic-gate /* 666*0Sstevel@tonic-gate * PCI Message Signalled Interrupts (MSI) capability masks and shifts 667*0Sstevel@tonic-gate */ 668*0Sstevel@tonic-gate #define PCI_MSI_ENABLE_BIT 0x0001 /* MSI enable mask in MSI ctrl reg */ 669*0Sstevel@tonic-gate #define PCI_MSI_MMC_MASK 0x000E /* MMC mask in MSI ctrl reg */ 670*0Sstevel@tonic-gate #define PCI_MSI_MMC_SHIFT 0x1 /* Shift for MMC bits */ 671*0Sstevel@tonic-gate #define PCI_MSI_MME_MASK 0x0070 /* MME mask in MSI ctrl reg */ 672*0Sstevel@tonic-gate #define PCI_MSI_MME_SHIFT 0x4 /* Shift for MME bits */ 673*0Sstevel@tonic-gate #define PCI_MSI_64BIT_MASK 0x0080 /* 64bit support mask in MSI ctrl reg */ 674*0Sstevel@tonic-gate #define PCI_MSI_PVM_MASK 0x0100 /* PVM support mask in MSI ctrl reg */ 675*0Sstevel@tonic-gate 676*0Sstevel@tonic-gate /* 677*0Sstevel@tonic-gate * PCI Extended Message Signalled Interrupts (MSI-X) capability entry offsets 678*0Sstevel@tonic-gate */ 679*0Sstevel@tonic-gate #define PCI_MSIX_CTRL 0x02 /* MSI-X control register, 2 bytes */ 680*0Sstevel@tonic-gate #define PCI_MSIX_TBL_OFFSET 0x04 /* MSI-X table offset, 4 bytes */ 681*0Sstevel@tonic-gate #define PCI_MSIX_TBL_BIR_MASK 0x0003 /* MSI-X table BIR mask */ 682*0Sstevel@tonic-gate #define PCI_MSIX_PBA_OFFSET 0x0C /* MSI-X pending bit array, 4 bytes */ 683*0Sstevel@tonic-gate #define PCI_MSIX_PBA_BIR_MASK 0x0003 /* MSI-X PBA BIR mask */ 684*0Sstevel@tonic-gate 685*0Sstevel@tonic-gate #define PCI_MSIX_TBL_SIZE_MASK 0x07FF /* table size mask in MSI-X ctrl reg */ 686*0Sstevel@tonic-gate #define PCI_MSIX_FUNCTION_MASK 0x4000 /* function mask in MSI-X ctrl reg */ 687*0Sstevel@tonic-gate #define PCI_MSIX_ENABLE_BIT 0x8000 /* MSI-X enable mask in MSI-X ctl reg */ 688*0Sstevel@tonic-gate 689*0Sstevel@tonic-gate #define PCI_MSIX_LOWER_ADDR_OFFSET 0 /* MSI-X lower addr offset */ 690*0Sstevel@tonic-gate #define PCI_MSIX_UPPER_ADDR_OFFSET 4 /* MSI-X upper addr offset */ 691*0Sstevel@tonic-gate #define PCI_MSIX_DATA_OFFSET 8 /* MSI-X data offset */ 692*0Sstevel@tonic-gate #define PCI_MSIX_VECTOR_CTRL_OFFSET 12 /* MSI-X vector ctrl offset */ 693*0Sstevel@tonic-gate #define PCI_MSIX_VECTOR_SIZE 16 /* MSI-X size of each vector */ 694*0Sstevel@tonic-gate 695*0Sstevel@tonic-gate /* 696*0Sstevel@tonic-gate * PCI Message Signalled Interrupts: other interesting constants 697*0Sstevel@tonic-gate */ 698*0Sstevel@tonic-gate #define PCI_MSI_MAX_INTRS 32 /* maximum MSI interrupts supported */ 699*0Sstevel@tonic-gate #define PCI_MSIX_MAX_INTRS 2048 /* maximum MSI-X interrupts supported */ 700*0Sstevel@tonic-gate 701*0Sstevel@tonic-gate /* 702*0Sstevel@tonic-gate * other interesting PCI constants 703*0Sstevel@tonic-gate */ 704*0Sstevel@tonic-gate #define PCI_BASE_NUM 6 /* num of base regs in configuration header */ 705*0Sstevel@tonic-gate #define PCI_BAR_SZ_32 4 /* size of 32 bit base addr reg in bytes */ 706*0Sstevel@tonic-gate #define PCI_BAR_SZ_64 8 /* size of 64 bit base addr reg in bytes */ 707*0Sstevel@tonic-gate #define PCI_BASE_SIZE 4 /* size of base reg in bytes */ 708*0Sstevel@tonic-gate #define PCI_CONF_HDR_SIZE 256 /* configuration header size */ 709*0Sstevel@tonic-gate #define PCI_CLK_33MHZ (33 * 1000 * 1000) /* 33MHz clock speed */ 710*0Sstevel@tonic-gate #define PCI_CLK_66MHZ (66 * 1000 * 1000) /* 66MHz clock speed */ 711*0Sstevel@tonic-gate #define PCI_CLK_133MHZ (133 * 1000 * 1000) /* 133MHz clock speed */ 712*0Sstevel@tonic-gate 713*0Sstevel@tonic-gate /* 714*0Sstevel@tonic-gate * PCI-Express definitions 715*0Sstevel@tonic-gate */ 716*0Sstevel@tonic-gate #define PCIE_CONF_HDR_SIZE 4096 /* PCI-Ex config header size */ 717*0Sstevel@tonic-gate 718*0Sstevel@tonic-gate /* 719*0Sstevel@tonic-gate * This structure represents one entry of the 1275 "reg" property and 720*0Sstevel@tonic-gate * "assigned-addresses" property for a PCI node. For the "reg" property, it 721*0Sstevel@tonic-gate * may be one of an arbitrary length array for devices with multiple address 722*0Sstevel@tonic-gate * windows. For the "assigned-addresses" property, it denotes an assigned 723*0Sstevel@tonic-gate * physical address on the PCI bus. It may be one entry of the six entries 724*0Sstevel@tonic-gate * for devices with multiple base registers. 725*0Sstevel@tonic-gate * 726*0Sstevel@tonic-gate * The physical address format is: 727*0Sstevel@tonic-gate * 728*0Sstevel@tonic-gate * Bit#: 33222222 22221111 11111100 00000000 729*0Sstevel@tonic-gate * 10987654 32109876 54321098 76543210 730*0Sstevel@tonic-gate * 731*0Sstevel@tonic-gate * pci_phys_hi cell: np0000tt bbbbbbbb dddddfff rrrrrrrr 732*0Sstevel@tonic-gate * pci_phys_mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 733*0Sstevel@tonic-gate * pci_phys_low cell: llllllll llllllll llllllll llllllll 734*0Sstevel@tonic-gate * 735*0Sstevel@tonic-gate * n is 0 if the address is relocatable, 1 otherwise 736*0Sstevel@tonic-gate * p is 1 if the addressable region is "prefetchable", 0 otherwise 737*0Sstevel@tonic-gate * t is 1 if the address range is aliased 738*0Sstevel@tonic-gate * tt is the type code, denoting which address space 739*0Sstevel@tonic-gate * bbbbbbbb is the 8-bit bus number 740*0Sstevel@tonic-gate * ddddd is the 5-bit device number 741*0Sstevel@tonic-gate * fff is the 3-bit function number 742*0Sstevel@tonic-gate * rrrrrrrr is the 8-bit register number 743*0Sstevel@tonic-gate * hh...hhh is the 32-bit unsigned number 744*0Sstevel@tonic-gate * ll...lll is the 32-bit unsigned number 745*0Sstevel@tonic-gate * 746*0Sstevel@tonic-gate * The physical size format is: 747*0Sstevel@tonic-gate * 748*0Sstevel@tonic-gate * pci_size_hi cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh 749*0Sstevel@tonic-gate * pci_size_low cell: llllllll llllllll llllllll llllllll 750*0Sstevel@tonic-gate * 751*0Sstevel@tonic-gate * hh...hhh is the 32-bit unsigned number 752*0Sstevel@tonic-gate * ll...lll is the 32-bit unsigned number 753*0Sstevel@tonic-gate */ 754*0Sstevel@tonic-gate struct pci_phys_spec { 755*0Sstevel@tonic-gate uint_t pci_phys_hi; /* child's address, hi word */ 756*0Sstevel@tonic-gate uint_t pci_phys_mid; /* child's address, middle word */ 757*0Sstevel@tonic-gate uint_t pci_phys_low; /* child's address, low word */ 758*0Sstevel@tonic-gate uint_t pci_size_hi; /* high word of size field */ 759*0Sstevel@tonic-gate uint_t pci_size_low; /* low word of size field */ 760*0Sstevel@tonic-gate }; 761*0Sstevel@tonic-gate 762*0Sstevel@tonic-gate typedef struct pci_phys_spec pci_regspec_t; 763*0Sstevel@tonic-gate 764*0Sstevel@tonic-gate /* 765*0Sstevel@tonic-gate * PCI masks for pci_phy_hi of PCI 1275 address cell. 766*0Sstevel@tonic-gate */ 767*0Sstevel@tonic-gate #define PCI_REG_REG_M 0xff /* register mask */ 768*0Sstevel@tonic-gate #define PCI_REG_FUNC_M 0x700 /* function mask */ 769*0Sstevel@tonic-gate #define PCI_REG_DEV_M 0xf800 /* device mask */ 770*0Sstevel@tonic-gate #define PCI_REG_BUS_M 0xff0000 /* bus number mask */ 771*0Sstevel@tonic-gate #define PCI_REG_ADDR_M 0x3000000 /* address space mask */ 772*0Sstevel@tonic-gate #define PCI_REG_ALIAS_M 0x20000000 /* aliased bit mask */ 773*0Sstevel@tonic-gate #define PCI_REG_PF_M 0x40000000 /* prefetch bit mask */ 774*0Sstevel@tonic-gate #define PCI_REG_REL_M 0x80000000 /* relocation bit mask */ 775*0Sstevel@tonic-gate #define PCI_REG_BDFR_M 0xffffff /* bus, dev, func, reg mask */ 776*0Sstevel@tonic-gate 777*0Sstevel@tonic-gate #define PCI_REG_FUNC_SHIFT 8 /* Offset of function bits */ 778*0Sstevel@tonic-gate #define PCI_REG_DEV_SHIFT 11 /* Offset of device bits */ 779*0Sstevel@tonic-gate #define PCI_REG_BUS_SHIFT 16 /* Offset of bus bits */ 780*0Sstevel@tonic-gate #define PCI_REG_ADDR_SHIFT 24 /* Offset of address bits */ 781*0Sstevel@tonic-gate 782*0Sstevel@tonic-gate #define PCI_REG_REG_G(x) ((x) & PCI_REG_REG_M) 783*0Sstevel@tonic-gate #define PCI_REG_FUNC_G(x) (((x) & PCI_REG_FUNC_M) >> PCI_REG_FUNC_SHIFT) 784*0Sstevel@tonic-gate #define PCI_REG_DEV_G(x) (((x) & PCI_REG_DEV_M) >> PCI_REG_DEV_SHIFT) 785*0Sstevel@tonic-gate #define PCI_REG_BUS_G(x) (((x) & PCI_REG_BUS_M) >> PCI_REG_BUS_SHIFT) 786*0Sstevel@tonic-gate #define PCI_REG_ADDR_G(x) (((x) & PCI_REG_ADDR_M) >> PCI_REG_ADDR_SHIFT) 787*0Sstevel@tonic-gate #define PCI_REG_BDFR_G(x) ((x) & PCI_REG_BDFR_M) 788*0Sstevel@tonic-gate 789*0Sstevel@tonic-gate /* 790*0Sstevel@tonic-gate * PCI bit encodings of pci_phys_hi of PCI 1275 address cell. 791*0Sstevel@tonic-gate */ 792*0Sstevel@tonic-gate #define PCI_ADDR_MASK PCI_REG_ADDR_M 793*0Sstevel@tonic-gate #define PCI_ADDR_CONFIG 0x00000000 /* configuration address */ 794*0Sstevel@tonic-gate #define PCI_ADDR_IO 0x01000000 /* I/O address */ 795*0Sstevel@tonic-gate #define PCI_ADDR_MEM32 0x02000000 /* 32-bit memory address */ 796*0Sstevel@tonic-gate #define PCI_ADDR_MEM64 0x03000000 /* 64-bit memory address */ 797*0Sstevel@tonic-gate #define PCI_ALIAS_B PCI_REG_ALIAS_M /* aliased bit */ 798*0Sstevel@tonic-gate #define PCI_PREFETCH_B PCI_REG_PF_M /* prefetch bit */ 799*0Sstevel@tonic-gate #define PCI_RELOCAT_B PCI_REG_REL_M /* non-relocatable bit */ 800*0Sstevel@tonic-gate #define PCI_CONF_ADDR_MASK 0x00ffffff /* mask for config address */ 801*0Sstevel@tonic-gate 802*0Sstevel@tonic-gate #define PCI_HARDDEC_8514 2 /* number of reg entries for 8514 hard-decode */ 803*0Sstevel@tonic-gate #define PCI_HARDDEC_VGA 3 /* number of reg entries for VGA hard-decode */ 804*0Sstevel@tonic-gate #define PCI_HARDDEC_IDE 4 /* number of reg entries for IDE hard-decode */ 805*0Sstevel@tonic-gate #define PCI_HARDDEC_IDE_PRI 2 /* number of reg entries for IDE primary */ 806*0Sstevel@tonic-gate #define PCI_HARDDEC_IDE_SEC 2 /* number of reg entries for IDE secondary */ 807*0Sstevel@tonic-gate 808*0Sstevel@tonic-gate /* 809*0Sstevel@tonic-gate * PCI Expansion ROM Header Format 810*0Sstevel@tonic-gate */ 811*0Sstevel@tonic-gate #define PCI_ROM_SIGNATURE 0x0 /* ROM Signature 0xaa55 */ 812*0Sstevel@tonic-gate #define PCI_ROM_ARCH_UNIQUE_START 0x2 /* Start of processor unique */ 813*0Sstevel@tonic-gate #define PCI_ROM_PCI_DATA_STRUCT_PTR 0x18 /* Ptr to PCI Data Structure */ 814*0Sstevel@tonic-gate 815*0Sstevel@tonic-gate /* 816*0Sstevel@tonic-gate * PCI Data Structure 817*0Sstevel@tonic-gate * 818*0Sstevel@tonic-gate * The PCI Data Structure is located within the first 64KB 819*0Sstevel@tonic-gate * of the ROM image and must be DWORD aligned. 820*0Sstevel@tonic-gate */ 821*0Sstevel@tonic-gate #define PCI_PDS_SIGNATURE 0x0 /* Signature, the string 'PCIR' */ 822*0Sstevel@tonic-gate #define PCI_PDS_VENDOR_ID 0x4 /* Vendor Identification */ 823*0Sstevel@tonic-gate #define PCI_PDS_DEVICE_ID 0x6 /* Device Identification */ 824*0Sstevel@tonic-gate #define PCI_PDS_VPD_PTR 0x8 /* Pointer to Vital Product Data */ 825*0Sstevel@tonic-gate #define PCI_PDS_PDS_LENGTH 0xa /* PCI Data Structure Length */ 826*0Sstevel@tonic-gate #define PCI_PDS_PDS_REVISION 0xc /* PCI Data Structure Revision */ 827*0Sstevel@tonic-gate #define PCI_PDS_CLASS_CODE 0xd /* Class Code */ 828*0Sstevel@tonic-gate #define PCI_PDS_IMAGE_LENGTH 0x10 /* Image Length in 512 byte units */ 829*0Sstevel@tonic-gate #define PCI_PDS_CODE_REVISON 0x12 /* Revision Level of Code/Data */ 830*0Sstevel@tonic-gate #define PCI_PDS_CODE_TYPE 0x14 /* Code Type */ 831*0Sstevel@tonic-gate #define PCI_PDS_INDICATOR 0x15 /* Indicates if image is last in ROM */ 832*0Sstevel@tonic-gate 833*0Sstevel@tonic-gate #define PCI_PDS_CODE_TYPE_PCAT 0x0 /* Intel x86/PC-AT Type */ 834*0Sstevel@tonic-gate #define PCI_PDS_CODE_TYPE_OPEN_FW 0x1 /* Open Firmware */ 835*0Sstevel@tonic-gate 836*0Sstevel@tonic-gate #ifdef __cplusplus 837*0Sstevel@tonic-gate } 838*0Sstevel@tonic-gate #endif 839*0Sstevel@tonic-gate 840*0Sstevel@tonic-gate #endif /* _SYS_PCI_H */ 841